blob: 951194c1d0a83ddd294468f5405dfff22d25d49d [file] [log] [blame]
Daniel Vetter0a10c852010-03-11 21:19:14 +00001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
Alex Deucherabf1dc62012-07-17 14:02:36 -040043/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
Daniel Vetter0a10c852010-03-11 21:19:14 +000053static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
Alex Deucherabf1dc62012-07-17 14:02:36 -040060/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
Daniel Vetter0a10c852010-03-11 21:19:14 +000070static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
Alex Deucherabf1dc62012-07-17 14:02:36 -040077/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
Daniel Vetter0a10c852010-03-11 21:19:14 +000085static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
Alex Deucherb4df8be2011-04-12 13:40:18 -0400125 if (rdev->family >= CHIP_R600) {
Daniel Vetter0a10c852010-03-11 21:19:14 +0000126 rdev->pciep_rreg = &r600_pciep_rreg;
127 rdev->pciep_wreg = &r600_pciep_wreg;
128 }
129}
130
131
132/* helper to disable agp */
Alex Deucherabf1dc62012-07-17 14:02:36 -0400133/**
134 * radeon_agp_disable - AGP disable helper function
135 *
136 * @rdev: radeon device pointer
137 *
138 * Removes AGP flags and changes the gart callbacks on AGP
139 * cards when using the internal gart rather than AGP (all asics).
140 */
Daniel Vetter0a10c852010-03-11 21:19:14 +0000141void radeon_agp_disable(struct radeon_device *rdev)
142{
143 rdev->flags &= ~RADEON_IS_AGP;
144 if (rdev->family >= CHIP_R600) {
145 DRM_INFO("Forcing AGP to PCIE mode\n");
146 rdev->flags |= RADEON_IS_PCIE;
147 } else if (rdev->family >= CHIP_RV515 ||
148 rdev->family == CHIP_RV380 ||
149 rdev->family == CHIP_RV410 ||
150 rdev->family == CHIP_R423) {
151 DRM_INFO("Forcing AGP to PCIE mode\n");
152 rdev->flags |= RADEON_IS_PCIE;
Alex Deucherc5b3b852012-02-23 17:53:46 -0500153 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
154 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
Daniel Vetter0a10c852010-03-11 21:19:14 +0000155 } else {
156 DRM_INFO("Forcing AGP to PCI mode\n");
157 rdev->flags |= RADEON_IS_PCI;
Alex Deucherc5b3b852012-02-23 17:53:46 -0500158 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
159 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
Daniel Vetter0a10c852010-03-11 21:19:14 +0000160 }
161 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
162}
163
164/*
165 * ASIC
166 */
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000167static struct radeon_asic r100_asic = {
168 .init = &r100_init,
169 .fini = &r100_fini,
170 .suspend = &r100_suspend,
171 .resume = &r100_resume,
172 .vga_set_state = &r100_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000173 .asic_reset = &r100_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500174 .ioctl_wait_idle = NULL,
175 .gui_idle = &r100_gui_idle,
176 .mc_wait_for_idle = &r100_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500177 .gart = {
178 .tlb_flush = &r100_pci_gart_tlb_flush,
179 .set_page = &r100_pci_gart_set_page,
180 },
Christian König4c87bc22011-10-19 19:02:21 +0200181 .ring = {
182 [RADEON_RING_TYPE_GFX_INDEX] = {
183 .ib_execute = &r100_ring_ib_execute,
184 .emit_fence = &r100_fence_ring_emit,
185 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100186 .cs_parse = &r100_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500187 .ring_start = &r100_ring_start,
188 .ring_test = &r100_ring_test,
189 .ib_test = &r100_ib_test,
Christian König312c4a82012-05-02 15:11:09 +0200190 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200191 }
192 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500193 .irq = {
194 .set = &r100_irq_set,
195 .process = &r100_irq_process,
196 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500197 .display = {
198 .bandwidth_update = &r100_bandwidth_update,
199 .get_vblank_counter = &r100_get_vblank_counter,
200 .wait_for_vblank = &r100_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400201 .set_backlight_level = &radeon_legacy_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500202 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500203 .copy = {
204 .blit = &r100_copy_blit,
205 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
206 .dma = NULL,
207 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
208 .copy = &r100_copy_blit,
209 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
210 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500211 .surface = {
212 .set_reg = r100_set_surface_reg,
213 .clear_reg = r100_clear_surface_reg,
214 },
Alex Deucher901ea572012-02-23 17:53:39 -0500215 .hpd = {
216 .init = &r100_hpd_init,
217 .fini = &r100_hpd_fini,
218 .sense = &r100_hpd_sense,
219 .set_polarity = &r100_hpd_set_polarity,
220 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500221 .pm = {
222 .misc = &r100_pm_misc,
223 .prepare = &r100_pm_prepare,
224 .finish = &r100_pm_finish,
225 .init_profile = &r100_pm_init_profile,
226 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500227 .get_engine_clock = &radeon_legacy_get_engine_clock,
228 .set_engine_clock = &radeon_legacy_set_engine_clock,
229 .get_memory_clock = &radeon_legacy_get_memory_clock,
230 .set_memory_clock = NULL,
231 .get_pcie_lanes = NULL,
232 .set_pcie_lanes = NULL,
233 .set_clock_gating = &radeon_legacy_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500234 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500235 .pflip = {
236 .pre_page_flip = &r100_pre_page_flip,
237 .page_flip = &r100_page_flip,
238 .post_page_flip = &r100_post_page_flip,
239 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000240};
241
242static struct radeon_asic r200_asic = {
243 .init = &r100_init,
244 .fini = &r100_fini,
245 .suspend = &r100_suspend,
246 .resume = &r100_resume,
247 .vga_set_state = &r100_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000248 .asic_reset = &r100_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500249 .ioctl_wait_idle = NULL,
250 .gui_idle = &r100_gui_idle,
251 .mc_wait_for_idle = &r100_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500252 .gart = {
253 .tlb_flush = &r100_pci_gart_tlb_flush,
254 .set_page = &r100_pci_gart_set_page,
255 },
Christian König4c87bc22011-10-19 19:02:21 +0200256 .ring = {
257 [RADEON_RING_TYPE_GFX_INDEX] = {
258 .ib_execute = &r100_ring_ib_execute,
259 .emit_fence = &r100_fence_ring_emit,
260 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100261 .cs_parse = &r100_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500262 .ring_start = &r100_ring_start,
263 .ring_test = &r100_ring_test,
264 .ib_test = &r100_ib_test,
Christian König312c4a82012-05-02 15:11:09 +0200265 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200266 }
267 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500268 .irq = {
269 .set = &r100_irq_set,
270 .process = &r100_irq_process,
271 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500272 .display = {
273 .bandwidth_update = &r100_bandwidth_update,
274 .get_vblank_counter = &r100_get_vblank_counter,
275 .wait_for_vblank = &r100_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400276 .set_backlight_level = &radeon_legacy_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500277 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500278 .copy = {
279 .blit = &r100_copy_blit,
280 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
281 .dma = &r200_copy_dma,
282 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
283 .copy = &r100_copy_blit,
284 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
285 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500286 .surface = {
287 .set_reg = r100_set_surface_reg,
288 .clear_reg = r100_clear_surface_reg,
289 },
Alex Deucher901ea572012-02-23 17:53:39 -0500290 .hpd = {
291 .init = &r100_hpd_init,
292 .fini = &r100_hpd_fini,
293 .sense = &r100_hpd_sense,
294 .set_polarity = &r100_hpd_set_polarity,
295 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500296 .pm = {
297 .misc = &r100_pm_misc,
298 .prepare = &r100_pm_prepare,
299 .finish = &r100_pm_finish,
300 .init_profile = &r100_pm_init_profile,
301 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500302 .get_engine_clock = &radeon_legacy_get_engine_clock,
303 .set_engine_clock = &radeon_legacy_set_engine_clock,
304 .get_memory_clock = &radeon_legacy_get_memory_clock,
305 .set_memory_clock = NULL,
306 .get_pcie_lanes = NULL,
307 .set_pcie_lanes = NULL,
308 .set_clock_gating = &radeon_legacy_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500309 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500310 .pflip = {
311 .pre_page_flip = &r100_pre_page_flip,
312 .page_flip = &r100_page_flip,
313 .post_page_flip = &r100_post_page_flip,
314 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000315};
316
317static struct radeon_asic r300_asic = {
318 .init = &r300_init,
319 .fini = &r300_fini,
320 .suspend = &r300_suspend,
321 .resume = &r300_resume,
322 .vga_set_state = &r100_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000323 .asic_reset = &r300_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500324 .ioctl_wait_idle = NULL,
325 .gui_idle = &r100_gui_idle,
326 .mc_wait_for_idle = &r300_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500327 .gart = {
328 .tlb_flush = &r100_pci_gart_tlb_flush,
329 .set_page = &r100_pci_gart_set_page,
330 },
Christian König4c87bc22011-10-19 19:02:21 +0200331 .ring = {
332 [RADEON_RING_TYPE_GFX_INDEX] = {
333 .ib_execute = &r100_ring_ib_execute,
334 .emit_fence = &r300_fence_ring_emit,
335 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100336 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500337 .ring_start = &r300_ring_start,
338 .ring_test = &r100_ring_test,
339 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200340 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200341 }
342 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500343 .irq = {
344 .set = &r100_irq_set,
345 .process = &r100_irq_process,
346 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500347 .display = {
348 .bandwidth_update = &r100_bandwidth_update,
349 .get_vblank_counter = &r100_get_vblank_counter,
350 .wait_for_vblank = &r100_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400351 .set_backlight_level = &radeon_legacy_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500352 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500353 .copy = {
354 .blit = &r100_copy_blit,
355 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
356 .dma = &r200_copy_dma,
357 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
358 .copy = &r100_copy_blit,
359 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
360 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500361 .surface = {
362 .set_reg = r100_set_surface_reg,
363 .clear_reg = r100_clear_surface_reg,
364 },
Alex Deucher901ea572012-02-23 17:53:39 -0500365 .hpd = {
366 .init = &r100_hpd_init,
367 .fini = &r100_hpd_fini,
368 .sense = &r100_hpd_sense,
369 .set_polarity = &r100_hpd_set_polarity,
370 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500371 .pm = {
372 .misc = &r100_pm_misc,
373 .prepare = &r100_pm_prepare,
374 .finish = &r100_pm_finish,
375 .init_profile = &r100_pm_init_profile,
376 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500377 .get_engine_clock = &radeon_legacy_get_engine_clock,
378 .set_engine_clock = &radeon_legacy_set_engine_clock,
379 .get_memory_clock = &radeon_legacy_get_memory_clock,
380 .set_memory_clock = NULL,
381 .get_pcie_lanes = &rv370_get_pcie_lanes,
382 .set_pcie_lanes = &rv370_set_pcie_lanes,
383 .set_clock_gating = &radeon_legacy_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500384 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500385 .pflip = {
386 .pre_page_flip = &r100_pre_page_flip,
387 .page_flip = &r100_page_flip,
388 .post_page_flip = &r100_post_page_flip,
389 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000390};
391
392static struct radeon_asic r300_asic_pcie = {
393 .init = &r300_init,
394 .fini = &r300_fini,
395 .suspend = &r300_suspend,
396 .resume = &r300_resume,
397 .vga_set_state = &r100_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000398 .asic_reset = &r300_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500399 .ioctl_wait_idle = NULL,
400 .gui_idle = &r100_gui_idle,
401 .mc_wait_for_idle = &r300_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500402 .gart = {
403 .tlb_flush = &rv370_pcie_gart_tlb_flush,
404 .set_page = &rv370_pcie_gart_set_page,
405 },
Christian König4c87bc22011-10-19 19:02:21 +0200406 .ring = {
407 [RADEON_RING_TYPE_GFX_INDEX] = {
408 .ib_execute = &r100_ring_ib_execute,
409 .emit_fence = &r300_fence_ring_emit,
410 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100411 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500412 .ring_start = &r300_ring_start,
413 .ring_test = &r100_ring_test,
414 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200415 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200416 }
417 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500418 .irq = {
419 .set = &r100_irq_set,
420 .process = &r100_irq_process,
421 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500422 .display = {
423 .bandwidth_update = &r100_bandwidth_update,
424 .get_vblank_counter = &r100_get_vblank_counter,
425 .wait_for_vblank = &r100_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400426 .set_backlight_level = &radeon_legacy_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500427 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500428 .copy = {
429 .blit = &r100_copy_blit,
430 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
431 .dma = &r200_copy_dma,
432 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
433 .copy = &r100_copy_blit,
434 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
435 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500436 .surface = {
437 .set_reg = r100_set_surface_reg,
438 .clear_reg = r100_clear_surface_reg,
439 },
Alex Deucher901ea572012-02-23 17:53:39 -0500440 .hpd = {
441 .init = &r100_hpd_init,
442 .fini = &r100_hpd_fini,
443 .sense = &r100_hpd_sense,
444 .set_polarity = &r100_hpd_set_polarity,
445 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500446 .pm = {
447 .misc = &r100_pm_misc,
448 .prepare = &r100_pm_prepare,
449 .finish = &r100_pm_finish,
450 .init_profile = &r100_pm_init_profile,
451 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500452 .get_engine_clock = &radeon_legacy_get_engine_clock,
453 .set_engine_clock = &radeon_legacy_set_engine_clock,
454 .get_memory_clock = &radeon_legacy_get_memory_clock,
455 .set_memory_clock = NULL,
456 .get_pcie_lanes = &rv370_get_pcie_lanes,
457 .set_pcie_lanes = &rv370_set_pcie_lanes,
458 .set_clock_gating = &radeon_legacy_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500459 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500460 .pflip = {
461 .pre_page_flip = &r100_pre_page_flip,
462 .page_flip = &r100_page_flip,
463 .post_page_flip = &r100_post_page_flip,
464 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000465};
466
467static struct radeon_asic r420_asic = {
468 .init = &r420_init,
469 .fini = &r420_fini,
470 .suspend = &r420_suspend,
471 .resume = &r420_resume,
472 .vga_set_state = &r100_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000473 .asic_reset = &r300_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500474 .ioctl_wait_idle = NULL,
475 .gui_idle = &r100_gui_idle,
476 .mc_wait_for_idle = &r300_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500477 .gart = {
478 .tlb_flush = &rv370_pcie_gart_tlb_flush,
479 .set_page = &rv370_pcie_gart_set_page,
480 },
Christian König4c87bc22011-10-19 19:02:21 +0200481 .ring = {
482 [RADEON_RING_TYPE_GFX_INDEX] = {
483 .ib_execute = &r100_ring_ib_execute,
484 .emit_fence = &r300_fence_ring_emit,
485 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100486 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500487 .ring_start = &r300_ring_start,
488 .ring_test = &r100_ring_test,
489 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200490 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200491 }
492 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500493 .irq = {
494 .set = &r100_irq_set,
495 .process = &r100_irq_process,
496 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500497 .display = {
498 .bandwidth_update = &r100_bandwidth_update,
499 .get_vblank_counter = &r100_get_vblank_counter,
500 .wait_for_vblank = &r100_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400501 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500502 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500503 .copy = {
504 .blit = &r100_copy_blit,
505 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
506 .dma = &r200_copy_dma,
507 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
508 .copy = &r100_copy_blit,
509 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
510 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500511 .surface = {
512 .set_reg = r100_set_surface_reg,
513 .clear_reg = r100_clear_surface_reg,
514 },
Alex Deucher901ea572012-02-23 17:53:39 -0500515 .hpd = {
516 .init = &r100_hpd_init,
517 .fini = &r100_hpd_fini,
518 .sense = &r100_hpd_sense,
519 .set_polarity = &r100_hpd_set_polarity,
520 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500521 .pm = {
522 .misc = &r100_pm_misc,
523 .prepare = &r100_pm_prepare,
524 .finish = &r100_pm_finish,
525 .init_profile = &r420_pm_init_profile,
526 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500527 .get_engine_clock = &radeon_atom_get_engine_clock,
528 .set_engine_clock = &radeon_atom_set_engine_clock,
529 .get_memory_clock = &radeon_atom_get_memory_clock,
530 .set_memory_clock = &radeon_atom_set_memory_clock,
531 .get_pcie_lanes = &rv370_get_pcie_lanes,
532 .set_pcie_lanes = &rv370_set_pcie_lanes,
533 .set_clock_gating = &radeon_atom_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500534 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500535 .pflip = {
536 .pre_page_flip = &r100_pre_page_flip,
537 .page_flip = &r100_page_flip,
538 .post_page_flip = &r100_post_page_flip,
539 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000540};
541
542static struct radeon_asic rs400_asic = {
543 .init = &rs400_init,
544 .fini = &rs400_fini,
545 .suspend = &rs400_suspend,
546 .resume = &rs400_resume,
547 .vga_set_state = &r100_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000548 .asic_reset = &r300_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500549 .ioctl_wait_idle = NULL,
550 .gui_idle = &r100_gui_idle,
551 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500552 .gart = {
553 .tlb_flush = &rs400_gart_tlb_flush,
554 .set_page = &rs400_gart_set_page,
555 },
Christian König4c87bc22011-10-19 19:02:21 +0200556 .ring = {
557 [RADEON_RING_TYPE_GFX_INDEX] = {
558 .ib_execute = &r100_ring_ib_execute,
559 .emit_fence = &r300_fence_ring_emit,
560 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100561 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500562 .ring_start = &r300_ring_start,
563 .ring_test = &r100_ring_test,
564 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200565 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200566 }
567 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500568 .irq = {
569 .set = &r100_irq_set,
570 .process = &r100_irq_process,
571 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500572 .display = {
573 .bandwidth_update = &r100_bandwidth_update,
574 .get_vblank_counter = &r100_get_vblank_counter,
575 .wait_for_vblank = &r100_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400576 .set_backlight_level = &radeon_legacy_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500577 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500578 .copy = {
579 .blit = &r100_copy_blit,
580 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
581 .dma = &r200_copy_dma,
582 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
583 .copy = &r100_copy_blit,
584 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
585 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500586 .surface = {
587 .set_reg = r100_set_surface_reg,
588 .clear_reg = r100_clear_surface_reg,
589 },
Alex Deucher901ea572012-02-23 17:53:39 -0500590 .hpd = {
591 .init = &r100_hpd_init,
592 .fini = &r100_hpd_fini,
593 .sense = &r100_hpd_sense,
594 .set_polarity = &r100_hpd_set_polarity,
595 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500596 .pm = {
597 .misc = &r100_pm_misc,
598 .prepare = &r100_pm_prepare,
599 .finish = &r100_pm_finish,
600 .init_profile = &r100_pm_init_profile,
601 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500602 .get_engine_clock = &radeon_legacy_get_engine_clock,
603 .set_engine_clock = &radeon_legacy_set_engine_clock,
604 .get_memory_clock = &radeon_legacy_get_memory_clock,
605 .set_memory_clock = NULL,
606 .get_pcie_lanes = NULL,
607 .set_pcie_lanes = NULL,
608 .set_clock_gating = &radeon_legacy_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500609 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500610 .pflip = {
611 .pre_page_flip = &r100_pre_page_flip,
612 .page_flip = &r100_page_flip,
613 .post_page_flip = &r100_post_page_flip,
614 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000615};
616
617static struct radeon_asic rs600_asic = {
618 .init = &rs600_init,
619 .fini = &rs600_fini,
620 .suspend = &rs600_suspend,
621 .resume = &rs600_resume,
622 .vga_set_state = &r100_vga_set_state,
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000623 .asic_reset = &rs600_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500624 .ioctl_wait_idle = NULL,
625 .gui_idle = &r100_gui_idle,
626 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500627 .gart = {
628 .tlb_flush = &rs600_gart_tlb_flush,
629 .set_page = &rs600_gart_set_page,
630 },
Christian König4c87bc22011-10-19 19:02:21 +0200631 .ring = {
632 [RADEON_RING_TYPE_GFX_INDEX] = {
633 .ib_execute = &r100_ring_ib_execute,
634 .emit_fence = &r300_fence_ring_emit,
635 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100636 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500637 .ring_start = &r300_ring_start,
638 .ring_test = &r100_ring_test,
639 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200640 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200641 }
642 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500643 .irq = {
644 .set = &rs600_irq_set,
645 .process = &rs600_irq_process,
646 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500647 .display = {
648 .bandwidth_update = &rs600_bandwidth_update,
649 .get_vblank_counter = &rs600_get_vblank_counter,
650 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400651 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500652 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500653 .copy = {
654 .blit = &r100_copy_blit,
655 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
656 .dma = &r200_copy_dma,
657 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
658 .copy = &r100_copy_blit,
659 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
660 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500661 .surface = {
662 .set_reg = r100_set_surface_reg,
663 .clear_reg = r100_clear_surface_reg,
664 },
Alex Deucher901ea572012-02-23 17:53:39 -0500665 .hpd = {
666 .init = &rs600_hpd_init,
667 .fini = &rs600_hpd_fini,
668 .sense = &rs600_hpd_sense,
669 .set_polarity = &rs600_hpd_set_polarity,
670 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500671 .pm = {
672 .misc = &rs600_pm_misc,
673 .prepare = &rs600_pm_prepare,
674 .finish = &rs600_pm_finish,
675 .init_profile = &r420_pm_init_profile,
676 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500677 .get_engine_clock = &radeon_atom_get_engine_clock,
678 .set_engine_clock = &radeon_atom_set_engine_clock,
679 .get_memory_clock = &radeon_atom_get_memory_clock,
680 .set_memory_clock = &radeon_atom_set_memory_clock,
681 .get_pcie_lanes = NULL,
682 .set_pcie_lanes = NULL,
683 .set_clock_gating = &radeon_atom_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500684 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500685 .pflip = {
686 .pre_page_flip = &rs600_pre_page_flip,
687 .page_flip = &rs600_page_flip,
688 .post_page_flip = &rs600_post_page_flip,
689 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000690};
691
692static struct radeon_asic rs690_asic = {
693 .init = &rs690_init,
694 .fini = &rs690_fini,
695 .suspend = &rs690_suspend,
696 .resume = &rs690_resume,
697 .vga_set_state = &r100_vga_set_state,
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000698 .asic_reset = &rs600_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500699 .ioctl_wait_idle = NULL,
700 .gui_idle = &r100_gui_idle,
701 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500702 .gart = {
703 .tlb_flush = &rs400_gart_tlb_flush,
704 .set_page = &rs400_gart_set_page,
705 },
Christian König4c87bc22011-10-19 19:02:21 +0200706 .ring = {
707 [RADEON_RING_TYPE_GFX_INDEX] = {
708 .ib_execute = &r100_ring_ib_execute,
709 .emit_fence = &r300_fence_ring_emit,
710 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100711 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500712 .ring_start = &r300_ring_start,
713 .ring_test = &r100_ring_test,
714 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200715 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200716 }
717 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500718 .irq = {
719 .set = &rs600_irq_set,
720 .process = &rs600_irq_process,
721 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500722 .display = {
723 .get_vblank_counter = &rs600_get_vblank_counter,
724 .bandwidth_update = &rs690_bandwidth_update,
725 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400726 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500727 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500728 .copy = {
729 .blit = &r100_copy_blit,
730 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
731 .dma = &r200_copy_dma,
732 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
733 .copy = &r200_copy_dma,
734 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
735 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500736 .surface = {
737 .set_reg = r100_set_surface_reg,
738 .clear_reg = r100_clear_surface_reg,
739 },
Alex Deucher901ea572012-02-23 17:53:39 -0500740 .hpd = {
741 .init = &rs600_hpd_init,
742 .fini = &rs600_hpd_fini,
743 .sense = &rs600_hpd_sense,
744 .set_polarity = &rs600_hpd_set_polarity,
745 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500746 .pm = {
747 .misc = &rs600_pm_misc,
748 .prepare = &rs600_pm_prepare,
749 .finish = &rs600_pm_finish,
750 .init_profile = &r420_pm_init_profile,
751 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500752 .get_engine_clock = &radeon_atom_get_engine_clock,
753 .set_engine_clock = &radeon_atom_set_engine_clock,
754 .get_memory_clock = &radeon_atom_get_memory_clock,
755 .set_memory_clock = &radeon_atom_set_memory_clock,
756 .get_pcie_lanes = NULL,
757 .set_pcie_lanes = NULL,
758 .set_clock_gating = &radeon_atom_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500759 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500760 .pflip = {
761 .pre_page_flip = &rs600_pre_page_flip,
762 .page_flip = &rs600_page_flip,
763 .post_page_flip = &rs600_post_page_flip,
764 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000765};
766
767static struct radeon_asic rv515_asic = {
768 .init = &rv515_init,
769 .fini = &rv515_fini,
770 .suspend = &rv515_suspend,
771 .resume = &rv515_resume,
772 .vga_set_state = &r100_vga_set_state,
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000773 .asic_reset = &rs600_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500774 .ioctl_wait_idle = NULL,
775 .gui_idle = &r100_gui_idle,
776 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500777 .gart = {
778 .tlb_flush = &rv370_pcie_gart_tlb_flush,
779 .set_page = &rv370_pcie_gart_set_page,
780 },
Christian König4c87bc22011-10-19 19:02:21 +0200781 .ring = {
782 [RADEON_RING_TYPE_GFX_INDEX] = {
783 .ib_execute = &r100_ring_ib_execute,
784 .emit_fence = &r300_fence_ring_emit,
785 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100786 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500787 .ring_start = &rv515_ring_start,
788 .ring_test = &r100_ring_test,
789 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200790 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200791 }
792 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500793 .irq = {
794 .set = &rs600_irq_set,
795 .process = &rs600_irq_process,
796 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500797 .display = {
798 .get_vblank_counter = &rs600_get_vblank_counter,
799 .bandwidth_update = &rv515_bandwidth_update,
800 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400801 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500802 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500803 .copy = {
804 .blit = &r100_copy_blit,
805 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
806 .dma = &r200_copy_dma,
807 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
808 .copy = &r100_copy_blit,
809 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
810 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500811 .surface = {
812 .set_reg = r100_set_surface_reg,
813 .clear_reg = r100_clear_surface_reg,
814 },
Alex Deucher901ea572012-02-23 17:53:39 -0500815 .hpd = {
816 .init = &rs600_hpd_init,
817 .fini = &rs600_hpd_fini,
818 .sense = &rs600_hpd_sense,
819 .set_polarity = &rs600_hpd_set_polarity,
820 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500821 .pm = {
822 .misc = &rs600_pm_misc,
823 .prepare = &rs600_pm_prepare,
824 .finish = &rs600_pm_finish,
825 .init_profile = &r420_pm_init_profile,
826 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500827 .get_engine_clock = &radeon_atom_get_engine_clock,
828 .set_engine_clock = &radeon_atom_set_engine_clock,
829 .get_memory_clock = &radeon_atom_get_memory_clock,
830 .set_memory_clock = &radeon_atom_set_memory_clock,
831 .get_pcie_lanes = &rv370_get_pcie_lanes,
832 .set_pcie_lanes = &rv370_set_pcie_lanes,
833 .set_clock_gating = &radeon_atom_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500834 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500835 .pflip = {
836 .pre_page_flip = &rs600_pre_page_flip,
837 .page_flip = &rs600_page_flip,
838 .post_page_flip = &rs600_post_page_flip,
839 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000840};
841
842static struct radeon_asic r520_asic = {
843 .init = &r520_init,
844 .fini = &rv515_fini,
845 .suspend = &rv515_suspend,
846 .resume = &r520_resume,
847 .vga_set_state = &r100_vga_set_state,
Jerome Glisse90aca4d2010-03-09 14:45:12 +0000848 .asic_reset = &rs600_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500849 .ioctl_wait_idle = NULL,
850 .gui_idle = &r100_gui_idle,
851 .mc_wait_for_idle = &r520_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500852 .gart = {
853 .tlb_flush = &rv370_pcie_gart_tlb_flush,
854 .set_page = &rv370_pcie_gart_set_page,
855 },
Christian König4c87bc22011-10-19 19:02:21 +0200856 .ring = {
857 [RADEON_RING_TYPE_GFX_INDEX] = {
858 .ib_execute = &r100_ring_ib_execute,
859 .emit_fence = &r300_fence_ring_emit,
860 .emit_semaphore = &r100_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100861 .cs_parse = &r300_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500862 .ring_start = &rv515_ring_start,
863 .ring_test = &r100_ring_test,
864 .ib_test = &r100_ib_test,
Christian König8ba957b52012-05-02 15:11:24 +0200865 .is_lockup = &r100_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200866 }
867 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500868 .irq = {
869 .set = &rs600_irq_set,
870 .process = &rs600_irq_process,
871 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500872 .display = {
873 .bandwidth_update = &rv515_bandwidth_update,
874 .get_vblank_counter = &rs600_get_vblank_counter,
875 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400876 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500877 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500878 .copy = {
879 .blit = &r100_copy_blit,
880 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
881 .dma = &r200_copy_dma,
882 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
883 .copy = &r100_copy_blit,
884 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
885 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500886 .surface = {
887 .set_reg = r100_set_surface_reg,
888 .clear_reg = r100_clear_surface_reg,
889 },
Alex Deucher901ea572012-02-23 17:53:39 -0500890 .hpd = {
891 .init = &rs600_hpd_init,
892 .fini = &rs600_hpd_fini,
893 .sense = &rs600_hpd_sense,
894 .set_polarity = &rs600_hpd_set_polarity,
895 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500896 .pm = {
897 .misc = &rs600_pm_misc,
898 .prepare = &rs600_pm_prepare,
899 .finish = &rs600_pm_finish,
900 .init_profile = &r420_pm_init_profile,
901 .get_dynpm_state = &r100_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500902 .get_engine_clock = &radeon_atom_get_engine_clock,
903 .set_engine_clock = &radeon_atom_set_engine_clock,
904 .get_memory_clock = &radeon_atom_get_memory_clock,
905 .set_memory_clock = &radeon_atom_set_memory_clock,
906 .get_pcie_lanes = &rv370_get_pcie_lanes,
907 .set_pcie_lanes = &rv370_set_pcie_lanes,
908 .set_clock_gating = &radeon_atom_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -0500909 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500910 .pflip = {
911 .pre_page_flip = &rs600_pre_page_flip,
912 .page_flip = &rs600_page_flip,
913 .post_page_flip = &rs600_post_page_flip,
914 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000915};
916
917static struct radeon_asic r600_asic = {
918 .init = &r600_init,
919 .fini = &r600_fini,
920 .suspend = &r600_suspend,
921 .resume = &r600_resume,
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000922 .vga_set_state = &r600_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000923 .asic_reset = &r600_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500924 .ioctl_wait_idle = r600_ioctl_wait_idle,
925 .gui_idle = &r600_gui_idle,
926 .mc_wait_for_idle = &r600_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -0500927 .gart = {
928 .tlb_flush = &r600_pcie_gart_tlb_flush,
929 .set_page = &rs600_gart_set_page,
930 },
Christian König4c87bc22011-10-19 19:02:21 +0200931 .ring = {
932 [RADEON_RING_TYPE_GFX_INDEX] = {
933 .ib_execute = &r600_ring_ib_execute,
934 .emit_fence = &r600_fence_ring_emit,
935 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +0100936 .cs_parse = &r600_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -0500937 .ring_test = &r600_ring_test,
938 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +0200939 .is_lockup = &r600_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +0200940 }
941 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -0500942 .irq = {
943 .set = &r600_irq_set,
944 .process = &r600_irq_process,
945 },
Alex Deucherc79a49c2012-02-23 17:53:47 -0500946 .display = {
947 .bandwidth_update = &rv515_bandwidth_update,
948 .get_vblank_counter = &rs600_get_vblank_counter,
949 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -0400950 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -0500951 },
Alex Deucher27cd7762012-02-23 17:53:42 -0500952 .copy = {
953 .blit = &r600_copy_blit,
954 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
955 .dma = NULL,
956 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
957 .copy = &r600_copy_blit,
958 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
959 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -0500960 .surface = {
961 .set_reg = r600_set_surface_reg,
962 .clear_reg = r600_clear_surface_reg,
963 },
Alex Deucher901ea572012-02-23 17:53:39 -0500964 .hpd = {
965 .init = &r600_hpd_init,
966 .fini = &r600_hpd_fini,
967 .sense = &r600_hpd_sense,
968 .set_polarity = &r600_hpd_set_polarity,
969 },
Alex Deuchera02fa392012-02-23 17:53:41 -0500970 .pm = {
971 .misc = &r600_pm_misc,
972 .prepare = &rs600_pm_prepare,
973 .finish = &rs600_pm_finish,
974 .init_profile = &r600_pm_init_profile,
975 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -0500976 .get_engine_clock = &radeon_atom_get_engine_clock,
977 .set_engine_clock = &radeon_atom_set_engine_clock,
978 .get_memory_clock = &radeon_atom_get_memory_clock,
979 .set_memory_clock = &radeon_atom_set_memory_clock,
980 .get_pcie_lanes = &r600_get_pcie_lanes,
981 .set_pcie_lanes = &r600_set_pcie_lanes,
982 .set_clock_gating = NULL,
Alex Deuchera02fa392012-02-23 17:53:41 -0500983 },
Alex Deucher0f9e0062012-02-23 17:53:40 -0500984 .pflip = {
985 .pre_page_flip = &rs600_pre_page_flip,
986 .page_flip = &rs600_page_flip,
987 .post_page_flip = &rs600_post_page_flip,
988 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +0000989};
990
Alex Deucherf47299c2010-03-16 20:54:38 -0400991static struct radeon_asic rs780_asic = {
992 .init = &r600_init,
993 .fini = &r600_fini,
994 .suspend = &r600_suspend,
995 .resume = &r600_resume,
Alex Deucherf47299c2010-03-16 20:54:38 -0400996 .vga_set_state = &r600_vga_set_state,
Jerome Glissea2d07b72010-03-09 14:45:11 +0000997 .asic_reset = &r600_asic_reset,
Alex Deucher54e88e02012-02-23 18:10:29 -0500998 .ioctl_wait_idle = r600_ioctl_wait_idle,
999 .gui_idle = &r600_gui_idle,
1000 .mc_wait_for_idle = &r600_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -05001001 .gart = {
1002 .tlb_flush = &r600_pcie_gart_tlb_flush,
1003 .set_page = &rs600_gart_set_page,
1004 },
Christian König4c87bc22011-10-19 19:02:21 +02001005 .ring = {
1006 [RADEON_RING_TYPE_GFX_INDEX] = {
1007 .ib_execute = &r600_ring_ib_execute,
1008 .emit_fence = &r600_fence_ring_emit,
1009 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001010 .cs_parse = &r600_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001011 .ring_test = &r600_ring_test,
1012 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001013 .is_lockup = &r600_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +02001014 }
1015 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001016 .irq = {
1017 .set = &r600_irq_set,
1018 .process = &r600_irq_process,
1019 },
Alex Deucherc79a49c2012-02-23 17:53:47 -05001020 .display = {
1021 .bandwidth_update = &rs690_bandwidth_update,
1022 .get_vblank_counter = &rs600_get_vblank_counter,
1023 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001024 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -05001025 },
Alex Deucher27cd7762012-02-23 17:53:42 -05001026 .copy = {
1027 .blit = &r600_copy_blit,
1028 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1029 .dma = NULL,
1030 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1031 .copy = &r600_copy_blit,
1032 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1033 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001034 .surface = {
1035 .set_reg = r600_set_surface_reg,
1036 .clear_reg = r600_clear_surface_reg,
1037 },
Alex Deucher901ea572012-02-23 17:53:39 -05001038 .hpd = {
1039 .init = &r600_hpd_init,
1040 .fini = &r600_hpd_fini,
1041 .sense = &r600_hpd_sense,
1042 .set_polarity = &r600_hpd_set_polarity,
1043 },
Alex Deuchera02fa392012-02-23 17:53:41 -05001044 .pm = {
1045 .misc = &r600_pm_misc,
1046 .prepare = &rs600_pm_prepare,
1047 .finish = &rs600_pm_finish,
1048 .init_profile = &rs780_pm_init_profile,
1049 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -05001050 .get_engine_clock = &radeon_atom_get_engine_clock,
1051 .set_engine_clock = &radeon_atom_set_engine_clock,
1052 .get_memory_clock = NULL,
1053 .set_memory_clock = NULL,
1054 .get_pcie_lanes = NULL,
1055 .set_pcie_lanes = NULL,
1056 .set_clock_gating = NULL,
Alex Deuchera02fa392012-02-23 17:53:41 -05001057 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001058 .pflip = {
1059 .pre_page_flip = &rs600_pre_page_flip,
1060 .page_flip = &rs600_page_flip,
1061 .post_page_flip = &rs600_post_page_flip,
1062 },
Alex Deucherf47299c2010-03-16 20:54:38 -04001063};
1064
Daniel Vetter48e7a5f2010-03-11 21:19:15 +00001065static struct radeon_asic rv770_asic = {
1066 .init = &rv770_init,
1067 .fini = &rv770_fini,
1068 .suspend = &rv770_suspend,
1069 .resume = &rv770_resume,
Jerome Glissea2d07b72010-03-09 14:45:11 +00001070 .asic_reset = &r600_asic_reset,
Daniel Vetter48e7a5f2010-03-11 21:19:15 +00001071 .vga_set_state = &r600_vga_set_state,
Alex Deucher54e88e02012-02-23 18:10:29 -05001072 .ioctl_wait_idle = r600_ioctl_wait_idle,
1073 .gui_idle = &r600_gui_idle,
1074 .mc_wait_for_idle = &r600_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -05001075 .gart = {
1076 .tlb_flush = &r600_pcie_gart_tlb_flush,
1077 .set_page = &rs600_gart_set_page,
1078 },
Christian König4c87bc22011-10-19 19:02:21 +02001079 .ring = {
1080 [RADEON_RING_TYPE_GFX_INDEX] = {
1081 .ib_execute = &r600_ring_ib_execute,
1082 .emit_fence = &r600_fence_ring_emit,
1083 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001084 .cs_parse = &r600_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001085 .ring_test = &r600_ring_test,
1086 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001087 .is_lockup = &r600_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +02001088 }
1089 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001090 .irq = {
1091 .set = &r600_irq_set,
1092 .process = &r600_irq_process,
1093 },
Alex Deucherc79a49c2012-02-23 17:53:47 -05001094 .display = {
1095 .bandwidth_update = &rv515_bandwidth_update,
1096 .get_vblank_counter = &rs600_get_vblank_counter,
1097 .wait_for_vblank = &avivo_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001098 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -05001099 },
Alex Deucher27cd7762012-02-23 17:53:42 -05001100 .copy = {
1101 .blit = &r600_copy_blit,
1102 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1103 .dma = NULL,
1104 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1105 .copy = &r600_copy_blit,
1106 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1107 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001108 .surface = {
1109 .set_reg = r600_set_surface_reg,
1110 .clear_reg = r600_clear_surface_reg,
1111 },
Alex Deucher901ea572012-02-23 17:53:39 -05001112 .hpd = {
1113 .init = &r600_hpd_init,
1114 .fini = &r600_hpd_fini,
1115 .sense = &r600_hpd_sense,
1116 .set_polarity = &r600_hpd_set_polarity,
1117 },
Alex Deuchera02fa392012-02-23 17:53:41 -05001118 .pm = {
1119 .misc = &rv770_pm_misc,
1120 .prepare = &rs600_pm_prepare,
1121 .finish = &rs600_pm_finish,
1122 .init_profile = &r600_pm_init_profile,
1123 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -05001124 .get_engine_clock = &radeon_atom_get_engine_clock,
1125 .set_engine_clock = &radeon_atom_set_engine_clock,
1126 .get_memory_clock = &radeon_atom_get_memory_clock,
1127 .set_memory_clock = &radeon_atom_set_memory_clock,
1128 .get_pcie_lanes = &r600_get_pcie_lanes,
1129 .set_pcie_lanes = &r600_set_pcie_lanes,
1130 .set_clock_gating = &radeon_atom_set_clock_gating,
Alex Deuchera02fa392012-02-23 17:53:41 -05001131 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001132 .pflip = {
1133 .pre_page_flip = &rs600_pre_page_flip,
1134 .page_flip = &rv770_page_flip,
1135 .post_page_flip = &rs600_post_page_flip,
1136 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +00001137};
1138
1139static struct radeon_asic evergreen_asic = {
1140 .init = &evergreen_init,
1141 .fini = &evergreen_fini,
1142 .suspend = &evergreen_suspend,
1143 .resume = &evergreen_resume,
Jerome Glissea2d07b72010-03-09 14:45:11 +00001144 .asic_reset = &evergreen_asic_reset,
Daniel Vetter48e7a5f2010-03-11 21:19:15 +00001145 .vga_set_state = &r600_vga_set_state,
Alex Deucher54e88e02012-02-23 18:10:29 -05001146 .ioctl_wait_idle = r600_ioctl_wait_idle,
1147 .gui_idle = &r600_gui_idle,
1148 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -05001149 .gart = {
1150 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1151 .set_page = &rs600_gart_set_page,
1152 },
Christian König4c87bc22011-10-19 19:02:21 +02001153 .ring = {
1154 [RADEON_RING_TYPE_GFX_INDEX] = {
1155 .ib_execute = &evergreen_ring_ib_execute,
1156 .emit_fence = &r600_fence_ring_emit,
1157 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001158 .cs_parse = &evergreen_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001159 .ring_test = &r600_ring_test,
1160 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001161 .is_lockup = &evergreen_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +02001162 }
1163 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001164 .irq = {
1165 .set = &evergreen_irq_set,
1166 .process = &evergreen_irq_process,
1167 },
Alex Deucherc79a49c2012-02-23 17:53:47 -05001168 .display = {
1169 .bandwidth_update = &evergreen_bandwidth_update,
1170 .get_vblank_counter = &evergreen_get_vblank_counter,
1171 .wait_for_vblank = &dce4_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001172 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -05001173 },
Alex Deucher27cd7762012-02-23 17:53:42 -05001174 .copy = {
1175 .blit = &r600_copy_blit,
1176 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1177 .dma = NULL,
1178 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1179 .copy = &r600_copy_blit,
1180 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1181 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001182 .surface = {
1183 .set_reg = r600_set_surface_reg,
1184 .clear_reg = r600_clear_surface_reg,
1185 },
Alex Deucher901ea572012-02-23 17:53:39 -05001186 .hpd = {
1187 .init = &evergreen_hpd_init,
1188 .fini = &evergreen_hpd_fini,
1189 .sense = &evergreen_hpd_sense,
1190 .set_polarity = &evergreen_hpd_set_polarity,
1191 },
Alex Deuchera02fa392012-02-23 17:53:41 -05001192 .pm = {
1193 .misc = &evergreen_pm_misc,
1194 .prepare = &evergreen_pm_prepare,
1195 .finish = &evergreen_pm_finish,
1196 .init_profile = &r600_pm_init_profile,
1197 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -05001198 .get_engine_clock = &radeon_atom_get_engine_clock,
1199 .set_engine_clock = &radeon_atom_set_engine_clock,
1200 .get_memory_clock = &radeon_atom_get_memory_clock,
1201 .set_memory_clock = &radeon_atom_set_memory_clock,
1202 .get_pcie_lanes = &r600_get_pcie_lanes,
1203 .set_pcie_lanes = &r600_set_pcie_lanes,
1204 .set_clock_gating = NULL,
Alex Deuchera02fa392012-02-23 17:53:41 -05001205 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001206 .pflip = {
1207 .pre_page_flip = &evergreen_pre_page_flip,
1208 .page_flip = &evergreen_page_flip,
1209 .post_page_flip = &evergreen_post_page_flip,
1210 },
Daniel Vetter48e7a5f2010-03-11 21:19:15 +00001211};
1212
Alex Deucher958261d2010-11-22 17:56:30 -05001213static struct radeon_asic sumo_asic = {
1214 .init = &evergreen_init,
1215 .fini = &evergreen_fini,
1216 .suspend = &evergreen_suspend,
1217 .resume = &evergreen_resume,
Alex Deucher958261d2010-11-22 17:56:30 -05001218 .asic_reset = &evergreen_asic_reset,
1219 .vga_set_state = &r600_vga_set_state,
Alex Deucher54e88e02012-02-23 18:10:29 -05001220 .ioctl_wait_idle = r600_ioctl_wait_idle,
1221 .gui_idle = &r600_gui_idle,
1222 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -05001223 .gart = {
1224 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1225 .set_page = &rs600_gart_set_page,
1226 },
Christian König4c87bc22011-10-19 19:02:21 +02001227 .ring = {
1228 [RADEON_RING_TYPE_GFX_INDEX] = {
1229 .ib_execute = &evergreen_ring_ib_execute,
1230 .emit_fence = &r600_fence_ring_emit,
1231 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001232 .cs_parse = &evergreen_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001233 .ring_test = &r600_ring_test,
1234 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001235 .is_lockup = &evergreen_gpu_is_lockup,
Christian Königeb0c19c2012-02-23 15:18:44 +01001236 },
Christian König4c87bc22011-10-19 19:02:21 +02001237 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001238 .irq = {
1239 .set = &evergreen_irq_set,
1240 .process = &evergreen_irq_process,
1241 },
Alex Deucherc79a49c2012-02-23 17:53:47 -05001242 .display = {
1243 .bandwidth_update = &evergreen_bandwidth_update,
1244 .get_vblank_counter = &evergreen_get_vblank_counter,
1245 .wait_for_vblank = &dce4_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001246 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -05001247 },
Alex Deucher27cd7762012-02-23 17:53:42 -05001248 .copy = {
1249 .blit = &r600_copy_blit,
1250 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1251 .dma = NULL,
1252 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1253 .copy = &r600_copy_blit,
1254 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1255 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001256 .surface = {
1257 .set_reg = r600_set_surface_reg,
1258 .clear_reg = r600_clear_surface_reg,
1259 },
Alex Deucher901ea572012-02-23 17:53:39 -05001260 .hpd = {
1261 .init = &evergreen_hpd_init,
1262 .fini = &evergreen_hpd_fini,
1263 .sense = &evergreen_hpd_sense,
1264 .set_polarity = &evergreen_hpd_set_polarity,
1265 },
Alex Deuchera02fa392012-02-23 17:53:41 -05001266 .pm = {
1267 .misc = &evergreen_pm_misc,
1268 .prepare = &evergreen_pm_prepare,
1269 .finish = &evergreen_pm_finish,
1270 .init_profile = &sumo_pm_init_profile,
1271 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -05001272 .get_engine_clock = &radeon_atom_get_engine_clock,
1273 .set_engine_clock = &radeon_atom_set_engine_clock,
1274 .get_memory_clock = NULL,
1275 .set_memory_clock = NULL,
1276 .get_pcie_lanes = NULL,
1277 .set_pcie_lanes = NULL,
1278 .set_clock_gating = NULL,
Alex Deuchera02fa392012-02-23 17:53:41 -05001279 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001280 .pflip = {
1281 .pre_page_flip = &evergreen_pre_page_flip,
1282 .page_flip = &evergreen_page_flip,
1283 .post_page_flip = &evergreen_post_page_flip,
1284 },
Alex Deucher958261d2010-11-22 17:56:30 -05001285};
1286
Alex Deuchera43b7662011-01-06 21:19:33 -05001287static struct radeon_asic btc_asic = {
1288 .init = &evergreen_init,
1289 .fini = &evergreen_fini,
1290 .suspend = &evergreen_suspend,
1291 .resume = &evergreen_resume,
Alex Deuchera43b7662011-01-06 21:19:33 -05001292 .asic_reset = &evergreen_asic_reset,
1293 .vga_set_state = &r600_vga_set_state,
Alex Deucher54e88e02012-02-23 18:10:29 -05001294 .ioctl_wait_idle = r600_ioctl_wait_idle,
1295 .gui_idle = &r600_gui_idle,
1296 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -05001297 .gart = {
1298 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1299 .set_page = &rs600_gart_set_page,
1300 },
Christian König4c87bc22011-10-19 19:02:21 +02001301 .ring = {
1302 [RADEON_RING_TYPE_GFX_INDEX] = {
1303 .ib_execute = &evergreen_ring_ib_execute,
1304 .emit_fence = &r600_fence_ring_emit,
1305 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001306 .cs_parse = &evergreen_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001307 .ring_test = &r600_ring_test,
1308 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001309 .is_lockup = &evergreen_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +02001310 }
1311 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001312 .irq = {
1313 .set = &evergreen_irq_set,
1314 .process = &evergreen_irq_process,
1315 },
Alex Deucherc79a49c2012-02-23 17:53:47 -05001316 .display = {
1317 .bandwidth_update = &evergreen_bandwidth_update,
1318 .get_vblank_counter = &evergreen_get_vblank_counter,
1319 .wait_for_vblank = &dce4_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001320 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -05001321 },
Alex Deucher27cd7762012-02-23 17:53:42 -05001322 .copy = {
1323 .blit = &r600_copy_blit,
1324 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1325 .dma = NULL,
1326 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1327 .copy = &r600_copy_blit,
1328 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1329 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001330 .surface = {
1331 .set_reg = r600_set_surface_reg,
1332 .clear_reg = r600_clear_surface_reg,
1333 },
Alex Deucher901ea572012-02-23 17:53:39 -05001334 .hpd = {
1335 .init = &evergreen_hpd_init,
1336 .fini = &evergreen_hpd_fini,
1337 .sense = &evergreen_hpd_sense,
1338 .set_polarity = &evergreen_hpd_set_polarity,
1339 },
Alex Deuchera02fa392012-02-23 17:53:41 -05001340 .pm = {
1341 .misc = &evergreen_pm_misc,
1342 .prepare = &evergreen_pm_prepare,
1343 .finish = &evergreen_pm_finish,
1344 .init_profile = &r600_pm_init_profile,
1345 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -05001346 .get_engine_clock = &radeon_atom_get_engine_clock,
1347 .set_engine_clock = &radeon_atom_set_engine_clock,
1348 .get_memory_clock = &radeon_atom_get_memory_clock,
1349 .set_memory_clock = &radeon_atom_set_memory_clock,
1350 .get_pcie_lanes = NULL,
1351 .set_pcie_lanes = NULL,
1352 .set_clock_gating = NULL,
Alex Deuchera02fa392012-02-23 17:53:41 -05001353 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001354 .pflip = {
1355 .pre_page_flip = &evergreen_pre_page_flip,
1356 .page_flip = &evergreen_page_flip,
1357 .post_page_flip = &evergreen_post_page_flip,
1358 },
Alex Deuchera43b7662011-01-06 21:19:33 -05001359};
1360
Alex Deuchere3487622011-03-02 20:07:36 -05001361static struct radeon_asic cayman_asic = {
1362 .init = &cayman_init,
1363 .fini = &cayman_fini,
1364 .suspend = &cayman_suspend,
1365 .resume = &cayman_resume,
Alex Deuchere3487622011-03-02 20:07:36 -05001366 .asic_reset = &cayman_asic_reset,
1367 .vga_set_state = &r600_vga_set_state,
Alex Deucher54e88e02012-02-23 18:10:29 -05001368 .ioctl_wait_idle = r600_ioctl_wait_idle,
1369 .gui_idle = &r600_gui_idle,
1370 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
Alex Deucherc5b3b852012-02-23 17:53:46 -05001371 .gart = {
1372 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1373 .set_page = &rs600_gart_set_page,
1374 },
Christian König05b07142012-08-06 20:21:10 +02001375 .vm = {
1376 .init = &cayman_vm_init,
1377 .fini = &cayman_vm_fini,
1378 .bind = &cayman_vm_bind,
1379 .unbind = &cayman_vm_unbind,
1380 .tlb_flush = &cayman_vm_tlb_flush,
1381 .page_flags = &cayman_vm_page_flags,
1382 .set_page = &cayman_vm_set_page,
1383 },
Christian König4c87bc22011-10-19 19:02:21 +02001384 .ring = {
1385 [RADEON_RING_TYPE_GFX_INDEX] = {
Jerome Glisse721604a2012-01-05 22:11:05 -05001386 .ib_execute = &cayman_ring_ib_execute,
1387 .ib_parse = &evergreen_ib_parse,
Alex Deucherb40e7e12011-11-17 14:57:50 -05001388 .emit_fence = &cayman_fence_ring_emit,
Christian König4c87bc22011-10-19 19:02:21 +02001389 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001390 .cs_parse = &evergreen_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001391 .ring_test = &r600_ring_test,
1392 .ib_test = &r600_ib_test,
Christian Königabfaa442012-05-02 15:11:25 +02001393 .is_lockup = &evergreen_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +02001394 },
1395 [CAYMAN_RING_TYPE_CP1_INDEX] = {
Jerome Glisse721604a2012-01-05 22:11:05 -05001396 .ib_execute = &cayman_ring_ib_execute,
1397 .ib_parse = &evergreen_ib_parse,
Alex Deucherb40e7e12011-11-17 14:57:50 -05001398 .emit_fence = &cayman_fence_ring_emit,
Christian König4c87bc22011-10-19 19:02:21 +02001399 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001400 .cs_parse = &evergreen_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001401 .ring_test = &r600_ring_test,
1402 .ib_test = &r600_ib_test,
Christian Königabfaa442012-05-02 15:11:25 +02001403 .is_lockup = &evergreen_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +02001404 },
1405 [CAYMAN_RING_TYPE_CP2_INDEX] = {
Jerome Glisse721604a2012-01-05 22:11:05 -05001406 .ib_execute = &cayman_ring_ib_execute,
1407 .ib_parse = &evergreen_ib_parse,
Alex Deucherb40e7e12011-11-17 14:57:50 -05001408 .emit_fence = &cayman_fence_ring_emit,
Christian König4c87bc22011-10-19 19:02:21 +02001409 .emit_semaphore = &r600_semaphore_ring_emit,
Christian Königeb0c19c2012-02-23 15:18:44 +01001410 .cs_parse = &evergreen_cs_parse,
Alex Deucherf7128122012-02-23 17:53:45 -05001411 .ring_test = &r600_ring_test,
1412 .ib_test = &r600_ib_test,
Christian Königabfaa442012-05-02 15:11:25 +02001413 .is_lockup = &evergreen_gpu_is_lockup,
Christian König4c87bc22011-10-19 19:02:21 +02001414 }
1415 },
Alex Deucherb35ea4a2012-02-23 17:53:43 -05001416 .irq = {
1417 .set = &evergreen_irq_set,
1418 .process = &evergreen_irq_process,
1419 },
Alex Deucherc79a49c2012-02-23 17:53:47 -05001420 .display = {
1421 .bandwidth_update = &evergreen_bandwidth_update,
1422 .get_vblank_counter = &evergreen_get_vblank_counter,
1423 .wait_for_vblank = &dce4_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001424 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherc79a49c2012-02-23 17:53:47 -05001425 },
Alex Deucher27cd7762012-02-23 17:53:42 -05001426 .copy = {
1427 .blit = &r600_copy_blit,
1428 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1429 .dma = NULL,
1430 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1431 .copy = &r600_copy_blit,
1432 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1433 },
Alex Deucher9e6f3d02012-02-23 17:53:49 -05001434 .surface = {
1435 .set_reg = r600_set_surface_reg,
1436 .clear_reg = r600_clear_surface_reg,
1437 },
Alex Deucher901ea572012-02-23 17:53:39 -05001438 .hpd = {
1439 .init = &evergreen_hpd_init,
1440 .fini = &evergreen_hpd_fini,
1441 .sense = &evergreen_hpd_sense,
1442 .set_polarity = &evergreen_hpd_set_polarity,
1443 },
Alex Deuchera02fa392012-02-23 17:53:41 -05001444 .pm = {
1445 .misc = &evergreen_pm_misc,
1446 .prepare = &evergreen_pm_prepare,
1447 .finish = &evergreen_pm_finish,
1448 .init_profile = &r600_pm_init_profile,
1449 .get_dynpm_state = &r600_pm_get_dynpm_state,
Alex Deucher798bcf72012-02-23 17:53:48 -05001450 .get_engine_clock = &radeon_atom_get_engine_clock,
1451 .set_engine_clock = &radeon_atom_set_engine_clock,
1452 .get_memory_clock = &radeon_atom_get_memory_clock,
1453 .set_memory_clock = &radeon_atom_set_memory_clock,
1454 .get_pcie_lanes = NULL,
1455 .set_pcie_lanes = NULL,
1456 .set_clock_gating = NULL,
Alex Deuchera02fa392012-02-23 17:53:41 -05001457 },
Alex Deucher0f9e0062012-02-23 17:53:40 -05001458 .pflip = {
1459 .pre_page_flip = &evergreen_pre_page_flip,
1460 .page_flip = &evergreen_page_flip,
1461 .post_page_flip = &evergreen_post_page_flip,
1462 },
Alex Deuchere3487622011-03-02 20:07:36 -05001463};
1464
Alex Deucherbe63fe82012-03-20 17:18:40 -04001465static struct radeon_asic trinity_asic = {
1466 .init = &cayman_init,
1467 .fini = &cayman_fini,
1468 .suspend = &cayman_suspend,
1469 .resume = &cayman_resume,
Alex Deucherbe63fe82012-03-20 17:18:40 -04001470 .asic_reset = &cayman_asic_reset,
1471 .vga_set_state = &r600_vga_set_state,
1472 .ioctl_wait_idle = r600_ioctl_wait_idle,
1473 .gui_idle = &r600_gui_idle,
1474 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1475 .gart = {
1476 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1477 .set_page = &rs600_gart_set_page,
1478 },
Christian König05b07142012-08-06 20:21:10 +02001479 .vm = {
1480 .init = &cayman_vm_init,
1481 .fini = &cayman_vm_fini,
1482 .bind = &cayman_vm_bind,
1483 .unbind = &cayman_vm_unbind,
1484 .tlb_flush = &cayman_vm_tlb_flush,
1485 .page_flags = &cayman_vm_page_flags,
1486 .set_page = &cayman_vm_set_page,
1487 },
Alex Deucherbe63fe82012-03-20 17:18:40 -04001488 .ring = {
1489 [RADEON_RING_TYPE_GFX_INDEX] = {
1490 .ib_execute = &cayman_ring_ib_execute,
1491 .ib_parse = &evergreen_ib_parse,
1492 .emit_fence = &cayman_fence_ring_emit,
1493 .emit_semaphore = &r600_semaphore_ring_emit,
1494 .cs_parse = &evergreen_cs_parse,
1495 .ring_test = &r600_ring_test,
1496 .ib_test = &r600_ib_test,
Christian Königabfaa442012-05-02 15:11:25 +02001497 .is_lockup = &evergreen_gpu_is_lockup,
Alex Deucherbe63fe82012-03-20 17:18:40 -04001498 },
1499 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1500 .ib_execute = &cayman_ring_ib_execute,
1501 .ib_parse = &evergreen_ib_parse,
1502 .emit_fence = &cayman_fence_ring_emit,
1503 .emit_semaphore = &r600_semaphore_ring_emit,
1504 .cs_parse = &evergreen_cs_parse,
1505 .ring_test = &r600_ring_test,
1506 .ib_test = &r600_ib_test,
Christian Königabfaa442012-05-02 15:11:25 +02001507 .is_lockup = &evergreen_gpu_is_lockup,
Alex Deucherbe63fe82012-03-20 17:18:40 -04001508 },
1509 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1510 .ib_execute = &cayman_ring_ib_execute,
1511 .ib_parse = &evergreen_ib_parse,
1512 .emit_fence = &cayman_fence_ring_emit,
1513 .emit_semaphore = &r600_semaphore_ring_emit,
1514 .cs_parse = &evergreen_cs_parse,
1515 .ring_test = &r600_ring_test,
1516 .ib_test = &r600_ib_test,
Christian Königabfaa442012-05-02 15:11:25 +02001517 .is_lockup = &evergreen_gpu_is_lockup,
Alex Deucherbe63fe82012-03-20 17:18:40 -04001518 }
1519 },
1520 .irq = {
1521 .set = &evergreen_irq_set,
1522 .process = &evergreen_irq_process,
1523 },
1524 .display = {
1525 .bandwidth_update = &dce6_bandwidth_update,
1526 .get_vblank_counter = &evergreen_get_vblank_counter,
1527 .wait_for_vblank = &dce4_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001528 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucherbe63fe82012-03-20 17:18:40 -04001529 },
1530 .copy = {
1531 .blit = &r600_copy_blit,
1532 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1533 .dma = NULL,
1534 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1535 .copy = &r600_copy_blit,
1536 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1537 },
1538 .surface = {
1539 .set_reg = r600_set_surface_reg,
1540 .clear_reg = r600_clear_surface_reg,
1541 },
1542 .hpd = {
1543 .init = &evergreen_hpd_init,
1544 .fini = &evergreen_hpd_fini,
1545 .sense = &evergreen_hpd_sense,
1546 .set_polarity = &evergreen_hpd_set_polarity,
1547 },
1548 .pm = {
1549 .misc = &evergreen_pm_misc,
1550 .prepare = &evergreen_pm_prepare,
1551 .finish = &evergreen_pm_finish,
1552 .init_profile = &sumo_pm_init_profile,
1553 .get_dynpm_state = &r600_pm_get_dynpm_state,
1554 .get_engine_clock = &radeon_atom_get_engine_clock,
1555 .set_engine_clock = &radeon_atom_set_engine_clock,
1556 .get_memory_clock = NULL,
1557 .set_memory_clock = NULL,
1558 .get_pcie_lanes = NULL,
1559 .set_pcie_lanes = NULL,
1560 .set_clock_gating = NULL,
1561 },
1562 .pflip = {
1563 .pre_page_flip = &evergreen_pre_page_flip,
1564 .page_flip = &evergreen_page_flip,
1565 .post_page_flip = &evergreen_post_page_flip,
1566 },
1567};
1568
Alex Deucher02779c02012-03-20 17:18:25 -04001569static struct radeon_asic si_asic = {
1570 .init = &si_init,
1571 .fini = &si_fini,
1572 .suspend = &si_suspend,
1573 .resume = &si_resume,
Alex Deucher02779c02012-03-20 17:18:25 -04001574 .asic_reset = &si_asic_reset,
1575 .vga_set_state = &r600_vga_set_state,
1576 .ioctl_wait_idle = r600_ioctl_wait_idle,
1577 .gui_idle = &r600_gui_idle,
1578 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1579 .gart = {
1580 .tlb_flush = &si_pcie_gart_tlb_flush,
1581 .set_page = &rs600_gart_set_page,
1582 },
Christian König05b07142012-08-06 20:21:10 +02001583 .vm = {
1584 .init = &si_vm_init,
1585 .fini = &si_vm_fini,
1586 .bind = &si_vm_bind,
1587 .unbind = &si_vm_unbind,
1588 .tlb_flush = &si_vm_tlb_flush,
1589 .page_flags = &cayman_vm_page_flags,
1590 .set_page = &cayman_vm_set_page,
1591 },
Alex Deucher02779c02012-03-20 17:18:25 -04001592 .ring = {
1593 [RADEON_RING_TYPE_GFX_INDEX] = {
1594 .ib_execute = &si_ring_ib_execute,
1595 .ib_parse = &si_ib_parse,
1596 .emit_fence = &si_fence_ring_emit,
1597 .emit_semaphore = &r600_semaphore_ring_emit,
1598 .cs_parse = NULL,
1599 .ring_test = &r600_ring_test,
1600 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001601 .is_lockup = &si_gpu_is_lockup,
Alex Deucher02779c02012-03-20 17:18:25 -04001602 },
1603 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1604 .ib_execute = &si_ring_ib_execute,
1605 .ib_parse = &si_ib_parse,
1606 .emit_fence = &si_fence_ring_emit,
1607 .emit_semaphore = &r600_semaphore_ring_emit,
1608 .cs_parse = NULL,
1609 .ring_test = &r600_ring_test,
1610 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001611 .is_lockup = &si_gpu_is_lockup,
Alex Deucher02779c02012-03-20 17:18:25 -04001612 },
1613 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1614 .ib_execute = &si_ring_ib_execute,
1615 .ib_parse = &si_ib_parse,
1616 .emit_fence = &si_fence_ring_emit,
1617 .emit_semaphore = &r600_semaphore_ring_emit,
1618 .cs_parse = NULL,
1619 .ring_test = &r600_ring_test,
1620 .ib_test = &r600_ib_test,
Christian König312c4a82012-05-02 15:11:09 +02001621 .is_lockup = &si_gpu_is_lockup,
Alex Deucher02779c02012-03-20 17:18:25 -04001622 }
1623 },
1624 .irq = {
1625 .set = &si_irq_set,
1626 .process = &si_irq_process,
1627 },
1628 .display = {
1629 .bandwidth_update = &dce6_bandwidth_update,
1630 .get_vblank_counter = &evergreen_get_vblank_counter,
1631 .wait_for_vblank = &dce4_wait_for_vblank,
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001632 .set_backlight_level = &atombios_set_backlight_level,
Alex Deucher02779c02012-03-20 17:18:25 -04001633 },
1634 .copy = {
1635 .blit = NULL,
1636 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1637 .dma = NULL,
1638 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1639 .copy = NULL,
1640 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1641 },
1642 .surface = {
1643 .set_reg = r600_set_surface_reg,
1644 .clear_reg = r600_clear_surface_reg,
1645 },
1646 .hpd = {
1647 .init = &evergreen_hpd_init,
1648 .fini = &evergreen_hpd_fini,
1649 .sense = &evergreen_hpd_sense,
1650 .set_polarity = &evergreen_hpd_set_polarity,
1651 },
1652 .pm = {
1653 .misc = &evergreen_pm_misc,
1654 .prepare = &evergreen_pm_prepare,
1655 .finish = &evergreen_pm_finish,
1656 .init_profile = &sumo_pm_init_profile,
1657 .get_dynpm_state = &r600_pm_get_dynpm_state,
1658 .get_engine_clock = &radeon_atom_get_engine_clock,
1659 .set_engine_clock = &radeon_atom_set_engine_clock,
1660 .get_memory_clock = &radeon_atom_get_memory_clock,
1661 .set_memory_clock = &radeon_atom_set_memory_clock,
1662 .get_pcie_lanes = NULL,
1663 .set_pcie_lanes = NULL,
1664 .set_clock_gating = NULL,
1665 },
1666 .pflip = {
1667 .pre_page_flip = &evergreen_pre_page_flip,
1668 .page_flip = &evergreen_page_flip,
1669 .post_page_flip = &evergreen_post_page_flip,
1670 },
1671};
1672
Alex Deucherabf1dc62012-07-17 14:02:36 -04001673/**
1674 * radeon_asic_init - register asic specific callbacks
1675 *
1676 * @rdev: radeon device pointer
1677 *
1678 * Registers the appropriate asic specific callbacks for each
1679 * chip family. Also sets other asics specific info like the number
1680 * of crtcs and the register aperture accessors (all asics).
1681 * Returns 0 for success.
1682 */
Daniel Vetter0a10c852010-03-11 21:19:14 +00001683int radeon_asic_init(struct radeon_device *rdev)
1684{
1685 radeon_register_accessor_init(rdev);
Alex Deucherba7e05e2011-06-16 18:14:22 +00001686
1687 /* set the number of crtcs */
1688 if (rdev->flags & RADEON_SINGLE_CRTC)
1689 rdev->num_crtc = 1;
1690 else
1691 rdev->num_crtc = 2;
1692
Daniel Vetter0a10c852010-03-11 21:19:14 +00001693 switch (rdev->family) {
1694 case CHIP_R100:
1695 case CHIP_RV100:
1696 case CHIP_RS100:
1697 case CHIP_RV200:
1698 case CHIP_RS200:
1699 rdev->asic = &r100_asic;
1700 break;
1701 case CHIP_R200:
1702 case CHIP_RV250:
1703 case CHIP_RS300:
1704 case CHIP_RV280:
1705 rdev->asic = &r200_asic;
1706 break;
1707 case CHIP_R300:
1708 case CHIP_R350:
1709 case CHIP_RV350:
1710 case CHIP_RV380:
1711 if (rdev->flags & RADEON_IS_PCIE)
1712 rdev->asic = &r300_asic_pcie;
1713 else
1714 rdev->asic = &r300_asic;
1715 break;
1716 case CHIP_R420:
1717 case CHIP_R423:
1718 case CHIP_RV410:
1719 rdev->asic = &r420_asic;
Alex Deucher07bb0842010-06-22 21:58:26 -04001720 /* handle macs */
1721 if (rdev->bios == NULL) {
Alex Deucher798bcf72012-02-23 17:53:48 -05001722 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
1723 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
1724 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
1725 rdev->asic->pm.set_memory_clock = NULL;
Alex Deucher37e9b6a2012-08-03 11:39:43 -04001726 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
Alex Deucher07bb0842010-06-22 21:58:26 -04001727 }
Daniel Vetter0a10c852010-03-11 21:19:14 +00001728 break;
1729 case CHIP_RS400:
1730 case CHIP_RS480:
1731 rdev->asic = &rs400_asic;
1732 break;
1733 case CHIP_RS600:
1734 rdev->asic = &rs600_asic;
1735 break;
1736 case CHIP_RS690:
1737 case CHIP_RS740:
1738 rdev->asic = &rs690_asic;
1739 break;
1740 case CHIP_RV515:
1741 rdev->asic = &rv515_asic;
1742 break;
1743 case CHIP_R520:
1744 case CHIP_RV530:
1745 case CHIP_RV560:
1746 case CHIP_RV570:
1747 case CHIP_R580:
1748 rdev->asic = &r520_asic;
1749 break;
1750 case CHIP_R600:
1751 case CHIP_RV610:
1752 case CHIP_RV630:
1753 case CHIP_RV620:
1754 case CHIP_RV635:
1755 case CHIP_RV670:
Alex Deucherf47299c2010-03-16 20:54:38 -04001756 rdev->asic = &r600_asic;
1757 break;
Daniel Vetter0a10c852010-03-11 21:19:14 +00001758 case CHIP_RS780:
1759 case CHIP_RS880:
Alex Deucherf47299c2010-03-16 20:54:38 -04001760 rdev->asic = &rs780_asic;
Daniel Vetter0a10c852010-03-11 21:19:14 +00001761 break;
1762 case CHIP_RV770:
1763 case CHIP_RV730:
1764 case CHIP_RV710:
1765 case CHIP_RV740:
1766 rdev->asic = &rv770_asic;
1767 break;
1768 case CHIP_CEDAR:
1769 case CHIP_REDWOOD:
1770 case CHIP_JUNIPER:
1771 case CHIP_CYPRESS:
1772 case CHIP_HEMLOCK:
Alex Deucherba7e05e2011-06-16 18:14:22 +00001773 /* set num crtcs */
1774 if (rdev->family == CHIP_CEDAR)
1775 rdev->num_crtc = 4;
1776 else
1777 rdev->num_crtc = 6;
Daniel Vetter0a10c852010-03-11 21:19:14 +00001778 rdev->asic = &evergreen_asic;
1779 break;
Alex Deucher958261d2010-11-22 17:56:30 -05001780 case CHIP_PALM:
Alex Deucher89da5a32011-05-31 15:42:47 -04001781 case CHIP_SUMO:
1782 case CHIP_SUMO2:
Alex Deucher958261d2010-11-22 17:56:30 -05001783 rdev->asic = &sumo_asic;
1784 break;
Alex Deuchera43b7662011-01-06 21:19:33 -05001785 case CHIP_BARTS:
1786 case CHIP_TURKS:
1787 case CHIP_CAICOS:
Alex Deucherba7e05e2011-06-16 18:14:22 +00001788 /* set num crtcs */
1789 if (rdev->family == CHIP_CAICOS)
1790 rdev->num_crtc = 4;
1791 else
1792 rdev->num_crtc = 6;
Alex Deuchera43b7662011-01-06 21:19:33 -05001793 rdev->asic = &btc_asic;
1794 break;
Alex Deuchere3487622011-03-02 20:07:36 -05001795 case CHIP_CAYMAN:
1796 rdev->asic = &cayman_asic;
Alex Deucherba7e05e2011-06-16 18:14:22 +00001797 /* set num crtcs */
1798 rdev->num_crtc = 6;
Alex Deuchere3487622011-03-02 20:07:36 -05001799 break;
Alex Deucherbe63fe82012-03-20 17:18:40 -04001800 case CHIP_ARUBA:
1801 rdev->asic = &trinity_asic;
1802 /* set num crtcs */
1803 rdev->num_crtc = 4;
Alex Deucherbe63fe82012-03-20 17:18:40 -04001804 break;
Alex Deucher02779c02012-03-20 17:18:25 -04001805 case CHIP_TAHITI:
1806 case CHIP_PITCAIRN:
1807 case CHIP_VERDE:
1808 rdev->asic = &si_asic;
1809 /* set num crtcs */
1810 rdev->num_crtc = 6;
Alex Deucher02779c02012-03-20 17:18:25 -04001811 break;
Daniel Vetter0a10c852010-03-11 21:19:14 +00001812 default:
1813 /* FIXME: not supported yet */
1814 return -EINVAL;
1815 }
1816
1817 if (rdev->flags & RADEON_IS_IGP) {
Alex Deucher798bcf72012-02-23 17:53:48 -05001818 rdev->asic->pm.get_memory_clock = NULL;
1819 rdev->asic->pm.set_memory_clock = NULL;
Daniel Vetter0a10c852010-03-11 21:19:14 +00001820 }
1821
Daniel Vetter0a10c852010-03-11 21:19:14 +00001822 return 0;
1823}
1824