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Santosh Shilimkar367cd312009-04-28 20:51:52 +05301/*
2 * OMAP4 SMP source file. It contains platform specific fucntions
3 * needed for the linux smp kernel.
4 *
5 * Copyright (C) 2009 Texas Instruments, Inc.
6 *
7 * Author:
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * Platform file needed for the OMAP4 SMP. This file is based on arm
11 * realview smp platform.
12 * * Copyright (c) 2002 ARM Limited.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18#include <linux/init.h>
19#include <linux/device.h>
Santosh Shilimkar367cd312009-04-28 20:51:52 +053020#include <linux/smp.h>
21#include <linux/io.h>
22
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080023#include <asm/cacheflush.h>
Santosh Shilimkar367cd312009-04-28 20:51:52 +053024#include <asm/smp_scu.h>
25#include <mach/hardware.h>
Santosh Shilimkarfbc9be12010-05-14 12:05:26 -070026#include <mach/omap4-common.h>
Santosh Shilimkar367cd312009-04-28 20:51:52 +053027
Santosh Shilimkar367cd312009-04-28 20:51:52 +053028/* SCU base address */
Tony Lindgrene4e7a132009-10-19 15:25:26 -070029static void __iomem *scu_base;
Santosh Shilimkar367cd312009-04-28 20:51:52 +053030
Santosh Shilimkar367cd312009-04-28 20:51:52 +053031static DEFINE_SPINLOCK(boot_lock);
32
33void __cpuinit platform_secondary_init(unsigned int cpu)
34{
35 trace_hardirqs_off();
36
37 /*
38 * If any interrupts are already enabled for the primary
39 * core (e.g. timer irq), then they will not have been enabled
40 * for us: do so
41 */
Tony Lindgrene4e7a132009-10-19 15:25:26 -070042 gic_cpu_init(0, gic_cpu_base_addr);
Santosh Shilimkar367cd312009-04-28 20:51:52 +053043
44 /*
45 * Synchronise with the boot thread.
46 */
47 spin_lock(&boot_lock);
48 spin_unlock(&boot_lock);
49}
50
51int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
52{
Santosh Shilimkar367cd312009-04-28 20:51:52 +053053 /*
54 * Set synchronisation state between this boot processor
55 * and the secondary one
56 */
57 spin_lock(&boot_lock);
58
59 /*
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080060 * Update the AuxCoreBoot0 with boot state for secondary core.
Santosh Shilimkar367cd312009-04-28 20:51:52 +053061 * omap_secondary_startup() routine will hold the secondary core till
62 * the AuxCoreBoot1 register is updated with cpu state
63 * A barrier is added to ensure that write buffer is drained
64 */
Santosh Shilimkar7d35b8d2010-08-02 13:18:19 +030065 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080066 flush_cache_all();
Santosh Shilimkar367cd312009-04-28 20:51:52 +053067 smp_wmb();
Russell Kingad3b69932010-11-15 09:42:08 +000068 smp_cross_call(cpumask_of(cpu), 1);
Santosh Shilimkar367cd312009-04-28 20:51:52 +053069
Santosh Shilimkar367cd312009-04-28 20:51:52 +053070 /*
71 * Now the secondary core is starting up let it run its
72 * calibrations, then wait for it to finish
73 */
74 spin_unlock(&boot_lock);
75
76 return 0;
77}
78
79static void __init wakeup_secondary(void)
80{
81 /*
82 * Write the address of secondary startup routine into the
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080083 * AuxCoreBoot1 where ROM code will jump and start executing
Santosh Shilimkar367cd312009-04-28 20:51:52 +053084 * on secondary core once out of WFE
85 * A barrier is added to ensure that write buffer is drained
86 */
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080087 omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
Santosh Shilimkar367cd312009-04-28 20:51:52 +053088 smp_wmb();
89
90 /*
91 * Send a 'sev' to wake the secondary core from WFE.
Santosh Shilimkar942e2c92009-12-11 16:16:35 -080092 * Drain the outstanding writes to memory
Santosh Shilimkar367cd312009-04-28 20:51:52 +053093 */
Tony Lindgrena4192d32010-08-16 09:21:20 +030094 dsb_sev();
Santosh Shilimkar367cd312009-04-28 20:51:52 +053095 mb();
96}
97
98/*
99 * Initialise the CPU possible map early - this describes the CPUs
100 * which may be present or become present in the system.
101 */
102void __init smp_init_cpus(void)
103{
Tony Lindgrene4e7a132009-10-19 15:25:26 -0700104 unsigned int i, ncores;
105
106 /* Never released */
107 scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
108 BUG_ON(!scu_base);
109
Russell Kingfd778f02010-12-02 18:09:37 +0000110 ncores = scu_get_core_count(scu_base);
Santosh Shilimkar367cd312009-04-28 20:51:52 +0530111
Santosh Shilimkar367cd312009-04-28 20:51:52 +0530112 /* sanity check */
Santosh Shilimkar367cd312009-04-28 20:51:52 +0530113 if (ncores > NR_CPUS) {
114 printk(KERN_WARNING
115 "OMAP4: no. of cores (%d) greater than configured "
116 "maximum of %d - clipping\n",
117 ncores, NR_CPUS);
118 ncores = NR_CPUS;
119 }
Russell Kingbbc3d142010-12-03 10:42:58 +0000120
121 for (i = 0; i < ncores; i++)
122 set_cpu_possible(i, true);
123}
124
Russell King05c74a62010-12-03 11:09:48 +0000125void __init platform_smp_prepare_cpus(unsigned int max_cpus)
Russell Kingbbc3d142010-12-03 10:42:58 +0000126{
Russell Kingbbc3d142010-12-03 10:42:58 +0000127 int i;
128
Santosh Shilimkar367cd312009-04-28 20:51:52 +0530129 /*
130 * Initialise the present map, which describes the set of CPUs
131 * actually populated at the present time.
132 */
133 for (i = 0; i < max_cpus; i++)
134 set_cpu_present(i, true);
135
Russell King05c74a62010-12-03 11:09:48 +0000136 /*
137 * Initialise the SCU and wake up the secondary core using
138 * wakeup_secondary().
139 */
140 scu_enable(scu_base);
141 wakeup_secondary();
Santosh Shilimkar367cd312009-04-28 20:51:52 +0530142}