Valentin Longchamp | 4e5bc99 | 2012-11-17 17:00:55 +0100 | [diff] [blame] | 1 | / { |
Andrew Lunn | 5d7fd65 | 2016-04-03 04:03:49 +0200 | [diff] [blame] | 2 | mbus@f1000000 { |
Andrew Lunn | eb13cf8 | 2016-04-03 04:03:47 +0200 | [diff] [blame] | 3 | pciec: pcie-controller@82000000 { |
Valentin Longchamp | d584a10 | 2014-05-16 10:49:01 +0200 | [diff] [blame] | 4 | compatible = "marvell,kirkwood-pcie"; |
| 5 | status = "disabled"; |
| 6 | device_type = "pci"; |
| 7 | |
| 8 | #address-cells = <3>; |
| 9 | #size-cells = <2>; |
| 10 | |
| 11 | bus-range = <0x00 0xff>; |
| 12 | |
| 13 | ranges = |
| 14 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 |
| 15 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ |
| 16 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; |
| 17 | |
| 18 | pcie0: pcie@1,0 { |
| 19 | device_type = "pci"; |
| 20 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; |
| 21 | reg = <0x0800 0 0 0 0>; |
| 22 | #address-cells = <3>; |
| 23 | #size-cells = <2>; |
| 24 | #interrupt-cells = <1>; |
| 25 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
| 26 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; |
| 27 | interrupt-map-mask = <0 0 0 0>; |
| 28 | interrupt-map = <0 0 0 0 &intc 9>; |
| 29 | marvell,pcie-port = <0>; |
| 30 | marvell,pcie-lane = <0>; |
| 31 | clocks = <&gate_clk 2>; |
| 32 | status = "disabled"; |
| 33 | }; |
| 34 | }; |
| 35 | }; |
| 36 | |
Valentin Longchamp | 4e5bc99 | 2012-11-17 17:00:55 +0100 | [diff] [blame] | 37 | ocp@f1000000 { |
Sebastian Hesselbarth | a948396 | 2014-04-30 14:56:32 +0200 | [diff] [blame] | 38 | pinctrl: pin-controller@10000 { |
Valentin Longchamp | 4e5bc99 | 2012-11-17 17:00:55 +0100 | [diff] [blame] | 39 | compatible = "marvell,98dx4122-pinctrl"; |
Valentin Longchamp | 4e5bc99 | 2012-11-17 17:00:55 +0100 | [diff] [blame] | 40 | |
Valentin Longchamp | 4e5bc99 | 2012-11-17 17:00:55 +0100 | [diff] [blame] | 41 | }; |
| 42 | }; |
| 43 | }; |
Valentin Longchamp | d584a10 | 2014-05-16 10:49:01 +0200 | [diff] [blame] | 44 | |
| 45 | &sata_phy0 { |
| 46 | status = "disabled"; |
| 47 | }; |
| 48 | |
| 49 | &sata_phy1 { |
| 50 | status = "disabled"; |
| 51 | }; |