| Sergei Shtylyov | e9189e6 | 2016-11-05 01:04:32 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for the SK-RZG1E board |
| 3 | * |
| 4 | * Copyright (C) 2016 Cogent Embedded, Inc. |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | /dts-v1/; |
| 12 | #include "r8a7745.dtsi" |
| 13 | |
| 14 | / { |
| 15 | model = "SK-RZG1E"; |
| 16 | compatible = "renesas,sk-rzg1e", "renesas,r8a7745"; |
| 17 | |
| 18 | aliases { |
| 19 | serial0 = &scif2; |
| 20 | }; |
| 21 | |
| 22 | chosen { |
| Sergei Shtylyov | 6b33436 | 2016-11-05 01:05:28 +0300 | [diff] [blame] | 23 | bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; |
| Sergei Shtylyov | e9189e6 | 2016-11-05 01:04:32 +0300 | [diff] [blame] | 24 | stdout-path = "serial0:115200n8"; |
| 25 | }; |
| 26 | |
| 27 | memory@40000000 { |
| 28 | device_type = "memory"; |
| 29 | reg = <0 0x40000000 0 0x40000000>; |
| 30 | }; |
| 31 | }; |
| 32 | |
| 33 | &extal_clk { |
| 34 | clock-frequency = <20000000>; |
| 35 | }; |
| 36 | |
| 37 | &scif2 { |
| 38 | status = "okay"; |
| 39 | }; |
| Sergei Shtylyov | 6b33436 | 2016-11-05 01:05:28 +0300 | [diff] [blame] | 40 | |
| 41 | ðer { |
| 42 | phy-handle = <&phy1>; |
| 43 | renesas,ether-link-active-low; |
| 44 | status = "okay"; |
| 45 | |
| 46 | phy1: ethernet-phy@1 { |
| 47 | reg = <1>; |
| 48 | interrupt-parent = <&irqc>; |
| 49 | interrupts = <8 IRQ_TYPE_LEVEL_LOW>; |
| 50 | micrel,led-mode = <1>; |
| 51 | }; |
| 52 | }; |