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gerrit-public.fairphone.software / kernel / msm-4.19 / 07ce870bed2f631ad53a2c1a90db20b5f8126ab9 / . / drivers / net / ethernet / intel / ixgbe / ixgbe_phy.h
blob: bbfe55c1054afd42252c169a4f100a58b13057f4 [file] [log] [blame]
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
Don Skidmore94971822012-01-06 03:24:16 +0000[diff] [blame]4 Copyright(c) 1999 - 2012 Intel Corporation.
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_PHY_H_
29#define _IXGBE_PHY_H_
30
31#include "ixgbe_type.h"
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]32#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
Emil Tantilov07ce8702012-12-19 07:14:17 +0000[diff] [blame^]33#define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]34
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]35/* EEPROM byte offsets */
36#define IXGBE_SFF_IDENTIFIER 0x0
37#define IXGBE_SFF_IDENTIFIER_SFP 0x3
38#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
39#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
40#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
41#define IXGBE_SFF_1GBE_COMP_CODES 0x6
42#define IXGBE_SFF_10GBE_COMP_CODES 0x3
Peter P Waskiewicz Jr537d58a2009-05-19 09:18:51 +0000[diff] [blame]43#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
Don Skidmoreea0a04d2010-05-18 16:00:13 +0000[diff] [blame]44#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
Emil Tantilov07ce8702012-12-19 07:14:17 +0000[diff] [blame^]45#define IXGBE_SFF_SFF_8472_SWAP 0x5C
46#define IXGBE_SFF_SFF_8472_COMP 0x5E
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]47
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]48/* Bitmasks */
Peter P Waskiewicz Jr537d58a2009-05-19 09:18:51 +0000[diff] [blame]49#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
Don Skidmoreea0a04d2010-05-18 16:00:13 +0000[diff] [blame]50#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
51#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]52#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
PJ Waskiewicz553b4492009-04-09 22:28:15 +0000[diff] [blame]53#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
Don Skidmorecb836a92010-06-29 18:30:59 +0000[diff] [blame]54#define IXGBE_SFF_1GBASET_CAPABLE 0x8
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]55#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
56#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
Emil Tantilov07ce8702012-12-19 07:14:17 +0000[diff] [blame^]57#define IXGBE_SFF_ADDRESSING_MODE 0x4
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]58#define IXGBE_I2C_EEPROM_READ_MASK 0x100
59#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
60#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
61#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
62#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
63#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
64
Emil Tantilov0b0c2b32011-02-26 06:40:16 +0000[diff] [blame]65/* Flow control defines */
66#define IXGBE_TAF_SYM_PAUSE 0x400
67#define IXGBE_TAF_ASM_PAUSE 0x800
68
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]69/* Bit-shift macros */
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]70#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
71#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
72#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]73
74/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
75#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
76#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
77#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]78#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]79
Donald Skidmorec4900be2008-11-20 21:11:42 -0800[diff] [blame]80/* I2C SDA and SCL timing parameters for standard mode */
81#define IXGBE_I2C_T_HD_STA 4
82#define IXGBE_I2C_T_LOW 5
83#define IXGBE_I2C_T_HIGH 4
84#define IXGBE_I2C_T_SU_STA 5
85#define IXGBE_I2C_T_HD_DATA 5
86#define IXGBE_I2C_T_SU_DATA 1
87#define IXGBE_I2C_T_RISE 1
88#define IXGBE_I2C_T_FALL 1
89#define IXGBE_I2C_T_SU_STO 4
90#define IXGBE_I2C_T_BUF 5
91
Mallikarjuna R Chilakala119fc602010-05-20 23:07:06 -0700[diff] [blame]92#define IXGBE_TN_LASI_STATUS_REG 0x9005
93#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]94
Emil Tantilov07ce8702012-12-19 07:14:17 +0000[diff] [blame^]95/* SFP+ SFF-8472 Compliance code */
96#define IXGBE_SFF_SFF_8472_UNSUP 0x00
97
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]98s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
99s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
100s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
101s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
102 u32 device_type, u16 *phy_data);
103s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
104 u32 device_type, u16 phy_data);
105s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
106s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
107 ixgbe_link_speed speed,
Jesse Brandeburgc44ade92008-09-11 19:59:59 -0700[diff] [blame]108 bool autoneg_wait_to_complete);
Don Skidmorea391f1d2010-11-16 19:27:15 -0800[diff] [blame]109s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
110 ixgbe_link_speed *speed,
111 bool *autoneg);
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]112
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700[diff] [blame]113/* PHY specific */
114s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
115 ixgbe_link_speed *speed,
116 bool *link_up);
Emil Tantilov9dda1732011-03-05 01:28:07 +0000[diff] [blame]117s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700[diff] [blame]118s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
119 u16 *firmware_version);
Don Skidmorefe15e8e12010-11-16 19:27:16 -0800[diff] [blame]120s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
121 u16 *firmware_version);
Jesse Brandeburg0befdb32008-10-31 00:46:40 -0700[diff] [blame]122
Donald Skidmorec4900be2008-11-20 21:11:42 -0800[diff] [blame]123s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
124s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
125s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
126 u16 *list_offset,
127 u16 *data_offset);
Mallikarjuna R Chilakala119fc602010-05-20 23:07:06 -0700[diff] [blame]128s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]129s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
130 u8 dev_addr, u8 *data);
131s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
132 u8 dev_addr, u8 data);
133s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
134 u8 *eeprom_data);
Emil Tantilov07ce8702012-12-19 07:14:17 +0000[diff] [blame^]135s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
136 u8 *sff8472_data);
PJ Waskiewicz11afc1b2009-02-27 15:44:30 +0000[diff] [blame]137s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
138 u8 eeprom_data);
Auke Kok9a799d72007-09-15 14:07:45 -0700[diff] [blame]139#endif /* _IXGBE_PHY_H_ */