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gerrit-public.fairphone.software / kernel / msm-4.19 / 0810569076c1f3cf4a82da40211dd0b07b3ad07e / . / drivers / net / wireless / ath / ath5k / rfbuffer.h
blob: 16b67e84906d10cf59e89160acbad401f8a986ca [file] [log] [blame]
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]1/*
2 * RF Buffer handling functions
3 *
4 * Copyright (c) 2009 Nick Kossifidis <mickflemm@gmail.com>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]20
21/*
22 * There are some special registers on the RF chip
23 * that control various operation settings related mostly to
24 * the analog parts (channel, gain adjustment etc).
25 *
26 * We don't write on those registers directly but
27 * we send a data packet on the chip, using a special register,
Bob Copelanda180a132010-08-15 13:03:12 -0400[diff] [blame]28 * that holds all the settings we need. After we've sent the
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]29 * data packet, we write on another special register to notify hw
30 * to apply the settings. This is done so that control registers
Bob Copelanda180a132010-08-15 13:03:12 -0400[diff] [blame]31 * can be dynamically programmed during operation and the settings
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]32 * are applied faster on the hw.
33 *
34 * We call each data packet an "RF Bank" and all the data we write
35 * (all RF Banks) "RF Buffer". This file holds initial RF Buffer
36 * data for the different RF chips, and various info to match RF
37 * Buffer offsets with specific RF registers so that we can access
38 * them. We tweak these settings on rfregs_init function.
39 *
40 * Also check out reg.h and U.S. Patent 6677779 B1 (about buffer
41 * registers and control registers):
42 *
43 * http://www.google.com/patents?id=qNURAAAAEBAJ
44 */
45
46
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]47/*
48 * Struct to hold default mode specific RF
49 * register values (RF Banks)
50 */
51struct ath5k_ini_rfbuffer {
52 u8 rfb_bank; /* RF Bank number */
53 u16 rfb_ctrl_register; /* RF Buffer control register */
Nick Kossifidis8c2b4182010-11-23 21:51:38 +0200[diff] [blame]54 u32 rfb_mode_data[3]; /* RF Buffer data for each mode */
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]55};
56
57/*
58 * Struct to hold RF Buffer field
59 * infos used to access certain RF
60 * analog registers
61 */
62struct ath5k_rfb_field {
63 u8 len; /* Field length */
64 u16 pos; /* Offset on the raw packet */
65 u8 col; /* Column -used for shifting */
66};
67
68/*
69 * RF analog register definition
70 */
71struct ath5k_rf_reg {
72 u8 bank; /* RF Buffer Bank number */
73 u8 index; /* Register's index on rf_regs_idx */
74 struct ath5k_rfb_field field; /* RF Buffer field for this register */
75};
76
77/* Map RF registers to indexes
78 * We do this to handle common bits and make our
79 * life easier by using an index for each register
80 * instead of a full rfb_field */
81enum ath5k_rf_regs_idx {
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]82 /* BANK 2 */
83 AR5K_RF_TURBO = 0,
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]84 /* BANK 6 */
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]85 AR5K_RF_OB_2GHZ,
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]86 AR5K_RF_OB_5GHZ,
87 AR5K_RF_DB_2GHZ,
88 AR5K_RF_DB_5GHZ,
89 AR5K_RF_FIXED_BIAS_A,
90 AR5K_RF_FIXED_BIAS_B,
91 AR5K_RF_PWD_XPD,
92 AR5K_RF_XPD_SEL,
93 AR5K_RF_XPD_GAIN,
94 AR5K_RF_PD_GAIN_LO,
95 AR5K_RF_PD_GAIN_HI,
96 AR5K_RF_HIGH_VC_CP,
97 AR5K_RF_MID_VC_CP,
98 AR5K_RF_LOW_VC_CP,
99 AR5K_RF_PUSH_UP,
100 AR5K_RF_PAD2GND,
101 AR5K_RF_XB2_LVL,
102 AR5K_RF_XB5_LVL,
103 AR5K_RF_PWD_ICLOBUF_2G,
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]104 AR5K_RF_PWD_84,
105 AR5K_RF_PWD_90,
106 AR5K_RF_PWD_130,
107 AR5K_RF_PWD_131,
108 AR5K_RF_PWD_132,
109 AR5K_RF_PWD_136,
110 AR5K_RF_PWD_137,
111 AR5K_RF_PWD_138,
112 AR5K_RF_PWD_166,
113 AR5K_RF_PWD_167,
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]114 AR5K_RF_DERBY_CHAN_SEL_MODE,
115 /* BANK 7 */
116 AR5K_RF_GAIN_I,
117 AR5K_RF_PLO_SEL,
118 AR5K_RF_RFGAIN_SEL,
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]119 AR5K_RF_RFGAIN_STEP,
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]120 AR5K_RF_WAIT_S,
121 AR5K_RF_WAIT_I,
122 AR5K_RF_MAX_TIME,
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]123 AR5K_RF_MIXVGA_OVR,
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]124 AR5K_RF_MIXGAIN_OVR,
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]125 AR5K_RF_MIXGAIN_STEP,
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]126 AR5K_RF_PD_DELAY_A,
127 AR5K_RF_PD_DELAY_B,
128 AR5K_RF_PD_DELAY_XR,
129 AR5K_RF_PD_PERIOD_A,
130 AR5K_RF_PD_PERIOD_B,
131 AR5K_RF_PD_PERIOD_XR,
132};
133
134
135/*******************\
136* RF5111 (Sombrero) *
137\*******************/
138
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]139/* BANK 2 len pos col */
140#define AR5K_RF5111_RF_TURBO { 1, 3, 0 }
141
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]142/* BANK 6 len pos col */
143#define AR5K_RF5111_OB_2GHZ { 3, 119, 0 }
144#define AR5K_RF5111_DB_2GHZ { 3, 122, 0 }
145
146#define AR5K_RF5111_OB_5GHZ { 3, 104, 0 }
147#define AR5K_RF5111_DB_5GHZ { 3, 107, 0 }
148
149#define AR5K_RF5111_PWD_XPD { 1, 95, 0 }
150#define AR5K_RF5111_XPD_GAIN { 4, 96, 0 }
151
152/* Access to PWD registers */
153#define AR5K_RF5111_PWD(_n) { 1, (135 - _n), 3 }
154
155/* BANK 7 len pos col */
156#define AR5K_RF5111_GAIN_I { 6, 29, 0 }
157#define AR5K_RF5111_PLO_SEL { 1, 4, 0 }
158#define AR5K_RF5111_RFGAIN_SEL { 1, 36, 0 }
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200[diff] [blame]159#define AR5K_RF5111_RFGAIN_STEP { 6, 37, 0 }
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]160/* Only on AR5212 BaseBand and up */
161#define AR5K_RF5111_WAIT_S { 5, 19, 0 }
162#define AR5K_RF5111_WAIT_I { 5, 24, 0 }
163#define AR5K_RF5111_MAX_TIME { 2, 49, 0 }
164
165static const struct ath5k_rf_reg rf_regs_5111[] = {
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]166 {2, AR5K_RF_TURBO, AR5K_RF5111_RF_TURBO},
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]167 {6, AR5K_RF_OB_2GHZ, AR5K_RF5111_OB_2GHZ},
168 {6, AR5K_RF_DB_2GHZ, AR5K_RF5111_DB_2GHZ},
169 {6, AR5K_RF_OB_5GHZ, AR5K_RF5111_OB_5GHZ},
170 {6, AR5K_RF_DB_5GHZ, AR5K_RF5111_DB_5GHZ},
171 {6, AR5K_RF_PWD_XPD, AR5K_RF5111_PWD_XPD},
172 {6, AR5K_RF_XPD_GAIN, AR5K_RF5111_XPD_GAIN},
173 {6, AR5K_RF_PWD_84, AR5K_RF5111_PWD(84)},
174 {6, AR5K_RF_PWD_90, AR5K_RF5111_PWD(90)},
175 {7, AR5K_RF_GAIN_I, AR5K_RF5111_GAIN_I},
176 {7, AR5K_RF_PLO_SEL, AR5K_RF5111_PLO_SEL},
177 {7, AR5K_RF_RFGAIN_SEL, AR5K_RF5111_RFGAIN_SEL},
178 {7, AR5K_RF_RFGAIN_STEP, AR5K_RF5111_RFGAIN_STEP},
179 {7, AR5K_RF_WAIT_S, AR5K_RF5111_WAIT_S},
180 {7, AR5K_RF_WAIT_I, AR5K_RF5111_WAIT_I},
181 {7, AR5K_RF_MAX_TIME, AR5K_RF5111_MAX_TIME}
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]182};
183
184/* Default mode specific settings */
185static const struct ath5k_ini_rfbuffer rfb_5111[] = {
Nick Kossifidis8c2b4182010-11-23 21:51:38 +0200[diff] [blame]186 /* BANK / C.R. A/XR B G */
187 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
188 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
189 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
190 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
191 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
192 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
193 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
194 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
195 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
196 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
197 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
198 { 0, 0x989c, { 0x00380000, 0x00380000, 0x00380000 } },
199 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
200 { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
201 { 0, 0x989c, { 0x00000000, 0x000000c0, 0x00000080 } },
202 { 0, 0x989c, { 0x000400f9, 0x000400ff, 0x000400fd } },
203 { 0, 0x98d4, { 0x00000000, 0x00000004, 0x00000004 } },
204 { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
205 { 2, 0x98d4, { 0x00000010, 0x00000010, 0x00000010 } },
206 { 3, 0x98d8, { 0x00601068, 0x00601068, 0x00601068 } },
207 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
208 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
209 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
210 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
211 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
212 { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
213 { 6, 0x989c, { 0x04000000, 0x04000000, 0x04000000 } },
214 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
215 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
216 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
217 { 6, 0x989c, { 0x00000000, 0x0a000000, 0x00000000 } },
218 { 6, 0x989c, { 0x003800c0, 0x023800c0, 0x003800c0 } },
219 { 6, 0x989c, { 0x00020006, 0x00000006, 0x00020006 } },
220 { 6, 0x989c, { 0x00000089, 0x00000089, 0x00000089 } },
221 { 6, 0x989c, { 0x000000a0, 0x000000a0, 0x000000a0 } },
222 { 6, 0x989c, { 0x00040007, 0x00040007, 0x00040007 } },
223 { 6, 0x98d4, { 0x0000001a, 0x0000001a, 0x0000001a } },
224 { 7, 0x989c, { 0x00000040, 0x00000040, 0x00000040 } },
225 { 7, 0x989c, { 0x00000010, 0x00000010, 0x00000010 } },
226 { 7, 0x989c, { 0x00000008, 0x00000008, 0x00000008 } },
227 { 7, 0x989c, { 0x0000004f, 0x0000004f, 0x0000004f } },
228 { 7, 0x989c, { 0x000000f1, 0x00000061, 0x000000f1 } },
229 { 7, 0x989c, { 0x0000904f, 0x0000904c, 0x0000904f } },
230 { 7, 0x989c, { 0x0000125a, 0x0000129a, 0x0000125a } },
231 { 7, 0x98cc, { 0x0000000e, 0x0000000f, 0x0000000e } },
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]232};
233
234
235
236/***********************\
237* RF5112/RF2112 (Derby) *
238\***********************/
239
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]240/* BANK 2 (Common) len pos col */
241#define AR5K_RF5112X_RF_TURBO { 1, 1, 2 }
242
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]243/* BANK 7 (Common) len pos col */
244#define AR5K_RF5112X_GAIN_I { 6, 14, 0 }
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200[diff] [blame]245#define AR5K_RF5112X_MIXVGA_OVR { 1, 36, 0 }
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]246#define AR5K_RF5112X_MIXGAIN_OVR { 2, 37, 0 }
Nick Kossifidis6f3b4142009-02-09 06:03:41 +0200[diff] [blame]247#define AR5K_RF5112X_MIXGAIN_STEP { 4, 32, 0 }
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]248#define AR5K_RF5112X_PD_DELAY_A { 4, 58, 0 }
249#define AR5K_RF5112X_PD_DELAY_B { 4, 62, 0 }
250#define AR5K_RF5112X_PD_DELAY_XR { 4, 66, 0 }
251#define AR5K_RF5112X_PD_PERIOD_A { 4, 70, 0 }
252#define AR5K_RF5112X_PD_PERIOD_B { 4, 74, 0 }
253#define AR5K_RF5112X_PD_PERIOD_XR { 4, 78, 0 }
254
255/* RFX112 (Derby 1) */
256
257/* BANK 6 len pos col */
258#define AR5K_RF5112_OB_2GHZ { 3, 269, 0 }
259#define AR5K_RF5112_DB_2GHZ { 3, 272, 0 }
260
261#define AR5K_RF5112_OB_5GHZ { 3, 261, 0 }
262#define AR5K_RF5112_DB_5GHZ { 3, 264, 0 }
263
264#define AR5K_RF5112_FIXED_BIAS_A { 1, 260, 0 }
265#define AR5K_RF5112_FIXED_BIAS_B { 1, 259, 0 }
266
267#define AR5K_RF5112_XPD_SEL { 1, 284, 0 }
268#define AR5K_RF5112_XPD_GAIN { 2, 252, 0 }
269
270/* Access to PWD registers */
271#define AR5K_RF5112_PWD(_n) { 1, (302 - _n), 3 }
272
273static const struct ath5k_rf_reg rf_regs_5112[] = {
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]274 {2, AR5K_RF_TURBO, AR5K_RF5112X_RF_TURBO},
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]275 {6, AR5K_RF_OB_2GHZ, AR5K_RF5112_OB_2GHZ},
276 {6, AR5K_RF_DB_2GHZ, AR5K_RF5112_DB_2GHZ},
277 {6, AR5K_RF_OB_5GHZ, AR5K_RF5112_OB_5GHZ},
278 {6, AR5K_RF_DB_5GHZ, AR5K_RF5112_DB_5GHZ},
279 {6, AR5K_RF_FIXED_BIAS_A, AR5K_RF5112_FIXED_BIAS_A},
280 {6, AR5K_RF_FIXED_BIAS_B, AR5K_RF5112_FIXED_BIAS_B},
281 {6, AR5K_RF_XPD_SEL, AR5K_RF5112_XPD_SEL},
282 {6, AR5K_RF_XPD_GAIN, AR5K_RF5112_XPD_GAIN},
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]283 {6, AR5K_RF_PWD_130, AR5K_RF5112_PWD(130)},
284 {6, AR5K_RF_PWD_131, AR5K_RF5112_PWD(131)},
285 {6, AR5K_RF_PWD_132, AR5K_RF5112_PWD(132)},
286 {6, AR5K_RF_PWD_136, AR5K_RF5112_PWD(136)},
287 {6, AR5K_RF_PWD_137, AR5K_RF5112_PWD(137)},
288 {6, AR5K_RF_PWD_138, AR5K_RF5112_PWD(138)},
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]289 {7, AR5K_RF_GAIN_I, AR5K_RF5112X_GAIN_I},
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]290 {7, AR5K_RF_MIXVGA_OVR, AR5K_RF5112X_MIXVGA_OVR},
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]291 {7, AR5K_RF_MIXGAIN_OVR, AR5K_RF5112X_MIXGAIN_OVR},
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]292 {7, AR5K_RF_MIXGAIN_STEP, AR5K_RF5112X_MIXGAIN_STEP},
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]293 {7, AR5K_RF_PD_DELAY_A, AR5K_RF5112X_PD_DELAY_A},
294 {7, AR5K_RF_PD_DELAY_B, AR5K_RF5112X_PD_DELAY_B},
295 {7, AR5K_RF_PD_DELAY_XR, AR5K_RF5112X_PD_DELAY_XR},
296 {7, AR5K_RF_PD_PERIOD_A, AR5K_RF5112X_PD_PERIOD_A},
297 {7, AR5K_RF_PD_PERIOD_B, AR5K_RF5112X_PD_PERIOD_B},
298 {7, AR5K_RF_PD_PERIOD_XR, AR5K_RF5112X_PD_PERIOD_XR},
299};
300
301/* Default mode specific settings */
302static const struct ath5k_ini_rfbuffer rfb_5112[] = {
Nick Kossifidis8c2b4182010-11-23 21:51:38 +0200[diff] [blame]303 /* BANK / C.R. A/XR B G */
304 { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
305 { 2, 0x98d0, { 0x03060408, 0x03060408, 0x03060408 } },
306 { 3, 0x98dc, { 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
307 { 6, 0x989c, { 0x00a00000, 0x00a00000, 0x00a00000 } },
308 { 6, 0x989c, { 0x000a0000, 0x000a0000, 0x000a0000 } },
309 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
310 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
311 { 6, 0x989c, { 0x00660000, 0x00660000, 0x00660000 } },
312 { 6, 0x989c, { 0x00db0000, 0x00db0000, 0x00db0000 } },
313 { 6, 0x989c, { 0x00f10000, 0x00f10000, 0x00f10000 } },
314 { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
315 { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
316 { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
317 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
318 { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
319 { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
320 { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
321 { 6, 0x989c, { 0x008b0000, 0x008b0000, 0x008b0000 } },
322 { 6, 0x989c, { 0x00600000, 0x00600000, 0x00600000 } },
323 { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
324 { 6, 0x989c, { 0x00840000, 0x00840000, 0x00840000 } },
325 { 6, 0x989c, { 0x00640000, 0x00640000, 0x00640000 } },
326 { 6, 0x989c, { 0x00200000, 0x00200000, 0x00200000 } },
327 { 6, 0x989c, { 0x00240000, 0x00240000, 0x00240000 } },
328 { 6, 0x989c, { 0x00250000, 0x00250000, 0x00250000 } },
329 { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
330 { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
331 { 6, 0x989c, { 0x00510000, 0x00510000, 0x00510000 } },
332 { 6, 0x989c, { 0x1c040000, 0x1c040000, 0x1c040000 } },
333 { 6, 0x989c, { 0x000a0000, 0x000a0000, 0x000a0000 } },
334 { 6, 0x989c, { 0x00a10000, 0x00a10000, 0x00a10000 } },
335 { 6, 0x989c, { 0x00400000, 0x00400000, 0x00400000 } },
336 { 6, 0x989c, { 0x03090000, 0x03090000, 0x03090000 } },
337 { 6, 0x989c, { 0x06000000, 0x06000000, 0x06000000 } },
338 { 6, 0x989c, { 0x000000b0, 0x000000a8, 0x000000a8 } },
339 { 6, 0x989c, { 0x0000002e, 0x0000002e, 0x0000002e } },
340 { 6, 0x989c, { 0x006c4a41, 0x006c4af1, 0x006c4a61 } },
341 { 6, 0x989c, { 0x0050892a, 0x0050892b, 0x0050892b } },
342 { 6, 0x989c, { 0x00842400, 0x00842400, 0x00842400 } },
343 { 6, 0x989c, { 0x00c69200, 0x00c69200, 0x00c69200 } },
344 { 6, 0x98d0, { 0x0002000c, 0x0002000c, 0x0002000c } },
345 { 7, 0x989c, { 0x00000094, 0x00000094, 0x00000094 } },
346 { 7, 0x989c, { 0x00000091, 0x00000091, 0x00000091 } },
347 { 7, 0x989c, { 0x0000000a, 0x00000012, 0x00000012 } },
348 { 7, 0x989c, { 0x00000080, 0x00000080, 0x00000080 } },
349 { 7, 0x989c, { 0x000000c1, 0x000000c1, 0x000000c1 } },
350 { 7, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
351 { 7, 0x989c, { 0x000000f0, 0x000000f0, 0x000000f0 } },
352 { 7, 0x989c, { 0x00000022, 0x00000022, 0x00000022 } },
353 { 7, 0x989c, { 0x00000092, 0x00000092, 0x00000092 } },
354 { 7, 0x989c, { 0x000000d4, 0x000000d4, 0x000000d4 } },
355 { 7, 0x989c, { 0x000014cc, 0x000014cc, 0x000014cc } },
356 { 7, 0x989c, { 0x0000048c, 0x0000048c, 0x0000048c } },
357 { 7, 0x98c4, { 0x00000003, 0x00000003, 0x00000003 } },
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]358};
359
360/* RFX112A (Derby 2) */
361
362/* BANK 6 len pos col */
363#define AR5K_RF5112A_OB_2GHZ { 3, 287, 0 }
364#define AR5K_RF5112A_DB_2GHZ { 3, 290, 0 }
365
366#define AR5K_RF5112A_OB_5GHZ { 3, 279, 0 }
367#define AR5K_RF5112A_DB_5GHZ { 3, 282, 0 }
368
369#define AR5K_RF5112A_FIXED_BIAS_A { 1, 278, 0 }
370#define AR5K_RF5112A_FIXED_BIAS_B { 1, 277, 0 }
371
372#define AR5K_RF5112A_XPD_SEL { 1, 302, 0 }
373#define AR5K_RF5112A_PDGAINLO { 2, 270, 0 }
374#define AR5K_RF5112A_PDGAINHI { 2, 257, 0 }
375
376/* Access to PWD registers */
377#define AR5K_RF5112A_PWD(_n) { 1, (306 - _n), 3 }
378
379/* Voltage regulators */
380#define AR5K_RF5112A_HIGH_VC_CP { 2, 90, 2 }
381#define AR5K_RF5112A_MID_VC_CP { 2, 92, 2 }
382#define AR5K_RF5112A_LOW_VC_CP { 2, 94, 2 }
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]383#define AR5K_RF5112A_PUSH_UP { 1, 254, 2 }
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]384
385/* Power consumption */
386#define AR5K_RF5112A_PAD2GND { 1, 281, 1 }
387#define AR5K_RF5112A_XB2_LVL { 2, 1, 3 }
388#define AR5K_RF5112A_XB5_LVL { 2, 3, 3 }
389
390static const struct ath5k_rf_reg rf_regs_5112a[] = {
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]391 {2, AR5K_RF_TURBO, AR5K_RF5112X_RF_TURBO},
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]392 {6, AR5K_RF_OB_2GHZ, AR5K_RF5112A_OB_2GHZ},
393 {6, AR5K_RF_DB_2GHZ, AR5K_RF5112A_DB_2GHZ},
394 {6, AR5K_RF_OB_5GHZ, AR5K_RF5112A_OB_5GHZ},
395 {6, AR5K_RF_DB_5GHZ, AR5K_RF5112A_DB_5GHZ},
396 {6, AR5K_RF_FIXED_BIAS_A, AR5K_RF5112A_FIXED_BIAS_A},
397 {6, AR5K_RF_FIXED_BIAS_B, AR5K_RF5112A_FIXED_BIAS_B},
398 {6, AR5K_RF_XPD_SEL, AR5K_RF5112A_XPD_SEL},
399 {6, AR5K_RF_PD_GAIN_LO, AR5K_RF5112A_PDGAINLO},
400 {6, AR5K_RF_PD_GAIN_HI, AR5K_RF5112A_PDGAINHI},
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]401 {6, AR5K_RF_PWD_130, AR5K_RF5112A_PWD(130)},
402 {6, AR5K_RF_PWD_131, AR5K_RF5112A_PWD(131)},
403 {6, AR5K_RF_PWD_132, AR5K_RF5112A_PWD(132)},
404 {6, AR5K_RF_PWD_136, AR5K_RF5112A_PWD(136)},
405 {6, AR5K_RF_PWD_137, AR5K_RF5112A_PWD(137)},
406 {6, AR5K_RF_PWD_138, AR5K_RF5112A_PWD(138)},
407 {6, AR5K_RF_PWD_166, AR5K_RF5112A_PWD(166)},
408 {6, AR5K_RF_PWD_167, AR5K_RF5112A_PWD(167)},
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]409 {6, AR5K_RF_HIGH_VC_CP, AR5K_RF5112A_HIGH_VC_CP},
410 {6, AR5K_RF_MID_VC_CP, AR5K_RF5112A_MID_VC_CP},
411 {6, AR5K_RF_LOW_VC_CP, AR5K_RF5112A_LOW_VC_CP},
412 {6, AR5K_RF_PUSH_UP, AR5K_RF5112A_PUSH_UP},
413 {6, AR5K_RF_PAD2GND, AR5K_RF5112A_PAD2GND},
414 {6, AR5K_RF_XB2_LVL, AR5K_RF5112A_XB2_LVL},
415 {6, AR5K_RF_XB5_LVL, AR5K_RF5112A_XB5_LVL},
416 {7, AR5K_RF_GAIN_I, AR5K_RF5112X_GAIN_I},
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]417 {7, AR5K_RF_MIXVGA_OVR, AR5K_RF5112X_MIXVGA_OVR},
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]418 {7, AR5K_RF_MIXGAIN_OVR, AR5K_RF5112X_MIXGAIN_OVR},
Nick Kossifidis8892e4e2009-02-09 06:06:34 +0200[diff] [blame]419 {7, AR5K_RF_MIXGAIN_STEP, AR5K_RF5112X_MIXGAIN_STEP},
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]420 {7, AR5K_RF_PD_DELAY_A, AR5K_RF5112X_PD_DELAY_A},
421 {7, AR5K_RF_PD_DELAY_B, AR5K_RF5112X_PD_DELAY_B},
422 {7, AR5K_RF_PD_DELAY_XR, AR5K_RF5112X_PD_DELAY_XR},
423 {7, AR5K_RF_PD_PERIOD_A, AR5K_RF5112X_PD_PERIOD_A},
424 {7, AR5K_RF_PD_PERIOD_B, AR5K_RF5112X_PD_PERIOD_B},
425 {7, AR5K_RF_PD_PERIOD_XR, AR5K_RF5112X_PD_PERIOD_XR},
426};
427
428/* Default mode specific settings */
429static const struct ath5k_ini_rfbuffer rfb_5112a[] = {
Nick Kossifidis8c2b4182010-11-23 21:51:38 +0200[diff] [blame]430 /* BANK / C.R. A/XR B G */
431 { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
432 { 2, 0x98d0, { 0x03060408, 0x03060408, 0x03060408 } },
433 { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
434 { 6, 0x989c, { 0x0f000000, 0x0f000000, 0x0f000000 } },
435 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
436 { 6, 0x989c, { 0x00800000, 0x00800000, 0x00800000 } },
437 { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
438 { 6, 0x989c, { 0x00010000, 0x00010000, 0x00010000 } },
439 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
440 { 6, 0x989c, { 0x00180000, 0x00180000, 0x00180000 } },
441 { 6, 0x989c, { 0x00600000, 0x006e0000, 0x006e0000 } },
442 { 6, 0x989c, { 0x00c70000, 0x00c70000, 0x00c70000 } },
443 { 6, 0x989c, { 0x004b0000, 0x004b0000, 0x004b0000 } },
444 { 6, 0x989c, { 0x04480000, 0x04480000, 0x04480000 } },
445 { 6, 0x989c, { 0x004c0000, 0x004c0000, 0x004c0000 } },
446 { 6, 0x989c, { 0x00e40000, 0x00e40000, 0x00e40000 } },
447 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
448 { 6, 0x989c, { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
449 { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
450 { 6, 0x989c, { 0x043f0000, 0x043f0000, 0x043f0000 } },
451 { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
452 { 6, 0x989c, { 0x02190000, 0x02190000, 0x02190000 } },
453 { 6, 0x989c, { 0x00240000, 0x00240000, 0x00240000 } },
454 { 6, 0x989c, { 0x00b40000, 0x00b40000, 0x00b40000 } },
455 { 6, 0x989c, { 0x00990000, 0x00990000, 0x00990000 } },
456 { 6, 0x989c, { 0x00500000, 0x00500000, 0x00500000 } },
457 { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
458 { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
459 { 6, 0x989c, { 0xc0320000, 0xc0320000, 0xc0320000 } },
460 { 6, 0x989c, { 0x01740000, 0x01740000, 0x01740000 } },
461 { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
462 { 6, 0x989c, { 0x86280000, 0x86280000, 0x86280000 } },
463 { 6, 0x989c, { 0x31840000, 0x31840000, 0x31840000 } },
464 { 6, 0x989c, { 0x00f20080, 0x00f20080, 0x00f20080 } },
465 { 6, 0x989c, { 0x00270019, 0x00270019, 0x00270019 } },
466 { 6, 0x989c, { 0x00000003, 0x00000003, 0x00000003 } },
467 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
468 { 6, 0x989c, { 0x000000b2, 0x000000b2, 0x000000b2 } },
469 { 6, 0x989c, { 0x00b02084, 0x00b02084, 0x00b02084 } },
470 { 6, 0x989c, { 0x004125a4, 0x004125a4, 0x004125a4 } },
471 { 6, 0x989c, { 0x00119220, 0x00119220, 0x00119220 } },
472 { 6, 0x989c, { 0x001a4800, 0x001a4800, 0x001a4800 } },
473 { 6, 0x98d8, { 0x000b0230, 0x000b0230, 0x000b0230 } },
474 { 7, 0x989c, { 0x00000094, 0x00000094, 0x00000094 } },
475 { 7, 0x989c, { 0x00000091, 0x00000091, 0x00000091 } },
476 { 7, 0x989c, { 0x00000012, 0x00000012, 0x00000012 } },
477 { 7, 0x989c, { 0x00000080, 0x00000080, 0x00000080 } },
478 { 7, 0x989c, { 0x000000d9, 0x000000d9, 0x000000d9 } },
479 { 7, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
480 { 7, 0x989c, { 0x000000f0, 0x000000f0, 0x000000f0 } },
481 { 7, 0x989c, { 0x000000a2, 0x000000a2, 0x000000a2 } },
482 { 7, 0x989c, { 0x00000052, 0x00000052, 0x00000052 } },
483 { 7, 0x989c, { 0x000000d4, 0x000000d4, 0x000000d4 } },
484 { 7, 0x989c, { 0x000014cc, 0x000014cc, 0x000014cc } },
485 { 7, 0x989c, { 0x0000048c, 0x0000048c, 0x0000048c } },
486 { 7, 0x98c4, { 0x00000003, 0x00000003, 0x00000003 } },
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]487};
488
489
490
491/******************\
492* RF2413 (Griffin) *
493\******************/
494
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]495/* BANK 2 len pos col */
496#define AR5K_RF2413_RF_TURBO { 1, 1, 2 }
497
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]498/* BANK 6 len pos col */
499#define AR5K_RF2413_OB_2GHZ { 3, 168, 0 }
500#define AR5K_RF2413_DB_2GHZ { 3, 165, 0 }
501
502static const struct ath5k_rf_reg rf_regs_2413[] = {
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]503 {2, AR5K_RF_TURBO, AR5K_RF2413_RF_TURBO},
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]504 {6, AR5K_RF_OB_2GHZ, AR5K_RF2413_OB_2GHZ},
505 {6, AR5K_RF_DB_2GHZ, AR5K_RF2413_DB_2GHZ},
506};
507
508/* Default mode specific settings
509 * XXX: a/aTurbo ???
510 */
511static const struct ath5k_ini_rfbuffer rfb_2413[] = {
Nick Kossifidis8c2b4182010-11-23 21:51:38 +0200[diff] [blame]512 /* BANK / C.R. A/XR B G */
513 { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
514 { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
515 { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
516 { 6, 0x989c, { 0xf0000000, 0xf0000000, 0xf0000000 } },
517 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
518 { 6, 0x989c, { 0x03000000, 0x03000000, 0x03000000 } },
519 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
520 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
521 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
522 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
523 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
524 { 6, 0x989c, { 0x40400000, 0x40400000, 0x40400000 } },
525 { 6, 0x989c, { 0x65050000, 0x65050000, 0x65050000 } },
526 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
527 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
528 { 6, 0x989c, { 0x00420000, 0x00420000, 0x00420000 } },
529 { 6, 0x989c, { 0x00b50000, 0x00b50000, 0x00b50000 } },
530 { 6, 0x989c, { 0x00030000, 0x00030000, 0x00030000 } },
531 { 6, 0x989c, { 0x00f70000, 0x00f70000, 0x00f70000 } },
532 { 6, 0x989c, { 0x009d0000, 0x009d0000, 0x009d0000 } },
533 { 6, 0x989c, { 0x00220000, 0x00220000, 0x00220000 } },
534 { 6, 0x989c, { 0x04220000, 0x04220000, 0x04220000 } },
535 { 6, 0x989c, { 0x00230018, 0x00230018, 0x00230018 } },
536 { 6, 0x989c, { 0x00280000, 0x00280060, 0x00280060 } },
537 { 6, 0x989c, { 0x005000c0, 0x005000c3, 0x005000c3 } },
538 { 6, 0x989c, { 0x0004007f, 0x0004007f, 0x0004007f } },
539 { 6, 0x989c, { 0x00000458, 0x00000458, 0x00000458 } },
540 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
541 { 6, 0x989c, { 0x0000c000, 0x0000c000, 0x0000c000 } },
542 { 6, 0x98d8, { 0x00400230, 0x00400230, 0x00400230 } },
543 { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
544 { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
545 { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]546};
547
548
549
550/***************************\
551* RF2315/RF2316 (Cobra SoC) *
552\***************************/
553
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]554/* BANK 2 len pos col */
555#define AR5K_RF2316_RF_TURBO { 1, 1, 2 }
556
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]557/* BANK 6 len pos col */
558#define AR5K_RF2316_OB_2GHZ { 3, 178, 0 }
559#define AR5K_RF2316_DB_2GHZ { 3, 175, 0 }
560
561static const struct ath5k_rf_reg rf_regs_2316[] = {
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]562 {2, AR5K_RF_TURBO, AR5K_RF2316_RF_TURBO},
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]563 {6, AR5K_RF_OB_2GHZ, AR5K_RF2316_OB_2GHZ},
564 {6, AR5K_RF_DB_2GHZ, AR5K_RF2316_DB_2GHZ},
565};
566
567/* Default mode specific settings */
568static const struct ath5k_ini_rfbuffer rfb_2316[] = {
Nick Kossifidis8c2b4182010-11-23 21:51:38 +0200[diff] [blame]569 /* BANK / C.R. A/XR B G */
570 { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
571 { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
572 { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
573 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
574 { 6, 0x989c, { 0xc0000000, 0xc0000000, 0xc0000000 } },
575 { 6, 0x989c, { 0x0f000000, 0x0f000000, 0x0f000000 } },
576 { 6, 0x989c, { 0x02000000, 0x02000000, 0x02000000 } },
577 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
578 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
579 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
580 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
581 { 6, 0x989c, { 0xf8000000, 0xf8000000, 0xf8000000 } },
582 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
583 { 6, 0x989c, { 0x95150000, 0x95150000, 0x95150000 } },
584 { 6, 0x989c, { 0xc1000000, 0xc1000000, 0xc1000000 } },
585 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
586 { 6, 0x989c, { 0x00080000, 0x00080000, 0x00080000 } },
587 { 6, 0x989c, { 0x00d50000, 0x00d50000, 0x00d50000 } },
588 { 6, 0x989c, { 0x000e0000, 0x000e0000, 0x000e0000 } },
589 { 6, 0x989c, { 0x00dc0000, 0x00dc0000, 0x00dc0000 } },
590 { 6, 0x989c, { 0x00770000, 0x00770000, 0x00770000 } },
591 { 6, 0x989c, { 0x008a0000, 0x008a0000, 0x008a0000 } },
592 { 6, 0x989c, { 0x10880000, 0x10880000, 0x10880000 } },
593 { 6, 0x989c, { 0x008c0060, 0x008c0060, 0x008c0060 } },
594 { 6, 0x989c, { 0x00a00000, 0x00a00080, 0x00a00080 } },
595 { 6, 0x989c, { 0x00400000, 0x0040000d, 0x0040000d } },
596 { 6, 0x989c, { 0x00110400, 0x00110400, 0x00110400 } },
597 { 6, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
598 { 6, 0x989c, { 0x00000001, 0x00000001, 0x00000001 } },
599 { 6, 0x989c, { 0x00000b00, 0x00000b00, 0x00000b00 } },
600 { 6, 0x989c, { 0x00000be8, 0x00000be8, 0x00000be8 } },
601 { 6, 0x98c0, { 0x00010000, 0x00010000, 0x00010000 } },
602 { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
603 { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
604 { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]605};
606
607
608
609/******************************\
610* RF5413/RF5424 (Eagle/Condor) *
611\******************************/
612
613/* BANK 6 len pos col */
614#define AR5K_RF5413_OB_2GHZ { 3, 241, 0 }
615#define AR5K_RF5413_DB_2GHZ { 3, 238, 0 }
616
617#define AR5K_RF5413_OB_5GHZ { 3, 247, 0 }
618#define AR5K_RF5413_DB_5GHZ { 3, 244, 0 }
619
620#define AR5K_RF5413_PWD_ICLOBUF2G { 3, 131, 3 }
621#define AR5K_RF5413_DERBY_CHAN_SEL_MODE { 1, 291, 2 }
622
623static const struct ath5k_rf_reg rf_regs_5413[] = {
624 {6, AR5K_RF_OB_2GHZ, AR5K_RF5413_OB_2GHZ},
625 {6, AR5K_RF_DB_2GHZ, AR5K_RF5413_DB_2GHZ},
626 {6, AR5K_RF_OB_5GHZ, AR5K_RF5413_OB_5GHZ},
627 {6, AR5K_RF_DB_5GHZ, AR5K_RF5413_DB_5GHZ},
628 {6, AR5K_RF_PWD_ICLOBUF_2G, AR5K_RF5413_PWD_ICLOBUF2G},
629 {6, AR5K_RF_DERBY_CHAN_SEL_MODE, AR5K_RF5413_DERBY_CHAN_SEL_MODE},
630};
631
632/* Default mode specific settings */
633static const struct ath5k_ini_rfbuffer rfb_5413[] = {
Nick Kossifidis8c2b4182010-11-23 21:51:38 +0200[diff] [blame]634 /* BANK / C.R. A/XR B G */
635 { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
636 { 2, 0x98d0, { 0x00000008, 0x00000008, 0x00000008 } },
637 { 3, 0x98dc, { 0x00a000c0, 0x00e000c0, 0x00e000c0 } },
638 { 6, 0x989c, { 0x33000000, 0x33000000, 0x33000000 } },
639 { 6, 0x989c, { 0x01000000, 0x01000000, 0x01000000 } },
640 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
641 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
642 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
643 { 6, 0x989c, { 0x1f000000, 0x1f000000, 0x1f000000 } },
644 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
645 { 6, 0x989c, { 0x00b80000, 0x00b80000, 0x00b80000 } },
646 { 6, 0x989c, { 0x00b70000, 0x00b70000, 0x00b70000 } },
647 { 6, 0x989c, { 0x00840000, 0x00840000, 0x00840000 } },
648 { 6, 0x989c, { 0x00980000, 0x00980000, 0x00980000 } },
649 { 6, 0x989c, { 0x00c00000, 0x00c00000, 0x00c00000 } },
650 { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
651 { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
652 { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
653 { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
654 { 6, 0x989c, { 0x00d70000, 0x00d70000, 0x00d70000 } },
655 { 6, 0x989c, { 0x00610000, 0x00610000, 0x00610000 } },
656 { 6, 0x989c, { 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
657 { 6, 0x989c, { 0x00de0000, 0x00de0000, 0x00de0000 } },
658 { 6, 0x989c, { 0x007f0000, 0x007f0000, 0x007f0000 } },
659 { 6, 0x989c, { 0x043d0000, 0x043d0000, 0x043d0000 } },
660 { 6, 0x989c, { 0x00770000, 0x00770000, 0x00770000 } },
661 { 6, 0x989c, { 0x00440000, 0x00440000, 0x00440000 } },
662 { 6, 0x989c, { 0x00980000, 0x00980000, 0x00980000 } },
663 { 6, 0x989c, { 0x00100080, 0x00100080, 0x00100080 } },
664 { 6, 0x989c, { 0x0005c034, 0x0005c034, 0x0005c034 } },
665 { 6, 0x989c, { 0x003100f0, 0x003100f0, 0x003100f0 } },
666 { 6, 0x989c, { 0x000c011f, 0x000c011f, 0x000c011f } },
667 { 6, 0x989c, { 0x00510040, 0x00510040, 0x00510040 } },
668 { 6, 0x989c, { 0x005000da, 0x005000da, 0x005000da } },
669 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
670 { 6, 0x989c, { 0x00004044, 0x00004044, 0x00004044 } },
671 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
672 { 6, 0x989c, { 0x000060c0, 0x000060c0, 0x000060c0 } },
673 { 6, 0x989c, { 0x00002c00, 0x00003600, 0x00003600 } },
674 { 6, 0x98c8, { 0x00000403, 0x00040403, 0x00040403 } },
675 { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
676 { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
677 { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]678};
679
680
681
682/***************************\
683* RF2425/RF2417 (Swan/Nala) *
684* AR2317 (Spider SoC) *
685\***************************/
686
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]687/* BANK 2 len pos col */
688#define AR5K_RF2425_RF_TURBO { 1, 1, 2 }
689
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]690/* BANK 6 len pos col */
691#define AR5K_RF2425_OB_2GHZ { 3, 193, 0 }
692#define AR5K_RF2425_DB_2GHZ { 3, 190, 0 }
693
694static const struct ath5k_rf_reg rf_regs_2425[] = {
Nick Kossifidis4352fab2010-11-23 21:53:28 +0200[diff] [blame]695 {2, AR5K_RF_TURBO, AR5K_RF2425_RF_TURBO},
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]696 {6, AR5K_RF_OB_2GHZ, AR5K_RF2425_OB_2GHZ},
697 {6, AR5K_RF_DB_2GHZ, AR5K_RF2425_DB_2GHZ},
698};
699
700/* Default mode specific settings
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]701 */
702static const struct ath5k_ini_rfbuffer rfb_2425[] = {
Nick Kossifidis8c2b4182010-11-23 21:51:38 +0200[diff] [blame]703 /* BANK / C.R. A/XR B G */
704 { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
705 { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
706 { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
707 { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
708 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
709 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
710 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
711 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
712 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
713 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
714 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
715 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
716 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
717 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
718 { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
719 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
720 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
721 { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
722 { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
723 { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
724 { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
725 { 6, 0x989c, { 0x00e70000, 0x00e70000, 0x00e70000 } },
726 { 6, 0x989c, { 0x00140000, 0x00140000, 0x00140000 } },
727 { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
728 { 6, 0x989c, { 0x0007001a, 0x0007001a, 0x0007001a } },
729 { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
730 { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
731 { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
732 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
733 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
734 { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
735 { 6, 0x989c, { 0x00001688, 0x00001688, 0x00001688 } },
736 { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
737 { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
738 { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
739 { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]740};
741
742/*
743 * TODO: Handle the few differences with swan during
744 * bank modification and get rid of this
745 */
746static const struct ath5k_ini_rfbuffer rfb_2317[] = {
Nick Kossifidis8c2b4182010-11-23 21:51:38 +0200[diff] [blame]747 /* BANK / C.R. A/XR B G */
748 { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
749 { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
750 { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
751 { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
752 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
753 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
754 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
755 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
756 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
757 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
758 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
759 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
760 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
761 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
762 { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
763 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
764 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
765 { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
766 { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
767 { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
768 { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
769 { 6, 0x989c, { 0x00e70000, 0x00e70000, 0x00e70000 } },
770 { 6, 0x989c, { 0x00140100, 0x00140100, 0x00140100 } },
771 { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
772 { 6, 0x989c, { 0x0007001a, 0x0007001a, 0x0007001a } },
773 { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
774 { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
775 { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
776 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
777 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
778 { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
779 { 6, 0x989c, { 0x00009688, 0x00009688, 0x00009688 } },
780 { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
781 { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
782 { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
783 { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]784};
785
786/*
787 * TODO: Handle the few differences with swan during
788 * bank modification and get rid of this
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]789 */
790static const struct ath5k_ini_rfbuffer rfb_2417[] = {
Nick Kossifidis8c2b4182010-11-23 21:51:38 +0200[diff] [blame]791 /* BANK / C.R. A/XR B G */
792 { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
793 { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
794 { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
795 { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
796 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
797 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
798 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
799 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
800 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
801 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
802 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
803 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
804 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
805 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
806 { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
807 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
808 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
809 { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
810 { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
811 { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
812 { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
813 { 6, 0x989c, { 0x00e70000, 0x80e70000, 0x80e70000 } },
814 { 6, 0x989c, { 0x00140000, 0x00140000, 0x00140000 } },
815 { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
816 { 6, 0x989c, { 0x0007001a, 0x0207001a, 0x0207001a } },
817 { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
818 { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
819 { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
820 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
821 { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
822 { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
823 { 6, 0x989c, { 0x00001688, 0x00001688, 0x00001688 } },
824 { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
825 { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
826 { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
827 { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
Nick Kossifidis33a31822009-02-09 06:00:34 +0200[diff] [blame]828};