Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Support for the Tundra TSI148 VME-PCI Bridge Chip |
| 3 | * |
Martyn Welch | 66bd8db | 2010-02-18 15:12:52 +0000 | [diff] [blame] | 4 | * Author: Martyn Welch <martyn.welch@ge.com> |
| 5 | * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 6 | * |
| 7 | * Based on work by Tom Armistead and Ajit Prem |
| 8 | * Copyright 2004 Motorola Inc. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License as published by the |
| 12 | * Free Software Foundation; either version 2 of the License, or (at your |
| 13 | * option) any later version. |
| 14 | */ |
| 15 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 16 | #include <linux/module.h> |
| 17 | #include <linux/moduleparam.h> |
| 18 | #include <linux/mm.h> |
| 19 | #include <linux/types.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <linux/proc_fs.h> |
| 22 | #include <linux/pci.h> |
| 23 | #include <linux/poll.h> |
| 24 | #include <linux/dma-mapping.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/spinlock.h> |
Greg Kroah-Hartman | 6af783c | 2009-10-12 15:00:08 -0700 | [diff] [blame] | 27 | #include <linux/sched.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 28 | #include <linux/slab.h> |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 29 | #include <linux/time.h> |
| 30 | #include <linux/io.h> |
| 31 | #include <linux/uaccess.h> |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 32 | #include <linux/byteorder/generic.h> |
Greg Kroah-Hartman | db3b9e9 | 2012-04-26 12:34:58 -0700 | [diff] [blame] | 33 | #include <linux/vme.h> |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 34 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 35 | #include "../vme_bridge.h" |
| 36 | #include "vme_tsi148.h" |
| 37 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 38 | static int tsi148_probe(struct pci_dev *, const struct pci_device_id *); |
| 39 | static void tsi148_remove(struct pci_dev *); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 40 | |
| 41 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 42 | /* Module parameter */ |
Rusty Russell | 90ab5ee | 2012-01-13 09:32:20 +1030 | [diff] [blame] | 43 | static bool err_chk; |
Martyn Welch | 638f199 | 2009-12-15 08:42:49 +0000 | [diff] [blame] | 44 | static int geoid; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 45 | |
Vincent Bossier | 584721c | 2011-06-03 10:07:39 +0100 | [diff] [blame] | 46 | static const char driver_name[] = "vme_tsi148"; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 47 | |
Jingoo Han | c3a09c1 | 2013-12-03 08:29:48 +0900 | [diff] [blame] | 48 | static const struct pci_device_id tsi148_ids[] = { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 49 | { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) }, |
| 50 | { }, |
| 51 | }; |
| 52 | |
| 53 | static struct pci_driver tsi148_driver = { |
| 54 | .name = driver_name, |
| 55 | .id_table = tsi148_ids, |
| 56 | .probe = tsi148_probe, |
| 57 | .remove = tsi148_remove, |
| 58 | }; |
| 59 | |
| 60 | static void reg_join(unsigned int high, unsigned int low, |
| 61 | unsigned long long *variable) |
| 62 | { |
| 63 | *variable = (unsigned long long)high << 32; |
| 64 | *variable |= (unsigned long long)low; |
| 65 | } |
| 66 | |
| 67 | static void reg_split(unsigned long long variable, unsigned int *high, |
| 68 | unsigned int *low) |
| 69 | { |
| 70 | *low = (unsigned int)variable & 0xFFFFFFFF; |
| 71 | *high = (unsigned int)(variable >> 32); |
| 72 | } |
| 73 | |
| 74 | /* |
| 75 | * Wakes up DMA queue. |
| 76 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 77 | static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge, |
| 78 | int channel_mask) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 79 | { |
| 80 | u32 serviced = 0; |
| 81 | |
| 82 | if (channel_mask & TSI148_LCSR_INTS_DMA0S) { |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 83 | wake_up(&bridge->dma_queue[0]); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 84 | serviced |= TSI148_LCSR_INTC_DMA0C; |
| 85 | } |
| 86 | if (channel_mask & TSI148_LCSR_INTS_DMA1S) { |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 87 | wake_up(&bridge->dma_queue[1]); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 88 | serviced |= TSI148_LCSR_INTC_DMA1C; |
| 89 | } |
| 90 | |
| 91 | return serviced; |
| 92 | } |
| 93 | |
| 94 | /* |
| 95 | * Wake up location monitor queue |
| 96 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 97 | static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 98 | { |
| 99 | int i; |
| 100 | u32 serviced = 0; |
| 101 | |
| 102 | for (i = 0; i < 4; i++) { |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 103 | if (stat & TSI148_LCSR_INTS_LMS[i]) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 104 | /* We only enable interrupts if the callback is set */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 105 | bridge->lm_callback[i](i); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 106 | serviced |= TSI148_LCSR_INTC_LMC[i]; |
| 107 | } |
| 108 | } |
| 109 | |
| 110 | return serviced; |
| 111 | } |
| 112 | |
| 113 | /* |
| 114 | * Wake up mail box queue. |
| 115 | * |
| 116 | * XXX This functionality is not exposed up though API. |
| 117 | */ |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 118 | static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 119 | { |
| 120 | int i; |
| 121 | u32 val; |
| 122 | u32 serviced = 0; |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 123 | struct tsi148_driver *bridge; |
| 124 | |
| 125 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 126 | |
| 127 | for (i = 0; i < 4; i++) { |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 128 | if (stat & TSI148_LCSR_INTS_MBS[i]) { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 129 | val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 130 | dev_err(tsi148_bridge->parent, "VME Mailbox %d received" |
| 131 | ": 0x%x\n", i, val); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 132 | serviced |= TSI148_LCSR_INTC_MBC[i]; |
| 133 | } |
| 134 | } |
| 135 | |
| 136 | return serviced; |
| 137 | } |
| 138 | |
| 139 | /* |
| 140 | * Display error & status message when PERR (PCI) exception interrupt occurs. |
| 141 | */ |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 142 | static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 143 | { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 144 | struct tsi148_driver *bridge; |
| 145 | |
| 146 | bridge = tsi148_bridge->driver_priv; |
| 147 | |
| 148 | dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, " |
| 149 | "attributes: %08x\n", |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 150 | ioread32be(bridge->base + TSI148_LCSR_EDPAU), |
| 151 | ioread32be(bridge->base + TSI148_LCSR_EDPAL), |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 152 | ioread32be(bridge->base + TSI148_LCSR_EDPAT)); |
| 153 | |
| 154 | dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split " |
| 155 | "completion reg: %08x\n", |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 156 | ioread32be(bridge->base + TSI148_LCSR_EDPXA), |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 157 | ioread32be(bridge->base + TSI148_LCSR_EDPXS)); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 158 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 159 | iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 160 | |
| 161 | return TSI148_LCSR_INTC_PERRC; |
| 162 | } |
| 163 | |
| 164 | /* |
| 165 | * Save address and status when VME error interrupt occurs. |
| 166 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 167 | static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 168 | { |
| 169 | unsigned int error_addr_high, error_addr_low; |
| 170 | unsigned long long error_addr; |
| 171 | u32 error_attrib; |
Martyn Welch | e31c51e | 2013-06-11 11:20:17 +0100 | [diff] [blame] | 172 | struct vme_bus_error *error = NULL; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 173 | struct tsi148_driver *bridge; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 174 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 175 | bridge = tsi148_bridge->driver_priv; |
| 176 | |
| 177 | error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); |
| 178 | error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); |
| 179 | error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 180 | |
| 181 | reg_join(error_addr_high, error_addr_low, &error_addr); |
| 182 | |
| 183 | /* Check for exception register overflow (we have lost error data) */ |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 184 | if (error_attrib & TSI148_LCSR_VEAT_VEOF) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 185 | dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow " |
| 186 | "Occurred\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 187 | } |
| 188 | |
Martyn Welch | e31c51e | 2013-06-11 11:20:17 +0100 | [diff] [blame] | 189 | if (err_chk) { |
| 190 | error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC); |
| 191 | if (error) { |
| 192 | error->address = error_addr; |
| 193 | error->attributes = error_attrib; |
| 194 | list_add_tail(&error->list, &tsi148_bridge->vme_errors); |
| 195 | } else { |
| 196 | dev_err(tsi148_bridge->parent, |
| 197 | "Unable to alloc memory for VMEbus Error reporting\n"); |
| 198 | } |
| 199 | } |
| 200 | |
| 201 | if (!error) { |
| 202 | dev_err(tsi148_bridge->parent, |
| 203 | "VME Bus Error at address: 0x%llx, attributes: %08x\n", |
| 204 | error_addr, error_attrib); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 205 | } |
| 206 | |
| 207 | /* Clear Status */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 208 | iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 209 | |
| 210 | return TSI148_LCSR_INTC_VERRC; |
| 211 | } |
| 212 | |
| 213 | /* |
| 214 | * Wake up IACK queue. |
| 215 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 216 | static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 217 | { |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 218 | wake_up(&bridge->iack_queue); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 219 | |
| 220 | return TSI148_LCSR_INTC_IACKC; |
| 221 | } |
| 222 | |
| 223 | /* |
| 224 | * Calling VME bus interrupt callback if provided. |
| 225 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 226 | static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge, |
| 227 | u32 stat) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 228 | { |
| 229 | int vec, i, serviced = 0; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 230 | struct tsi148_driver *bridge; |
| 231 | |
| 232 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 233 | |
| 234 | for (i = 7; i > 0; i--) { |
| 235 | if (stat & (1 << i)) { |
| 236 | /* |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 237 | * Note: Even though the registers are defined as |
| 238 | * 32-bits in the spec, we only want to issue 8-bit |
| 239 | * IACK cycles on the bus, read from offset 3. |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 240 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 241 | vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 242 | |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 243 | vme_irq_handler(tsi148_bridge, i, vec); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 244 | |
| 245 | serviced |= (1 << i); |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | return serviced; |
| 250 | } |
| 251 | |
| 252 | /* |
| 253 | * Top level interrupt handler. Clears appropriate interrupt status bits and |
| 254 | * then calls appropriate sub handler(s). |
| 255 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 256 | static irqreturn_t tsi148_irqhandler(int irq, void *ptr) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 257 | { |
| 258 | u32 stat, enable, serviced = 0; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 259 | struct vme_bridge *tsi148_bridge; |
| 260 | struct tsi148_driver *bridge; |
| 261 | |
| 262 | tsi148_bridge = ptr; |
| 263 | |
| 264 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 265 | |
| 266 | /* Determine which interrupts are unmasked and set */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 267 | enable = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
| 268 | stat = ioread32be(bridge->base + TSI148_LCSR_INTS); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 269 | |
| 270 | /* Only look at unmasked interrupts */ |
| 271 | stat &= enable; |
| 272 | |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 273 | if (unlikely(!stat)) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 274 | return IRQ_NONE; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 275 | |
| 276 | /* Call subhandlers as appropriate */ |
| 277 | /* DMA irqs */ |
| 278 | if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S)) |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 279 | serviced |= tsi148_DMA_irqhandler(bridge, stat); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 280 | |
| 281 | /* Location monitor irqs */ |
| 282 | if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S | |
| 283 | TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S)) |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 284 | serviced |= tsi148_LM_irqhandler(bridge, stat); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 285 | |
| 286 | /* Mail box irqs */ |
| 287 | if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S | |
| 288 | TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S)) |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 289 | serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 290 | |
| 291 | /* PCI bus error */ |
| 292 | if (stat & TSI148_LCSR_INTS_PERRS) |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 293 | serviced |= tsi148_PERR_irqhandler(tsi148_bridge); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 294 | |
| 295 | /* VME bus error */ |
| 296 | if (stat & TSI148_LCSR_INTS_VERRS) |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 297 | serviced |= tsi148_VERR_irqhandler(tsi148_bridge); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 298 | |
| 299 | /* IACK irq */ |
| 300 | if (stat & TSI148_LCSR_INTS_IACKS) |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 301 | serviced |= tsi148_IACK_irqhandler(bridge); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 302 | |
| 303 | /* VME bus irqs */ |
| 304 | if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S | |
| 305 | TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S | |
| 306 | TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S | |
| 307 | TSI148_LCSR_INTS_IRQ1S)) |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 308 | serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 309 | |
| 310 | /* Clear serviced interrupts */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 311 | iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 312 | |
| 313 | return IRQ_HANDLED; |
| 314 | } |
| 315 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 316 | static int tsi148_irq_init(struct vme_bridge *tsi148_bridge) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 317 | { |
| 318 | int result; |
| 319 | unsigned int tmp; |
| 320 | struct pci_dev *pdev; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 321 | struct tsi148_driver *bridge; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 322 | |
Aaron Sierra | 177581fa | 2014-04-03 14:48:27 -0500 | [diff] [blame] | 323 | pdev = to_pci_dev(tsi148_bridge->parent); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 324 | |
| 325 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 326 | |
| 327 | /* Initialise list for VME bus errors */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 328 | INIT_LIST_HEAD(&tsi148_bridge->vme_errors); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 329 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 330 | mutex_init(&tsi148_bridge->irq_mtx); |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 331 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 332 | result = request_irq(pdev->irq, |
| 333 | tsi148_irqhandler, |
| 334 | IRQF_SHARED, |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 335 | driver_name, tsi148_bridge); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 336 | if (result) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 337 | dev_err(tsi148_bridge->parent, "Can't get assigned pci irq " |
| 338 | "vector %02X\n", pdev->irq); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 339 | return result; |
| 340 | } |
| 341 | |
| 342 | /* Enable and unmask interrupts */ |
| 343 | tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO | |
| 344 | TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO | |
| 345 | TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO | |
| 346 | TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO | |
| 347 | TSI148_LCSR_INTEO_IACKEO; |
| 348 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 349 | /* This leaves the following interrupts masked. |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 350 | * TSI148_LCSR_INTEO_VIEEO |
| 351 | * TSI148_LCSR_INTEO_SYSFLEO |
| 352 | * TSI148_LCSR_INTEO_ACFLEO |
| 353 | */ |
| 354 | |
| 355 | /* Don't enable Location Monitor interrupts here - they will be |
| 356 | * enabled when the location monitors are properly configured and |
| 357 | * a callback has been attached. |
| 358 | * TSI148_LCSR_INTEO_LM0EO |
| 359 | * TSI148_LCSR_INTEO_LM1EO |
| 360 | * TSI148_LCSR_INTEO_LM2EO |
| 361 | * TSI148_LCSR_INTEO_LM3EO |
| 362 | */ |
| 363 | |
| 364 | /* Don't enable VME interrupts until we add a handler, else the board |
| 365 | * will respond to it and we don't want that unless it knows how to |
| 366 | * properly deal with it. |
| 367 | * TSI148_LCSR_INTEO_IRQ7EO |
| 368 | * TSI148_LCSR_INTEO_IRQ6EO |
| 369 | * TSI148_LCSR_INTEO_IRQ5EO |
| 370 | * TSI148_LCSR_INTEO_IRQ4EO |
| 371 | * TSI148_LCSR_INTEO_IRQ3EO |
| 372 | * TSI148_LCSR_INTEO_IRQ2EO |
| 373 | * TSI148_LCSR_INTEO_IRQ1EO |
| 374 | */ |
| 375 | |
| 376 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
| 377 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); |
| 378 | |
| 379 | return 0; |
| 380 | } |
| 381 | |
Emilio G. Cota | a82ad05 | 2010-11-12 11:14:47 +0000 | [diff] [blame] | 382 | static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge, |
| 383 | struct pci_dev *pdev) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 384 | { |
Emilio G. Cota | a82ad05 | 2010-11-12 11:14:47 +0000 | [diff] [blame] | 385 | struct tsi148_driver *bridge = tsi148_bridge->driver_priv; |
| 386 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 387 | /* Turn off interrupts */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 388 | iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO); |
| 389 | iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 390 | |
| 391 | /* Clear all interrupts */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 392 | iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 393 | |
| 394 | /* Detach interrupt handler */ |
Emilio G. Cota | a82ad05 | 2010-11-12 11:14:47 +0000 | [diff] [blame] | 395 | free_irq(pdev->irq, tsi148_bridge); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 396 | } |
| 397 | |
| 398 | /* |
| 399 | * Check to see if an IACk has been received, return true (1) or false (0). |
| 400 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 401 | static int tsi148_iack_received(struct tsi148_driver *bridge) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 402 | { |
| 403 | u32 tmp; |
| 404 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 405 | tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 406 | |
| 407 | if (tmp & TSI148_LCSR_VICR_IRQS) |
| 408 | return 0; |
| 409 | else |
| 410 | return 1; |
| 411 | } |
| 412 | |
| 413 | /* |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 414 | * Configure VME interrupt |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 415 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 416 | static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level, |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 417 | int state, int sync) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 418 | { |
Martyn Welch | 7515502 | 2009-08-11 13:50:49 +0100 | [diff] [blame] | 419 | struct pci_dev *pdev; |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 420 | u32 tmp; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 421 | struct tsi148_driver *bridge; |
| 422 | |
| 423 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 424 | |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 425 | /* We need to do the ordering differently for enabling and disabling */ |
| 426 | if (state == 0) { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 427 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 428 | tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1]; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 429 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); |
Martyn Welch | df45517 | 2009-08-05 17:38:31 +0100 | [diff] [blame] | 430 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 431 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
Martyn Welch | df45517 | 2009-08-05 17:38:31 +0100 | [diff] [blame] | 432 | tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1]; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 433 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
Martyn Welch | 7515502 | 2009-08-11 13:50:49 +0100 | [diff] [blame] | 434 | |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 435 | if (sync != 0) { |
Aaron Sierra | 177581fa | 2014-04-03 14:48:27 -0500 | [diff] [blame] | 436 | pdev = to_pci_dev(tsi148_bridge->parent); |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 437 | synchronize_irq(pdev->irq); |
| 438 | } |
| 439 | } else { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 440 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 441 | tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1]; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 442 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 443 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 444 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 445 | tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1]; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 446 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 447 | } |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 448 | } |
| 449 | |
| 450 | /* |
| 451 | * Generate a VME bus interrupt at the requested level & vector. Wait for |
| 452 | * interrupt to be acked. |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 453 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 454 | static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level, |
| 455 | int statid) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 456 | { |
| 457 | u32 tmp; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 458 | struct tsi148_driver *bridge; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 459 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 460 | bridge = tsi148_bridge->driver_priv; |
| 461 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 462 | mutex_lock(&bridge->vme_int); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 463 | |
| 464 | /* Read VICR register */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 465 | tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 466 | |
| 467 | /* Set Status/ID */ |
| 468 | tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) | |
| 469 | (statid & TSI148_LCSR_VICR_STID_M); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 470 | iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 471 | |
| 472 | /* Assert VMEbus IRQ */ |
| 473 | tmp = tmp | TSI148_LCSR_VICR_IRQL[level]; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 474 | iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 475 | |
| 476 | /* XXX Consider implementing a timeout? */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 477 | wait_event_interruptible(bridge->iack_queue, |
| 478 | tsi148_iack_received(bridge)); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 479 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 480 | mutex_unlock(&bridge->vme_int); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 481 | |
| 482 | return 0; |
| 483 | } |
| 484 | |
| 485 | /* |
| 486 | * Find the first error in this address range |
| 487 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 488 | static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge, |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 489 | u32 aspace, unsigned long long address, size_t count) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 490 | { |
| 491 | struct list_head *err_pos; |
| 492 | struct vme_bus_error *vme_err, *valid = NULL; |
| 493 | unsigned long long bound; |
| 494 | |
| 495 | bound = address + count; |
| 496 | |
| 497 | /* |
| 498 | * XXX We are currently not looking at the address space when parsing |
| 499 | * for errors. This is because parsing the Address Modifier Codes |
| 500 | * is going to be quite resource intensive to do properly. We |
| 501 | * should be OK just looking at the addresses and this is certainly |
| 502 | * much better than what we had before. |
| 503 | */ |
| 504 | err_pos = NULL; |
| 505 | /* Iterate through errors */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 506 | list_for_each(err_pos, &tsi148_bridge->vme_errors) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 507 | vme_err = list_entry(err_pos, struct vme_bus_error, list); |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 508 | if ((vme_err->address >= address) && |
| 509 | (vme_err->address < bound)) { |
| 510 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 511 | valid = vme_err; |
| 512 | break; |
| 513 | } |
| 514 | } |
| 515 | |
| 516 | return valid; |
| 517 | } |
| 518 | |
| 519 | /* |
| 520 | * Clear errors in the provided address range. |
| 521 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 522 | static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge, |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 523 | u32 aspace, unsigned long long address, size_t count) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 524 | { |
| 525 | struct list_head *err_pos, *temp; |
| 526 | struct vme_bus_error *vme_err; |
| 527 | unsigned long long bound; |
| 528 | |
| 529 | bound = address + count; |
| 530 | |
| 531 | /* |
| 532 | * XXX We are currently not looking at the address space when parsing |
| 533 | * for errors. This is because parsing the Address Modifier Codes |
| 534 | * is going to be quite resource intensive to do properly. We |
| 535 | * should be OK just looking at the addresses and this is certainly |
| 536 | * much better than what we had before. |
| 537 | */ |
| 538 | err_pos = NULL; |
| 539 | /* Iterate through errors */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 540 | list_for_each_safe(err_pos, temp, &tsi148_bridge->vme_errors) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 541 | vme_err = list_entry(err_pos, struct vme_bus_error, list); |
| 542 | |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 543 | if ((vme_err->address >= address) && |
| 544 | (vme_err->address < bound)) { |
| 545 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 546 | list_del(err_pos); |
| 547 | kfree(vme_err); |
| 548 | } |
| 549 | } |
| 550 | } |
| 551 | |
| 552 | /* |
| 553 | * Initialize a slave window with the requested attributes. |
| 554 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 555 | static int tsi148_slave_set(struct vme_slave_resource *image, int enabled, |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 556 | unsigned long long vme_base, unsigned long long size, |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 557 | dma_addr_t pci_base, u32 aspace, u32 cycle) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 558 | { |
| 559 | unsigned int i, addr = 0, granularity = 0; |
| 560 | unsigned int temp_ctl = 0; |
| 561 | unsigned int vme_base_low, vme_base_high; |
| 562 | unsigned int vme_bound_low, vme_bound_high; |
| 563 | unsigned int pci_offset_low, pci_offset_high; |
| 564 | unsigned long long vme_bound, pci_offset; |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 565 | struct vme_bridge *tsi148_bridge; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 566 | struct tsi148_driver *bridge; |
| 567 | |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 568 | tsi148_bridge = image->parent; |
| 569 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 570 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 571 | i = image->number; |
| 572 | |
| 573 | switch (aspace) { |
| 574 | case VME_A16: |
| 575 | granularity = 0x10; |
| 576 | addr |= TSI148_LCSR_ITAT_AS_A16; |
| 577 | break; |
| 578 | case VME_A24: |
| 579 | granularity = 0x1000; |
| 580 | addr |= TSI148_LCSR_ITAT_AS_A24; |
| 581 | break; |
| 582 | case VME_A32: |
| 583 | granularity = 0x10000; |
| 584 | addr |= TSI148_LCSR_ITAT_AS_A32; |
| 585 | break; |
| 586 | case VME_A64: |
| 587 | granularity = 0x10000; |
| 588 | addr |= TSI148_LCSR_ITAT_AS_A64; |
| 589 | break; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 590 | default: |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 591 | dev_err(tsi148_bridge->parent, "Invalid address space\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 592 | return -EINVAL; |
| 593 | break; |
| 594 | } |
| 595 | |
| 596 | /* Convert 64-bit variables to 2x 32-bit variables */ |
| 597 | reg_split(vme_base, &vme_base_high, &vme_base_low); |
| 598 | |
| 599 | /* |
| 600 | * Bound address is a valid address for the window, adjust |
| 601 | * accordingly |
| 602 | */ |
| 603 | vme_bound = vme_base + size - granularity; |
| 604 | reg_split(vme_bound, &vme_bound_high, &vme_bound_low); |
| 605 | pci_offset = (unsigned long long)pci_base - vme_base; |
| 606 | reg_split(pci_offset, &pci_offset_high, &pci_offset_low); |
| 607 | |
| 608 | if (vme_base_low & (granularity - 1)) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 609 | dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 610 | return -EINVAL; |
| 611 | } |
| 612 | if (vme_bound_low & (granularity - 1)) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 613 | dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 614 | return -EINVAL; |
| 615 | } |
| 616 | if (pci_offset_low & (granularity - 1)) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 617 | dev_err(tsi148_bridge->parent, "Invalid PCI Offset " |
| 618 | "alignment\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 619 | return -EINVAL; |
| 620 | } |
| 621 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 622 | /* Disable while we are mucking around */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 623 | temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 624 | TSI148_LCSR_OFFSET_ITAT); |
| 625 | temp_ctl &= ~TSI148_LCSR_ITAT_EN; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 626 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 627 | TSI148_LCSR_OFFSET_ITAT); |
| 628 | |
| 629 | /* Setup mapping */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 630 | iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 631 | TSI148_LCSR_OFFSET_ITSAU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 632 | iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 633 | TSI148_LCSR_OFFSET_ITSAL); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 634 | iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 635 | TSI148_LCSR_OFFSET_ITEAU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 636 | iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 637 | TSI148_LCSR_OFFSET_ITEAL); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 638 | iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 639 | TSI148_LCSR_OFFSET_ITOFU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 640 | iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 641 | TSI148_LCSR_OFFSET_ITOFL); |
| 642 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 643 | /* Setup 2eSST speeds */ |
| 644 | temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M; |
| 645 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { |
| 646 | case VME_2eSST160: |
| 647 | temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160; |
| 648 | break; |
| 649 | case VME_2eSST267: |
| 650 | temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267; |
| 651 | break; |
| 652 | case VME_2eSST320: |
| 653 | temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320; |
| 654 | break; |
| 655 | } |
| 656 | |
| 657 | /* Setup cycle types */ |
| 658 | temp_ctl &= ~(0x1F << 7); |
| 659 | if (cycle & VME_BLT) |
| 660 | temp_ctl |= TSI148_LCSR_ITAT_BLT; |
| 661 | if (cycle & VME_MBLT) |
| 662 | temp_ctl |= TSI148_LCSR_ITAT_MBLT; |
| 663 | if (cycle & VME_2eVME) |
| 664 | temp_ctl |= TSI148_LCSR_ITAT_2eVME; |
| 665 | if (cycle & VME_2eSST) |
| 666 | temp_ctl |= TSI148_LCSR_ITAT_2eSST; |
| 667 | if (cycle & VME_2eSSTB) |
| 668 | temp_ctl |= TSI148_LCSR_ITAT_2eSSTB; |
| 669 | |
| 670 | /* Setup address space */ |
| 671 | temp_ctl &= ~TSI148_LCSR_ITAT_AS_M; |
| 672 | temp_ctl |= addr; |
| 673 | |
| 674 | temp_ctl &= ~0xF; |
| 675 | if (cycle & VME_SUPER) |
| 676 | temp_ctl |= TSI148_LCSR_ITAT_SUPR ; |
| 677 | if (cycle & VME_USER) |
| 678 | temp_ctl |= TSI148_LCSR_ITAT_NPRIV; |
| 679 | if (cycle & VME_PROG) |
| 680 | temp_ctl |= TSI148_LCSR_ITAT_PGM; |
| 681 | if (cycle & VME_DATA) |
| 682 | temp_ctl |= TSI148_LCSR_ITAT_DATA; |
| 683 | |
| 684 | /* Write ctl reg without enable */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 685 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 686 | TSI148_LCSR_OFFSET_ITAT); |
| 687 | |
| 688 | if (enabled) |
| 689 | temp_ctl |= TSI148_LCSR_ITAT_EN; |
| 690 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 691 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 692 | TSI148_LCSR_OFFSET_ITAT); |
| 693 | |
| 694 | return 0; |
| 695 | } |
| 696 | |
| 697 | /* |
| 698 | * Get slave window configuration. |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 699 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 700 | static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled, |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 701 | unsigned long long *vme_base, unsigned long long *size, |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 702 | dma_addr_t *pci_base, u32 *aspace, u32 *cycle) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 703 | { |
| 704 | unsigned int i, granularity = 0, ctl = 0; |
| 705 | unsigned int vme_base_low, vme_base_high; |
| 706 | unsigned int vme_bound_low, vme_bound_high; |
| 707 | unsigned int pci_offset_low, pci_offset_high; |
| 708 | unsigned long long vme_bound, pci_offset; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 709 | struct tsi148_driver *bridge; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 710 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 711 | bridge = image->parent->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 712 | |
| 713 | i = image->number; |
| 714 | |
| 715 | /* Read registers */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 716 | ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 717 | TSI148_LCSR_OFFSET_ITAT); |
| 718 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 719 | vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 720 | TSI148_LCSR_OFFSET_ITSAU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 721 | vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 722 | TSI148_LCSR_OFFSET_ITSAL); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 723 | vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 724 | TSI148_LCSR_OFFSET_ITEAU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 725 | vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 726 | TSI148_LCSR_OFFSET_ITEAL); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 727 | pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 728 | TSI148_LCSR_OFFSET_ITOFU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 729 | pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 730 | TSI148_LCSR_OFFSET_ITOFL); |
| 731 | |
| 732 | /* Convert 64-bit variables to 2x 32-bit variables */ |
| 733 | reg_join(vme_base_high, vme_base_low, vme_base); |
| 734 | reg_join(vme_bound_high, vme_bound_low, &vme_bound); |
| 735 | reg_join(pci_offset_high, pci_offset_low, &pci_offset); |
| 736 | |
Joe Schultz | 098ced8 | 2014-04-03 14:47:55 -0500 | [diff] [blame] | 737 | *pci_base = (dma_addr_t)(*vme_base + pci_offset); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 738 | |
| 739 | *enabled = 0; |
| 740 | *aspace = 0; |
| 741 | *cycle = 0; |
| 742 | |
| 743 | if (ctl & TSI148_LCSR_ITAT_EN) |
| 744 | *enabled = 1; |
| 745 | |
| 746 | if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) { |
| 747 | granularity = 0x10; |
| 748 | *aspace |= VME_A16; |
| 749 | } |
| 750 | if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) { |
| 751 | granularity = 0x1000; |
| 752 | *aspace |= VME_A24; |
| 753 | } |
| 754 | if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) { |
| 755 | granularity = 0x10000; |
| 756 | *aspace |= VME_A32; |
| 757 | } |
| 758 | if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) { |
| 759 | granularity = 0x10000; |
| 760 | *aspace |= VME_A64; |
| 761 | } |
| 762 | |
| 763 | /* Need granularity before we set the size */ |
| 764 | *size = (unsigned long long)((vme_bound - *vme_base) + granularity); |
| 765 | |
| 766 | |
| 767 | if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160) |
| 768 | *cycle |= VME_2eSST160; |
| 769 | if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267) |
| 770 | *cycle |= VME_2eSST267; |
| 771 | if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320) |
| 772 | *cycle |= VME_2eSST320; |
| 773 | |
| 774 | if (ctl & TSI148_LCSR_ITAT_BLT) |
| 775 | *cycle |= VME_BLT; |
| 776 | if (ctl & TSI148_LCSR_ITAT_MBLT) |
| 777 | *cycle |= VME_MBLT; |
| 778 | if (ctl & TSI148_LCSR_ITAT_2eVME) |
| 779 | *cycle |= VME_2eVME; |
| 780 | if (ctl & TSI148_LCSR_ITAT_2eSST) |
| 781 | *cycle |= VME_2eSST; |
| 782 | if (ctl & TSI148_LCSR_ITAT_2eSSTB) |
| 783 | *cycle |= VME_2eSSTB; |
| 784 | |
| 785 | if (ctl & TSI148_LCSR_ITAT_SUPR) |
| 786 | *cycle |= VME_SUPER; |
| 787 | if (ctl & TSI148_LCSR_ITAT_NPRIV) |
| 788 | *cycle |= VME_USER; |
| 789 | if (ctl & TSI148_LCSR_ITAT_PGM) |
| 790 | *cycle |= VME_PROG; |
| 791 | if (ctl & TSI148_LCSR_ITAT_DATA) |
| 792 | *cycle |= VME_DATA; |
| 793 | |
| 794 | return 0; |
| 795 | } |
| 796 | |
| 797 | /* |
| 798 | * Allocate and map PCI Resource |
| 799 | */ |
| 800 | static int tsi148_alloc_resource(struct vme_master_resource *image, |
| 801 | unsigned long long size) |
| 802 | { |
| 803 | unsigned long long existing_size; |
| 804 | int retval = 0; |
| 805 | struct pci_dev *pdev; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 806 | struct vme_bridge *tsi148_bridge; |
| 807 | |
| 808 | tsi148_bridge = image->parent; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 809 | |
Aaron Sierra | 177581fa | 2014-04-03 14:48:27 -0500 | [diff] [blame] | 810 | pdev = to_pci_dev(tsi148_bridge->parent); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 811 | |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 812 | existing_size = (unsigned long long)(image->bus_resource.end - |
| 813 | image->bus_resource.start); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 814 | |
| 815 | /* If the existing size is OK, return */ |
Martyn Welch | 59c2290 | 2009-10-29 16:35:01 +0000 | [diff] [blame] | 816 | if ((size != 0) && (existing_size == (size - 1))) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 817 | return 0; |
| 818 | |
| 819 | if (existing_size != 0) { |
| 820 | iounmap(image->kern_base); |
| 821 | image->kern_base = NULL; |
Ilia Mirkin | 794a894 | 2011-03-13 00:29:13 -0500 | [diff] [blame] | 822 | kfree(image->bus_resource.name); |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 823 | release_resource(&image->bus_resource); |
| 824 | memset(&image->bus_resource, 0, sizeof(struct resource)); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 825 | } |
| 826 | |
Martyn Welch | 59c2290 | 2009-10-29 16:35:01 +0000 | [diff] [blame] | 827 | /* Exit here if size is zero */ |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 828 | if (size == 0) |
Martyn Welch | 59c2290 | 2009-10-29 16:35:01 +0000 | [diff] [blame] | 829 | return 0; |
Martyn Welch | 59c2290 | 2009-10-29 16:35:01 +0000 | [diff] [blame] | 830 | |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 831 | if (image->bus_resource.name == NULL) { |
Julia Lawall | 0aa3f13 | 2010-05-30 22:27:46 +0200 | [diff] [blame] | 832 | image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC); |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 833 | if (image->bus_resource.name == NULL) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 834 | dev_err(tsi148_bridge->parent, "Unable to allocate " |
| 835 | "memory for resource name\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 836 | retval = -ENOMEM; |
| 837 | goto err_name; |
| 838 | } |
| 839 | } |
| 840 | |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 841 | sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name, |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 842 | image->number); |
| 843 | |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 844 | image->bus_resource.start = 0; |
| 845 | image->bus_resource.end = (unsigned long)size; |
| 846 | image->bus_resource.flags = IORESOURCE_MEM; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 847 | |
| 848 | retval = pci_bus_alloc_resource(pdev->bus, |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 849 | &image->bus_resource, size, size, PCIBIOS_MIN_MEM, |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 850 | 0, NULL, NULL); |
| 851 | if (retval) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 852 | dev_err(tsi148_bridge->parent, "Failed to allocate mem " |
| 853 | "resource for window %d size 0x%lx start 0x%lx\n", |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 854 | image->number, (unsigned long)size, |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 855 | (unsigned long)image->bus_resource.start); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 856 | goto err_resource; |
| 857 | } |
| 858 | |
| 859 | image->kern_base = ioremap_nocache( |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 860 | image->bus_resource.start, size); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 861 | if (image->kern_base == NULL) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 862 | dev_err(tsi148_bridge->parent, "Failed to remap resource\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 863 | retval = -ENOMEM; |
| 864 | goto err_remap; |
| 865 | } |
| 866 | |
| 867 | return 0; |
| 868 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 869 | err_remap: |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 870 | release_resource(&image->bus_resource); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 871 | err_resource: |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 872 | kfree(image->bus_resource.name); |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 873 | memset(&image->bus_resource, 0, sizeof(struct resource)); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 874 | err_name: |
| 875 | return retval; |
| 876 | } |
| 877 | |
| 878 | /* |
| 879 | * Free and unmap PCI Resource |
| 880 | */ |
| 881 | static void tsi148_free_resource(struct vme_master_resource *image) |
| 882 | { |
| 883 | iounmap(image->kern_base); |
| 884 | image->kern_base = NULL; |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 885 | release_resource(&image->bus_resource); |
Martyn Welch | 8fafb47 | 2010-02-18 15:13:12 +0000 | [diff] [blame] | 886 | kfree(image->bus_resource.name); |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 887 | memset(&image->bus_resource, 0, sizeof(struct resource)); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 888 | } |
| 889 | |
| 890 | /* |
| 891 | * Set the attributes of an outbound window. |
| 892 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 893 | static int tsi148_master_set(struct vme_master_resource *image, int enabled, |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 894 | unsigned long long vme_base, unsigned long long size, u32 aspace, |
| 895 | u32 cycle, u32 dwidth) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 896 | { |
| 897 | int retval = 0; |
| 898 | unsigned int i; |
| 899 | unsigned int temp_ctl = 0; |
| 900 | unsigned int pci_base_low, pci_base_high; |
| 901 | unsigned int pci_bound_low, pci_bound_high; |
| 902 | unsigned int vme_offset_low, vme_offset_high; |
| 903 | unsigned long long pci_bound, vme_offset, pci_base; |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 904 | struct vme_bridge *tsi148_bridge; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 905 | struct tsi148_driver *bridge; |
Joe Schultz | 226572b | 2014-04-03 14:48:16 -0500 | [diff] [blame] | 906 | struct pci_bus_region region; |
| 907 | struct pci_dev *pdev; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 908 | |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 909 | tsi148_bridge = image->parent; |
| 910 | |
| 911 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 912 | |
Aaron Sierra | 177581fa | 2014-04-03 14:48:27 -0500 | [diff] [blame] | 913 | pdev = to_pci_dev(tsi148_bridge->parent); |
Joe Schultz | 226572b | 2014-04-03 14:48:16 -0500 | [diff] [blame] | 914 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 915 | /* Verify input data */ |
| 916 | if (vme_base & 0xFFFF) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 917 | dev_err(tsi148_bridge->parent, "Invalid VME Window " |
| 918 | "alignment\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 919 | retval = -EINVAL; |
| 920 | goto err_window; |
| 921 | } |
Martyn Welch | 59c2290 | 2009-10-29 16:35:01 +0000 | [diff] [blame] | 922 | |
| 923 | if ((size == 0) && (enabled != 0)) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 924 | dev_err(tsi148_bridge->parent, "Size must be non-zero for " |
| 925 | "enabled windows\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 926 | retval = -EINVAL; |
| 927 | goto err_window; |
| 928 | } |
| 929 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 930 | spin_lock(&image->lock); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 931 | |
| 932 | /* Let's allocate the resource here rather than further up the stack as |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 933 | * it avoids pushing loads of bus dependent stuff up the stack. If size |
Martyn Welch | 59c2290 | 2009-10-29 16:35:01 +0000 | [diff] [blame] | 934 | * is zero, any existing resource will be freed. |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 935 | */ |
| 936 | retval = tsi148_alloc_resource(image, size); |
| 937 | if (retval) { |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 938 | spin_unlock(&image->lock); |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 939 | dev_err(tsi148_bridge->parent, "Unable to allocate memory for " |
Martyn Welch | 59c2290 | 2009-10-29 16:35:01 +0000 | [diff] [blame] | 940 | "resource\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 941 | goto err_res; |
| 942 | } |
| 943 | |
Martyn Welch | 59c2290 | 2009-10-29 16:35:01 +0000 | [diff] [blame] | 944 | if (size == 0) { |
| 945 | pci_base = 0; |
| 946 | pci_bound = 0; |
| 947 | vme_offset = 0; |
| 948 | } else { |
Joe Schultz | 226572b | 2014-04-03 14:48:16 -0500 | [diff] [blame] | 949 | pcibios_resource_to_bus(pdev->bus, ®ion, |
| 950 | &image->bus_resource); |
| 951 | pci_base = region.start; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 952 | |
Martyn Welch | 59c2290 | 2009-10-29 16:35:01 +0000 | [diff] [blame] | 953 | /* |
| 954 | * Bound address is a valid address for the window, adjust |
| 955 | * according to window granularity. |
| 956 | */ |
| 957 | pci_bound = pci_base + (size - 0x10000); |
| 958 | vme_offset = vme_base - pci_base; |
| 959 | } |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 960 | |
| 961 | /* Convert 64-bit variables to 2x 32-bit variables */ |
| 962 | reg_split(pci_base, &pci_base_high, &pci_base_low); |
| 963 | reg_split(pci_bound, &pci_bound_high, &pci_bound_low); |
| 964 | reg_split(vme_offset, &vme_offset_high, &vme_offset_low); |
| 965 | |
| 966 | if (pci_base_low & 0xFFFF) { |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 967 | spin_unlock(&image->lock); |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 968 | dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 969 | retval = -EINVAL; |
| 970 | goto err_gran; |
| 971 | } |
| 972 | if (pci_bound_low & 0xFFFF) { |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 973 | spin_unlock(&image->lock); |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 974 | dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 975 | retval = -EINVAL; |
| 976 | goto err_gran; |
| 977 | } |
| 978 | if (vme_offset_low & 0xFFFF) { |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 979 | spin_unlock(&image->lock); |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 980 | dev_err(tsi148_bridge->parent, "Invalid VME Offset " |
| 981 | "alignment\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 982 | retval = -EINVAL; |
| 983 | goto err_gran; |
| 984 | } |
| 985 | |
| 986 | i = image->number; |
| 987 | |
| 988 | /* Disable while we are mucking around */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 989 | temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 990 | TSI148_LCSR_OFFSET_OTAT); |
| 991 | temp_ctl &= ~TSI148_LCSR_OTAT_EN; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 992 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 993 | TSI148_LCSR_OFFSET_OTAT); |
| 994 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 995 | /* Setup 2eSST speeds */ |
| 996 | temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M; |
| 997 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { |
| 998 | case VME_2eSST160: |
| 999 | temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160; |
| 1000 | break; |
| 1001 | case VME_2eSST267: |
| 1002 | temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267; |
| 1003 | break; |
| 1004 | case VME_2eSST320: |
| 1005 | temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320; |
| 1006 | break; |
| 1007 | } |
| 1008 | |
| 1009 | /* Setup cycle types */ |
| 1010 | if (cycle & VME_BLT) { |
| 1011 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; |
| 1012 | temp_ctl |= TSI148_LCSR_OTAT_TM_BLT; |
| 1013 | } |
| 1014 | if (cycle & VME_MBLT) { |
| 1015 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; |
| 1016 | temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT; |
| 1017 | } |
| 1018 | if (cycle & VME_2eVME) { |
| 1019 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; |
| 1020 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME; |
| 1021 | } |
| 1022 | if (cycle & VME_2eSST) { |
| 1023 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; |
| 1024 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST; |
| 1025 | } |
| 1026 | if (cycle & VME_2eSSTB) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1027 | dev_warn(tsi148_bridge->parent, "Currently not setting " |
| 1028 | "Broadcast Select Registers\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1029 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; |
| 1030 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB; |
| 1031 | } |
| 1032 | |
| 1033 | /* Setup data width */ |
| 1034 | temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M; |
| 1035 | switch (dwidth) { |
| 1036 | case VME_D16: |
| 1037 | temp_ctl |= TSI148_LCSR_OTAT_DBW_16; |
| 1038 | break; |
| 1039 | case VME_D32: |
| 1040 | temp_ctl |= TSI148_LCSR_OTAT_DBW_32; |
| 1041 | break; |
| 1042 | default: |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1043 | spin_unlock(&image->lock); |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1044 | dev_err(tsi148_bridge->parent, "Invalid data width\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1045 | retval = -EINVAL; |
| 1046 | goto err_dwidth; |
| 1047 | } |
| 1048 | |
| 1049 | /* Setup address space */ |
| 1050 | temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M; |
| 1051 | switch (aspace) { |
| 1052 | case VME_A16: |
| 1053 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16; |
| 1054 | break; |
| 1055 | case VME_A24: |
| 1056 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24; |
| 1057 | break; |
| 1058 | case VME_A32: |
| 1059 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32; |
| 1060 | break; |
| 1061 | case VME_A64: |
| 1062 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64; |
| 1063 | break; |
| 1064 | case VME_CRCSR: |
| 1065 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR; |
| 1066 | break; |
| 1067 | case VME_USER1: |
| 1068 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1; |
| 1069 | break; |
| 1070 | case VME_USER2: |
| 1071 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2; |
| 1072 | break; |
| 1073 | case VME_USER3: |
| 1074 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3; |
| 1075 | break; |
| 1076 | case VME_USER4: |
| 1077 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4; |
| 1078 | break; |
| 1079 | default: |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1080 | spin_unlock(&image->lock); |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1081 | dev_err(tsi148_bridge->parent, "Invalid address space\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1082 | retval = -EINVAL; |
| 1083 | goto err_aspace; |
| 1084 | break; |
| 1085 | } |
| 1086 | |
| 1087 | temp_ctl &= ~(3<<4); |
| 1088 | if (cycle & VME_SUPER) |
| 1089 | temp_ctl |= TSI148_LCSR_OTAT_SUP; |
| 1090 | if (cycle & VME_PROG) |
| 1091 | temp_ctl |= TSI148_LCSR_OTAT_PGM; |
| 1092 | |
| 1093 | /* Setup mapping */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1094 | iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1095 | TSI148_LCSR_OFFSET_OTSAU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1096 | iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1097 | TSI148_LCSR_OFFSET_OTSAL); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1098 | iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1099 | TSI148_LCSR_OFFSET_OTEAU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1100 | iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1101 | TSI148_LCSR_OFFSET_OTEAL); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1102 | iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1103 | TSI148_LCSR_OFFSET_OTOFU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1104 | iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1105 | TSI148_LCSR_OFFSET_OTOFL); |
| 1106 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1107 | /* Write ctl reg without enable */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1108 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1109 | TSI148_LCSR_OFFSET_OTAT); |
| 1110 | |
| 1111 | if (enabled) |
| 1112 | temp_ctl |= TSI148_LCSR_OTAT_EN; |
| 1113 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1114 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1115 | TSI148_LCSR_OFFSET_OTAT); |
| 1116 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1117 | spin_unlock(&image->lock); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1118 | return 0; |
| 1119 | |
| 1120 | err_aspace: |
| 1121 | err_dwidth: |
| 1122 | err_gran: |
| 1123 | tsi148_free_resource(image); |
| 1124 | err_res: |
| 1125 | err_window: |
| 1126 | return retval; |
| 1127 | |
| 1128 | } |
| 1129 | |
| 1130 | /* |
| 1131 | * Set the attributes of an outbound window. |
| 1132 | * |
| 1133 | * XXX Not parsing prefetch information. |
| 1134 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 1135 | static int __tsi148_master_get(struct vme_master_resource *image, int *enabled, |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 1136 | unsigned long long *vme_base, unsigned long long *size, u32 *aspace, |
| 1137 | u32 *cycle, u32 *dwidth) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1138 | { |
| 1139 | unsigned int i, ctl; |
| 1140 | unsigned int pci_base_low, pci_base_high; |
| 1141 | unsigned int pci_bound_low, pci_bound_high; |
| 1142 | unsigned int vme_offset_low, vme_offset_high; |
| 1143 | |
| 1144 | unsigned long long pci_base, pci_bound, vme_offset; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1145 | struct tsi148_driver *bridge; |
| 1146 | |
| 1147 | bridge = image->parent->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1148 | |
| 1149 | i = image->number; |
| 1150 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1151 | ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1152 | TSI148_LCSR_OFFSET_OTAT); |
| 1153 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1154 | pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1155 | TSI148_LCSR_OFFSET_OTSAU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1156 | pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1157 | TSI148_LCSR_OFFSET_OTSAL); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1158 | pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1159 | TSI148_LCSR_OFFSET_OTEAU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1160 | pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1161 | TSI148_LCSR_OFFSET_OTEAL); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1162 | vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1163 | TSI148_LCSR_OFFSET_OTOFU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1164 | vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1165 | TSI148_LCSR_OFFSET_OTOFL); |
| 1166 | |
| 1167 | /* Convert 64-bit variables to 2x 32-bit variables */ |
| 1168 | reg_join(pci_base_high, pci_base_low, &pci_base); |
| 1169 | reg_join(pci_bound_high, pci_bound_low, &pci_bound); |
| 1170 | reg_join(vme_offset_high, vme_offset_low, &vme_offset); |
| 1171 | |
| 1172 | *vme_base = pci_base + vme_offset; |
| 1173 | *size = (unsigned long long)(pci_bound - pci_base) + 0x10000; |
| 1174 | |
| 1175 | *enabled = 0; |
| 1176 | *aspace = 0; |
| 1177 | *cycle = 0; |
| 1178 | *dwidth = 0; |
| 1179 | |
| 1180 | if (ctl & TSI148_LCSR_OTAT_EN) |
| 1181 | *enabled = 1; |
| 1182 | |
| 1183 | /* Setup address space */ |
| 1184 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16) |
| 1185 | *aspace |= VME_A16; |
| 1186 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24) |
| 1187 | *aspace |= VME_A24; |
| 1188 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32) |
| 1189 | *aspace |= VME_A32; |
| 1190 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64) |
| 1191 | *aspace |= VME_A64; |
| 1192 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR) |
| 1193 | *aspace |= VME_CRCSR; |
| 1194 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1) |
| 1195 | *aspace |= VME_USER1; |
| 1196 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2) |
| 1197 | *aspace |= VME_USER2; |
| 1198 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3) |
| 1199 | *aspace |= VME_USER3; |
| 1200 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4) |
| 1201 | *aspace |= VME_USER4; |
| 1202 | |
| 1203 | /* Setup 2eSST speeds */ |
| 1204 | if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160) |
| 1205 | *cycle |= VME_2eSST160; |
| 1206 | if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267) |
| 1207 | *cycle |= VME_2eSST267; |
| 1208 | if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320) |
| 1209 | *cycle |= VME_2eSST320; |
| 1210 | |
| 1211 | /* Setup cycle types */ |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1212 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1213 | *cycle |= VME_SCT; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1214 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1215 | *cycle |= VME_BLT; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1216 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1217 | *cycle |= VME_MBLT; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1218 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1219 | *cycle |= VME_2eVME; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1220 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1221 | *cycle |= VME_2eSST; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1222 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1223 | *cycle |= VME_2eSSTB; |
| 1224 | |
| 1225 | if (ctl & TSI148_LCSR_OTAT_SUP) |
| 1226 | *cycle |= VME_SUPER; |
| 1227 | else |
| 1228 | *cycle |= VME_USER; |
| 1229 | |
| 1230 | if (ctl & TSI148_LCSR_OTAT_PGM) |
| 1231 | *cycle |= VME_PROG; |
| 1232 | else |
| 1233 | *cycle |= VME_DATA; |
| 1234 | |
| 1235 | /* Setup data width */ |
| 1236 | if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16) |
| 1237 | *dwidth = VME_D16; |
| 1238 | if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32) |
| 1239 | *dwidth = VME_D32; |
| 1240 | |
| 1241 | return 0; |
| 1242 | } |
| 1243 | |
| 1244 | |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 1245 | static int tsi148_master_get(struct vme_master_resource *image, int *enabled, |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 1246 | unsigned long long *vme_base, unsigned long long *size, u32 *aspace, |
| 1247 | u32 *cycle, u32 *dwidth) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1248 | { |
| 1249 | int retval; |
| 1250 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1251 | spin_lock(&image->lock); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1252 | |
| 1253 | retval = __tsi148_master_get(image, enabled, vme_base, size, aspace, |
| 1254 | cycle, dwidth); |
| 1255 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1256 | spin_unlock(&image->lock); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1257 | |
| 1258 | return retval; |
| 1259 | } |
| 1260 | |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 1261 | static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf, |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1262 | size_t count, loff_t offset) |
| 1263 | { |
| 1264 | int retval, enabled; |
| 1265 | unsigned long long vme_base, size; |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 1266 | u32 aspace, cycle, dwidth; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1267 | struct vme_bus_error *vme_err = NULL; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1268 | struct vme_bridge *tsi148_bridge; |
Jingoo Han | 4e8764d | 2013-08-19 16:40:15 +0900 | [diff] [blame] | 1269 | void __iomem *addr = image->kern_base + offset; |
Martyn Welch | 363e2e6 | 2012-07-19 17:48:46 +0100 | [diff] [blame] | 1270 | unsigned int done = 0; |
| 1271 | unsigned int count32; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1272 | |
| 1273 | tsi148_bridge = image->parent; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1274 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1275 | spin_lock(&image->lock); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1276 | |
Martyn Welch | 363e2e6 | 2012-07-19 17:48:46 +0100 | [diff] [blame] | 1277 | /* The following code handles VME address alignment. We cannot use |
Martyn Welch | a2a720e | 2014-02-06 13:35:36 +0000 | [diff] [blame] | 1278 | * memcpy_xxx here because it may cut data transfers in to 8-bit |
| 1279 | * cycles when D16 or D32 cycles are required on the VME bus. |
Martyn Welch | 363e2e6 | 2012-07-19 17:48:46 +0100 | [diff] [blame] | 1280 | * On the other hand, the bridge itself assures that the maximum data |
| 1281 | * cycle configured for the transfer is used and splits it |
| 1282 | * automatically for non-aligned addresses, so we don't want the |
| 1283 | * overhead of needlessly forcing small transfers for the entire cycle. |
| 1284 | */ |
| 1285 | if ((uintptr_t)addr & 0x1) { |
| 1286 | *(u8 *)buf = ioread8(addr); |
| 1287 | done += 1; |
| 1288 | if (done == count) |
| 1289 | goto out; |
| 1290 | } |
Martyn Welch | f0342e6 | 2014-02-07 15:48:56 +0000 | [diff] [blame] | 1291 | if ((uintptr_t)(addr + done) & 0x2) { |
Martyn Welch | 363e2e6 | 2012-07-19 17:48:46 +0100 | [diff] [blame] | 1292 | if ((count - done) < 2) { |
| 1293 | *(u8 *)(buf + done) = ioread8(addr + done); |
| 1294 | done += 1; |
| 1295 | goto out; |
| 1296 | } else { |
| 1297 | *(u16 *)(buf + done) = ioread16(addr + done); |
| 1298 | done += 2; |
| 1299 | } |
| 1300 | } |
| 1301 | |
| 1302 | count32 = (count - done) & ~0x3; |
Martyn Welch | a2a720e | 2014-02-06 13:35:36 +0000 | [diff] [blame] | 1303 | while (done < count32) { |
| 1304 | *(u32 *)(buf + done) = ioread32(addr + done); |
| 1305 | done += 4; |
Martyn Welch | 363e2e6 | 2012-07-19 17:48:46 +0100 | [diff] [blame] | 1306 | } |
| 1307 | |
| 1308 | if ((count - done) & 0x2) { |
| 1309 | *(u16 *)(buf + done) = ioread16(addr + done); |
| 1310 | done += 2; |
| 1311 | } |
| 1312 | if ((count - done) & 0x1) { |
| 1313 | *(u8 *)(buf + done) = ioread8(addr + done); |
| 1314 | done += 1; |
| 1315 | } |
| 1316 | |
| 1317 | out: |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1318 | retval = count; |
| 1319 | |
| 1320 | if (!err_chk) |
| 1321 | goto skip_chk; |
| 1322 | |
| 1323 | __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle, |
| 1324 | &dwidth); |
| 1325 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1326 | vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset, |
| 1327 | count); |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1328 | if (vme_err != NULL) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1329 | dev_err(image->parent->parent, "First VME read error detected " |
| 1330 | "an at address 0x%llx\n", vme_err->address); |
| 1331 | retval = vme_err->address - (vme_base + offset); |
| 1332 | /* Clear down save errors in this address range */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1333 | tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset, |
| 1334 | count); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1335 | } |
| 1336 | |
| 1337 | skip_chk: |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1338 | spin_unlock(&image->lock); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1339 | |
| 1340 | return retval; |
| 1341 | } |
| 1342 | |
| 1343 | |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 1344 | static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf, |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1345 | size_t count, loff_t offset) |
| 1346 | { |
| 1347 | int retval = 0, enabled; |
| 1348 | unsigned long long vme_base, size; |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 1349 | u32 aspace, cycle, dwidth; |
Jingoo Han | 4e8764d | 2013-08-19 16:40:15 +0900 | [diff] [blame] | 1350 | void __iomem *addr = image->kern_base + offset; |
Martyn Welch | 363e2e6 | 2012-07-19 17:48:46 +0100 | [diff] [blame] | 1351 | unsigned int done = 0; |
| 1352 | unsigned int count32; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1353 | |
| 1354 | struct vme_bus_error *vme_err = NULL; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1355 | struct vme_bridge *tsi148_bridge; |
| 1356 | struct tsi148_driver *bridge; |
| 1357 | |
| 1358 | tsi148_bridge = image->parent; |
| 1359 | |
| 1360 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1361 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1362 | spin_lock(&image->lock); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1363 | |
Martyn Welch | 363e2e6 | 2012-07-19 17:48:46 +0100 | [diff] [blame] | 1364 | /* Here we apply for the same strategy we do in master_read |
Martyn Welch | a2a720e | 2014-02-06 13:35:36 +0000 | [diff] [blame] | 1365 | * function in order to assure the correct cycles. |
Martyn Welch | 363e2e6 | 2012-07-19 17:48:46 +0100 | [diff] [blame] | 1366 | */ |
| 1367 | if ((uintptr_t)addr & 0x1) { |
| 1368 | iowrite8(*(u8 *)buf, addr); |
| 1369 | done += 1; |
| 1370 | if (done == count) |
| 1371 | goto out; |
| 1372 | } |
Martyn Welch | f0342e6 | 2014-02-07 15:48:56 +0000 | [diff] [blame] | 1373 | if ((uintptr_t)(addr + done) & 0x2) { |
Martyn Welch | 363e2e6 | 2012-07-19 17:48:46 +0100 | [diff] [blame] | 1374 | if ((count - done) < 2) { |
| 1375 | iowrite8(*(u8 *)(buf + done), addr + done); |
| 1376 | done += 1; |
| 1377 | goto out; |
| 1378 | } else { |
| 1379 | iowrite16(*(u16 *)(buf + done), addr + done); |
| 1380 | done += 2; |
| 1381 | } |
| 1382 | } |
| 1383 | |
| 1384 | count32 = (count - done) & ~0x3; |
Martyn Welch | a2a720e | 2014-02-06 13:35:36 +0000 | [diff] [blame] | 1385 | while (done < count32) { |
| 1386 | iowrite32(*(u32 *)(buf + done), addr + done); |
| 1387 | done += 4; |
Martyn Welch | 363e2e6 | 2012-07-19 17:48:46 +0100 | [diff] [blame] | 1388 | } |
| 1389 | |
| 1390 | if ((count - done) & 0x2) { |
| 1391 | iowrite16(*(u16 *)(buf + done), addr + done); |
| 1392 | done += 2; |
| 1393 | } |
| 1394 | if ((count - done) & 0x1) { |
| 1395 | iowrite8(*(u8 *)(buf + done), addr + done); |
| 1396 | done += 1; |
| 1397 | } |
| 1398 | |
| 1399 | out: |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1400 | retval = count; |
| 1401 | |
| 1402 | /* |
| 1403 | * Writes are posted. We need to do a read on the VME bus to flush out |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1404 | * all of the writes before we check for errors. We can't guarantee |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1405 | * that reading the data we have just written is safe. It is believed |
| 1406 | * that there isn't any read, write re-ordering, so we can read any |
| 1407 | * location in VME space, so lets read the Device ID from the tsi148's |
| 1408 | * own registers as mapped into CR/CSR space. |
| 1409 | * |
| 1410 | * We check for saved errors in the written address range/space. |
| 1411 | */ |
| 1412 | |
| 1413 | if (!err_chk) |
| 1414 | goto skip_chk; |
| 1415 | |
| 1416 | /* |
| 1417 | * Get window info first, to maximise the time that the buffers may |
| 1418 | * fluch on their own |
| 1419 | */ |
| 1420 | __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle, |
| 1421 | &dwidth); |
| 1422 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1423 | ioread16(bridge->flush_image->kern_base + 0x7F000); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1424 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1425 | vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset, |
| 1426 | count); |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1427 | if (vme_err != NULL) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1428 | dev_warn(tsi148_bridge->parent, "First VME write error detected" |
| 1429 | " an at address 0x%llx\n", vme_err->address); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1430 | retval = vme_err->address - (vme_base + offset); |
| 1431 | /* Clear down save errors in this address range */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1432 | tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset, |
| 1433 | count); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1434 | } |
| 1435 | |
| 1436 | skip_chk: |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1437 | spin_unlock(&image->lock); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1438 | |
| 1439 | return retval; |
| 1440 | } |
| 1441 | |
| 1442 | /* |
| 1443 | * Perform an RMW cycle on the VME bus. |
| 1444 | * |
| 1445 | * Requires a previously configured master window, returns final value. |
| 1446 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 1447 | static unsigned int tsi148_master_rmw(struct vme_master_resource *image, |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1448 | unsigned int mask, unsigned int compare, unsigned int swap, |
| 1449 | loff_t offset) |
| 1450 | { |
| 1451 | unsigned long long pci_addr; |
| 1452 | unsigned int pci_addr_high, pci_addr_low; |
| 1453 | u32 tmp, result; |
| 1454 | int i; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1455 | struct tsi148_driver *bridge; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1456 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1457 | bridge = image->parent->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1458 | |
| 1459 | /* Find the PCI address that maps to the desired VME address */ |
| 1460 | i = image->number; |
| 1461 | |
| 1462 | /* Locking as we can only do one of these at a time */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1463 | mutex_lock(&bridge->vme_rmw); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1464 | |
| 1465 | /* Lock image */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1466 | spin_lock(&image->lock); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1467 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1468 | pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1469 | TSI148_LCSR_OFFSET_OTSAU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1470 | pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1471 | TSI148_LCSR_OFFSET_OTSAL); |
| 1472 | |
| 1473 | reg_join(pci_addr_high, pci_addr_low, &pci_addr); |
| 1474 | reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low); |
| 1475 | |
| 1476 | /* Configure registers */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1477 | iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN); |
| 1478 | iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC); |
| 1479 | iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS); |
| 1480 | iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU); |
| 1481 | iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1482 | |
| 1483 | /* Enable RMW */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1484 | tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1485 | tmp |= TSI148_LCSR_VMCTRL_RMWEN; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1486 | iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1487 | |
| 1488 | /* Kick process off with a read to the required address. */ |
| 1489 | result = ioread32be(image->kern_base + offset); |
| 1490 | |
| 1491 | /* Disable RMW */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1492 | tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1493 | tmp &= ~TSI148_LCSR_VMCTRL_RMWEN; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1494 | iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1495 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1496 | spin_unlock(&image->lock); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1497 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1498 | mutex_unlock(&bridge->vme_rmw); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1499 | |
| 1500 | return result; |
| 1501 | } |
| 1502 | |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1503 | static int tsi148_dma_set_vme_src_attributes(struct device *dev, __be32 *attr, |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 1504 | u32 aspace, u32 cycle, u32 dwidth) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1505 | { |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1506 | u32 val; |
| 1507 | |
| 1508 | val = be32_to_cpu(*attr); |
| 1509 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1510 | /* Setup 2eSST speeds */ |
| 1511 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { |
| 1512 | case VME_2eSST160: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1513 | val |= TSI148_LCSR_DSAT_2eSSTM_160; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1514 | break; |
| 1515 | case VME_2eSST267: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1516 | val |= TSI148_LCSR_DSAT_2eSSTM_267; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1517 | break; |
| 1518 | case VME_2eSST320: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1519 | val |= TSI148_LCSR_DSAT_2eSSTM_320; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1520 | break; |
| 1521 | } |
| 1522 | |
| 1523 | /* Setup cycle types */ |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1524 | if (cycle & VME_SCT) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1525 | val |= TSI148_LCSR_DSAT_TM_SCT; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1526 | |
| 1527 | if (cycle & VME_BLT) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1528 | val |= TSI148_LCSR_DSAT_TM_BLT; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1529 | |
| 1530 | if (cycle & VME_MBLT) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1531 | val |= TSI148_LCSR_DSAT_TM_MBLT; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1532 | |
| 1533 | if (cycle & VME_2eVME) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1534 | val |= TSI148_LCSR_DSAT_TM_2eVME; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1535 | |
| 1536 | if (cycle & VME_2eSST) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1537 | val |= TSI148_LCSR_DSAT_TM_2eSST; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1538 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1539 | if (cycle & VME_2eSSTB) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1540 | dev_err(dev, "Currently not setting Broadcast Select " |
| 1541 | "Registers\n"); |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1542 | val |= TSI148_LCSR_DSAT_TM_2eSSTB; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1543 | } |
| 1544 | |
| 1545 | /* Setup data width */ |
| 1546 | switch (dwidth) { |
| 1547 | case VME_D16: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1548 | val |= TSI148_LCSR_DSAT_DBW_16; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1549 | break; |
| 1550 | case VME_D32: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1551 | val |= TSI148_LCSR_DSAT_DBW_32; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1552 | break; |
| 1553 | default: |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1554 | dev_err(dev, "Invalid data width\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1555 | return -EINVAL; |
| 1556 | } |
| 1557 | |
| 1558 | /* Setup address space */ |
| 1559 | switch (aspace) { |
| 1560 | case VME_A16: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1561 | val |= TSI148_LCSR_DSAT_AMODE_A16; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1562 | break; |
| 1563 | case VME_A24: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1564 | val |= TSI148_LCSR_DSAT_AMODE_A24; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1565 | break; |
| 1566 | case VME_A32: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1567 | val |= TSI148_LCSR_DSAT_AMODE_A32; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1568 | break; |
| 1569 | case VME_A64: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1570 | val |= TSI148_LCSR_DSAT_AMODE_A64; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1571 | break; |
| 1572 | case VME_CRCSR: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1573 | val |= TSI148_LCSR_DSAT_AMODE_CRCSR; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1574 | break; |
| 1575 | case VME_USER1: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1576 | val |= TSI148_LCSR_DSAT_AMODE_USER1; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1577 | break; |
| 1578 | case VME_USER2: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1579 | val |= TSI148_LCSR_DSAT_AMODE_USER2; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1580 | break; |
| 1581 | case VME_USER3: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1582 | val |= TSI148_LCSR_DSAT_AMODE_USER3; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1583 | break; |
| 1584 | case VME_USER4: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1585 | val |= TSI148_LCSR_DSAT_AMODE_USER4; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1586 | break; |
| 1587 | default: |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1588 | dev_err(dev, "Invalid address space\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1589 | return -EINVAL; |
| 1590 | break; |
| 1591 | } |
| 1592 | |
| 1593 | if (cycle & VME_SUPER) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1594 | val |= TSI148_LCSR_DSAT_SUP; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1595 | if (cycle & VME_PROG) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1596 | val |= TSI148_LCSR_DSAT_PGM; |
| 1597 | |
| 1598 | *attr = cpu_to_be32(val); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1599 | |
| 1600 | return 0; |
| 1601 | } |
| 1602 | |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1603 | static int tsi148_dma_set_vme_dest_attributes(struct device *dev, __be32 *attr, |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 1604 | u32 aspace, u32 cycle, u32 dwidth) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1605 | { |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1606 | u32 val; |
| 1607 | |
| 1608 | val = be32_to_cpu(*attr); |
| 1609 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1610 | /* Setup 2eSST speeds */ |
| 1611 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { |
| 1612 | case VME_2eSST160: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1613 | val |= TSI148_LCSR_DDAT_2eSSTM_160; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1614 | break; |
| 1615 | case VME_2eSST267: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1616 | val |= TSI148_LCSR_DDAT_2eSSTM_267; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1617 | break; |
| 1618 | case VME_2eSST320: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1619 | val |= TSI148_LCSR_DDAT_2eSSTM_320; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1620 | break; |
| 1621 | } |
| 1622 | |
| 1623 | /* Setup cycle types */ |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1624 | if (cycle & VME_SCT) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1625 | val |= TSI148_LCSR_DDAT_TM_SCT; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1626 | |
| 1627 | if (cycle & VME_BLT) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1628 | val |= TSI148_LCSR_DDAT_TM_BLT; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1629 | |
| 1630 | if (cycle & VME_MBLT) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1631 | val |= TSI148_LCSR_DDAT_TM_MBLT; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1632 | |
| 1633 | if (cycle & VME_2eVME) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1634 | val |= TSI148_LCSR_DDAT_TM_2eVME; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1635 | |
| 1636 | if (cycle & VME_2eSST) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1637 | val |= TSI148_LCSR_DDAT_TM_2eSST; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1638 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1639 | if (cycle & VME_2eSSTB) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1640 | dev_err(dev, "Currently not setting Broadcast Select " |
| 1641 | "Registers\n"); |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1642 | val |= TSI148_LCSR_DDAT_TM_2eSSTB; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1643 | } |
| 1644 | |
| 1645 | /* Setup data width */ |
| 1646 | switch (dwidth) { |
| 1647 | case VME_D16: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1648 | val |= TSI148_LCSR_DDAT_DBW_16; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1649 | break; |
| 1650 | case VME_D32: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1651 | val |= TSI148_LCSR_DDAT_DBW_32; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1652 | break; |
| 1653 | default: |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1654 | dev_err(dev, "Invalid data width\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1655 | return -EINVAL; |
| 1656 | } |
| 1657 | |
| 1658 | /* Setup address space */ |
| 1659 | switch (aspace) { |
| 1660 | case VME_A16: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1661 | val |= TSI148_LCSR_DDAT_AMODE_A16; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1662 | break; |
| 1663 | case VME_A24: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1664 | val |= TSI148_LCSR_DDAT_AMODE_A24; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1665 | break; |
| 1666 | case VME_A32: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1667 | val |= TSI148_LCSR_DDAT_AMODE_A32; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1668 | break; |
| 1669 | case VME_A64: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1670 | val |= TSI148_LCSR_DDAT_AMODE_A64; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1671 | break; |
| 1672 | case VME_CRCSR: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1673 | val |= TSI148_LCSR_DDAT_AMODE_CRCSR; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1674 | break; |
| 1675 | case VME_USER1: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1676 | val |= TSI148_LCSR_DDAT_AMODE_USER1; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1677 | break; |
| 1678 | case VME_USER2: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1679 | val |= TSI148_LCSR_DDAT_AMODE_USER2; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1680 | break; |
| 1681 | case VME_USER3: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1682 | val |= TSI148_LCSR_DDAT_AMODE_USER3; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1683 | break; |
| 1684 | case VME_USER4: |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1685 | val |= TSI148_LCSR_DDAT_AMODE_USER4; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1686 | break; |
| 1687 | default: |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1688 | dev_err(dev, "Invalid address space\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1689 | return -EINVAL; |
| 1690 | break; |
| 1691 | } |
| 1692 | |
| 1693 | if (cycle & VME_SUPER) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1694 | val |= TSI148_LCSR_DDAT_SUP; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1695 | if (cycle & VME_PROG) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1696 | val |= TSI148_LCSR_DDAT_PGM; |
| 1697 | |
| 1698 | *attr = cpu_to_be32(val); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1699 | |
| 1700 | return 0; |
| 1701 | } |
| 1702 | |
| 1703 | /* |
| 1704 | * Add a link list descriptor to the list |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1705 | * |
| 1706 | * Note: DMA engine expects the DMA descriptor to be big endian. |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1707 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 1708 | static int tsi148_dma_list_add(struct vme_dma_list *list, |
| 1709 | struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1710 | { |
| 1711 | struct tsi148_dma_entry *entry, *prev; |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1712 | u32 address_high, address_low, val; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1713 | struct vme_dma_pattern *pattern_attr; |
| 1714 | struct vme_dma_pci *pci_attr; |
| 1715 | struct vme_dma_vme *vme_attr; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1716 | int retval = 0; |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1717 | struct vme_bridge *tsi148_bridge; |
| 1718 | |
| 1719 | tsi148_bridge = list->parent->parent; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1720 | |
Martyn Welch | bb9ea89 | 2010-02-18 16:22:13 +0000 | [diff] [blame] | 1721 | /* Descriptor must be aligned on 64-bit boundaries */ |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1722 | entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1723 | if (entry == NULL) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1724 | dev_err(tsi148_bridge->parent, "Failed to allocate memory for " |
| 1725 | "dma resource structure\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1726 | retval = -ENOMEM; |
| 1727 | goto err_mem; |
| 1728 | } |
| 1729 | |
| 1730 | /* Test descriptor alignment */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1731 | if ((unsigned long)&entry->descriptor & 0x7) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1732 | dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 " |
| 1733 | "byte boundary as required: %p\n", |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1734 | &entry->descriptor); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1735 | retval = -EINVAL; |
| 1736 | goto err_align; |
| 1737 | } |
| 1738 | |
| 1739 | /* Given we are going to fill out the structure, we probably don't |
| 1740 | * need to zero it, but better safe than sorry for now. |
| 1741 | */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1742 | memset(&entry->descriptor, 0, sizeof(struct tsi148_dma_descriptor)); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1743 | |
| 1744 | /* Fill out source part */ |
| 1745 | switch (src->type) { |
| 1746 | case VME_DMA_PATTERN: |
Kulikov Vasiliy | c4d82fb | 2010-06-29 14:16:20 +0400 | [diff] [blame] | 1747 | pattern_attr = src->private; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1748 | |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1749 | entry->descriptor.dsal = cpu_to_be32(pattern_attr->pattern); |
| 1750 | |
| 1751 | val = TSI148_LCSR_DSAT_TYP_PAT; |
| 1752 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1753 | /* Default behaviour is 32 bit pattern */ |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1754 | if (pattern_attr->type & VME_DMA_PATTERN_BYTE) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1755 | val |= TSI148_LCSR_DSAT_PSZ; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1756 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1757 | /* It seems that the default behaviour is to increment */ |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1758 | if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0) |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1759 | val |= TSI148_LCSR_DSAT_NIN; |
| 1760 | entry->descriptor.dsat = cpu_to_be32(val); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1761 | break; |
| 1762 | case VME_DMA_PCI: |
Kulikov Vasiliy | c4d82fb | 2010-06-29 14:16:20 +0400 | [diff] [blame] | 1763 | pci_attr = src->private; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1764 | |
| 1765 | reg_split((unsigned long long)pci_attr->address, &address_high, |
| 1766 | &address_low); |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1767 | entry->descriptor.dsau = cpu_to_be32(address_high); |
| 1768 | entry->descriptor.dsal = cpu_to_be32(address_low); |
| 1769 | entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_PCI); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1770 | break; |
| 1771 | case VME_DMA_VME: |
Kulikov Vasiliy | c4d82fb | 2010-06-29 14:16:20 +0400 | [diff] [blame] | 1772 | vme_attr = src->private; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1773 | |
| 1774 | reg_split((unsigned long long)vme_attr->address, &address_high, |
| 1775 | &address_low); |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1776 | entry->descriptor.dsau = cpu_to_be32(address_high); |
| 1777 | entry->descriptor.dsal = cpu_to_be32(address_low); |
| 1778 | entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_VME); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1779 | |
| 1780 | retval = tsi148_dma_set_vme_src_attributes( |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1781 | tsi148_bridge->parent, &entry->descriptor.dsat, |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1782 | vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1783 | if (retval < 0) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1784 | goto err_source; |
| 1785 | break; |
| 1786 | default: |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1787 | dev_err(tsi148_bridge->parent, "Invalid source type\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1788 | retval = -EINVAL; |
| 1789 | goto err_source; |
| 1790 | break; |
| 1791 | } |
| 1792 | |
| 1793 | /* Assume last link - this will be over-written by adding another */ |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1794 | entry->descriptor.dnlau = cpu_to_be32(0); |
| 1795 | entry->descriptor.dnlal = cpu_to_be32(TSI148_LCSR_DNLAL_LLA); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1796 | |
| 1797 | /* Fill out destination part */ |
| 1798 | switch (dest->type) { |
| 1799 | case VME_DMA_PCI: |
Kulikov Vasiliy | c4d82fb | 2010-06-29 14:16:20 +0400 | [diff] [blame] | 1800 | pci_attr = dest->private; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1801 | |
| 1802 | reg_split((unsigned long long)pci_attr->address, &address_high, |
| 1803 | &address_low); |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1804 | entry->descriptor.ddau = cpu_to_be32(address_high); |
| 1805 | entry->descriptor.ddal = cpu_to_be32(address_low); |
| 1806 | entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_PCI); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1807 | break; |
| 1808 | case VME_DMA_VME: |
Kulikov Vasiliy | c4d82fb | 2010-06-29 14:16:20 +0400 | [diff] [blame] | 1809 | vme_attr = dest->private; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1810 | |
| 1811 | reg_split((unsigned long long)vme_attr->address, &address_high, |
| 1812 | &address_low); |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1813 | entry->descriptor.ddau = cpu_to_be32(address_high); |
| 1814 | entry->descriptor.ddal = cpu_to_be32(address_low); |
| 1815 | entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_VME); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1816 | |
| 1817 | retval = tsi148_dma_set_vme_dest_attributes( |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1818 | tsi148_bridge->parent, &entry->descriptor.ddat, |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1819 | vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1820 | if (retval < 0) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1821 | goto err_dest; |
| 1822 | break; |
| 1823 | default: |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1824 | dev_err(tsi148_bridge->parent, "Invalid destination type\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1825 | retval = -EINVAL; |
| 1826 | goto err_dest; |
| 1827 | break; |
| 1828 | } |
| 1829 | |
| 1830 | /* Fill out count */ |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1831 | entry->descriptor.dcnt = cpu_to_be32((u32)count); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1832 | |
| 1833 | /* Add to list */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1834 | list_add_tail(&entry->list, &list->entries); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1835 | |
| 1836 | /* Fill out previous descriptors "Next Address" */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1837 | if (entry->list.prev != &list->entries) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1838 | prev = list_entry(entry->list.prev, struct tsi148_dma_entry, |
| 1839 | list); |
| 1840 | /* We need the bus address for the pointer */ |
Martyn Welch | 3abc48a | 2012-03-22 13:27:29 +0000 | [diff] [blame] | 1841 | entry->dma_handle = dma_map_single(tsi148_bridge->parent, |
| 1842 | &entry->descriptor, |
| 1843 | sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE); |
| 1844 | |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1845 | reg_split((unsigned long long)entry->dma_handle, &address_high, |
| 1846 | &address_low); |
| 1847 | entry->descriptor.dnlau = cpu_to_be32(address_high); |
| 1848 | entry->descriptor.dnlal = cpu_to_be32(address_low); |
| 1849 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1850 | } |
| 1851 | |
| 1852 | return 0; |
| 1853 | |
| 1854 | err_dest: |
| 1855 | err_source: |
| 1856 | err_align: |
| 1857 | kfree(entry); |
| 1858 | err_mem: |
| 1859 | return retval; |
| 1860 | } |
| 1861 | |
| 1862 | /* |
| 1863 | * Check to see if the provided DMA channel is busy. |
| 1864 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1865 | static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1866 | { |
| 1867 | u32 tmp; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1868 | struct tsi148_driver *bridge; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1869 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1870 | bridge = tsi148_bridge->driver_priv; |
| 1871 | |
| 1872 | tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1873 | TSI148_LCSR_OFFSET_DSTA); |
| 1874 | |
| 1875 | if (tmp & TSI148_LCSR_DSTA_BSY) |
| 1876 | return 0; |
| 1877 | else |
| 1878 | return 1; |
| 1879 | |
| 1880 | } |
| 1881 | |
| 1882 | /* |
| 1883 | * Execute a previously generated link list |
| 1884 | * |
| 1885 | * XXX Need to provide control register configuration. |
| 1886 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 1887 | static int tsi148_dma_list_exec(struct vme_dma_list *list) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1888 | { |
| 1889 | struct vme_dma_resource *ctrlr; |
| 1890 | int channel, retval = 0; |
| 1891 | struct tsi148_dma_entry *entry; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1892 | u32 bus_addr_high, bus_addr_low; |
| 1893 | u32 val, dctlreg = 0; |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1894 | struct vme_bridge *tsi148_bridge; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1895 | struct tsi148_driver *bridge; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1896 | |
| 1897 | ctrlr = list->parent; |
| 1898 | |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1899 | tsi148_bridge = ctrlr->parent; |
| 1900 | |
| 1901 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1902 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1903 | mutex_lock(&ctrlr->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1904 | |
| 1905 | channel = ctrlr->number; |
| 1906 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1907 | if (!list_empty(&ctrlr->running)) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1908 | /* |
| 1909 | * XXX We have an active DMA transfer and currently haven't |
| 1910 | * sorted out the mechanism for "pending" DMA transfers. |
| 1911 | * Return busy. |
| 1912 | */ |
| 1913 | /* Need to add to pending here */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1914 | mutex_unlock(&ctrlr->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1915 | return -EBUSY; |
| 1916 | } else { |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1917 | list_add(&list->list, &ctrlr->running); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1918 | } |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1919 | |
| 1920 | /* Get first bus address and write into registers */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1921 | entry = list_first_entry(&list->entries, struct tsi148_dma_entry, |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1922 | list); |
| 1923 | |
Martyn Welch | 3abc48a | 2012-03-22 13:27:29 +0000 | [diff] [blame] | 1924 | entry->dma_handle = dma_map_single(tsi148_bridge->parent, |
| 1925 | &entry->descriptor, |
| 1926 | sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1927 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1928 | mutex_unlock(&ctrlr->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1929 | |
Martyn Welch | 3abc48a | 2012-03-22 13:27:29 +0000 | [diff] [blame] | 1930 | reg_split(entry->dma_handle, &bus_addr_high, &bus_addr_low); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1931 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1932 | iowrite32be(bus_addr_high, bridge->base + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1933 | TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1934 | iowrite32be(bus_addr_low, bridge->base + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1935 | TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL); |
| 1936 | |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1937 | dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + |
| 1938 | TSI148_LCSR_OFFSET_DCTL); |
| 1939 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1940 | /* Start the operation */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1941 | iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1942 | TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL); |
| 1943 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1944 | wait_event_interruptible(bridge->dma_queue[channel], |
| 1945 | tsi148_dma_busy(ctrlr->parent, channel)); |
Martyn Welch | ac1a4f2 | 2012-03-22 13:27:30 +0000 | [diff] [blame] | 1946 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1947 | /* |
| 1948 | * Read status register, this register is valid until we kick off a |
| 1949 | * new transfer. |
| 1950 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 1951 | val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1952 | TSI148_LCSR_OFFSET_DSTA); |
| 1953 | |
| 1954 | if (val & TSI148_LCSR_DSTA_VBE) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 1955 | dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1956 | retval = -EIO; |
| 1957 | } |
| 1958 | |
| 1959 | /* Remove list from running list */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1960 | mutex_lock(&ctrlr->mtx); |
| 1961 | list_del(&list->list); |
| 1962 | mutex_unlock(&ctrlr->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1963 | |
| 1964 | return retval; |
| 1965 | } |
| 1966 | |
| 1967 | /* |
| 1968 | * Clean up a previously generated link list |
| 1969 | * |
| 1970 | * We have a separate function, don't assume that the chain can't be reused. |
| 1971 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 1972 | static int tsi148_dma_list_empty(struct vme_dma_list *list) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1973 | { |
| 1974 | struct list_head *pos, *temp; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1975 | struct tsi148_dma_entry *entry; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1976 | |
Martyn Welch | 3abc48a | 2012-03-22 13:27:29 +0000 | [diff] [blame] | 1977 | struct vme_bridge *tsi148_bridge = list->parent->parent; |
| 1978 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1979 | /* detach and free each entry */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 1980 | list_for_each_safe(pos, temp, &list->entries) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1981 | list_del(pos); |
| 1982 | entry = list_entry(pos, struct tsi148_dma_entry, list); |
Martyn Welch | 3abc48a | 2012-03-22 13:27:29 +0000 | [diff] [blame] | 1983 | |
| 1984 | dma_unmap_single(tsi148_bridge->parent, entry->dma_handle, |
| 1985 | sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1986 | kfree(entry); |
| 1987 | } |
| 1988 | |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 1989 | return 0; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 1990 | } |
| 1991 | |
| 1992 | /* |
| 1993 | * All 4 location monitors reside at the same base - this is therefore a |
| 1994 | * system wide configuration. |
| 1995 | * |
| 1996 | * This does not enable the LM monitor - that should be done when the first |
| 1997 | * callback is attached and disabled when the last callback is removed. |
| 1998 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 1999 | static int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 2000 | u32 aspace, u32 cycle) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2001 | { |
| 2002 | u32 lm_base_high, lm_base_low, lm_ctl = 0; |
| 2003 | int i; |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2004 | struct vme_bridge *tsi148_bridge; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2005 | struct tsi148_driver *bridge; |
| 2006 | |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2007 | tsi148_bridge = lm->parent; |
| 2008 | |
| 2009 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2010 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2011 | mutex_lock(&lm->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2012 | |
| 2013 | /* If we already have a callback attached, we can't move it! */ |
Martyn Welch | 42fb503 | 2009-08-11 17:44:56 +0100 | [diff] [blame] | 2014 | for (i = 0; i < lm->monitors; i++) { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2015 | if (bridge->lm_callback[i] != NULL) { |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2016 | mutex_unlock(&lm->mtx); |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2017 | dev_err(tsi148_bridge->parent, "Location monitor " |
| 2018 | "callback attached, can't reset\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2019 | return -EBUSY; |
| 2020 | } |
| 2021 | } |
| 2022 | |
| 2023 | switch (aspace) { |
| 2024 | case VME_A16: |
| 2025 | lm_ctl |= TSI148_LCSR_LMAT_AS_A16; |
| 2026 | break; |
| 2027 | case VME_A24: |
| 2028 | lm_ctl |= TSI148_LCSR_LMAT_AS_A24; |
| 2029 | break; |
| 2030 | case VME_A32: |
| 2031 | lm_ctl |= TSI148_LCSR_LMAT_AS_A32; |
| 2032 | break; |
| 2033 | case VME_A64: |
| 2034 | lm_ctl |= TSI148_LCSR_LMAT_AS_A64; |
| 2035 | break; |
| 2036 | default: |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2037 | mutex_unlock(&lm->mtx); |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2038 | dev_err(tsi148_bridge->parent, "Invalid address space\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2039 | return -EINVAL; |
| 2040 | break; |
| 2041 | } |
| 2042 | |
| 2043 | if (cycle & VME_SUPER) |
| 2044 | lm_ctl |= TSI148_LCSR_LMAT_SUPR ; |
| 2045 | if (cycle & VME_USER) |
| 2046 | lm_ctl |= TSI148_LCSR_LMAT_NPRIV; |
| 2047 | if (cycle & VME_PROG) |
| 2048 | lm_ctl |= TSI148_LCSR_LMAT_PGM; |
| 2049 | if (cycle & VME_DATA) |
| 2050 | lm_ctl |= TSI148_LCSR_LMAT_DATA; |
| 2051 | |
| 2052 | reg_split(lm_base, &lm_base_high, &lm_base_low); |
| 2053 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2054 | iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU); |
| 2055 | iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL); |
| 2056 | iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2057 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2058 | mutex_unlock(&lm->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2059 | |
| 2060 | return 0; |
| 2061 | } |
| 2062 | |
| 2063 | /* Get configuration of the callback monitor and return whether it is enabled |
| 2064 | * or disabled. |
| 2065 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 2066 | static int tsi148_lm_get(struct vme_lm_resource *lm, |
Martyn Welch | 6af04b0 | 2011-12-01 17:06:29 +0000 | [diff] [blame] | 2067 | unsigned long long *lm_base, u32 *aspace, u32 *cycle) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2068 | { |
| 2069 | u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2070 | struct tsi148_driver *bridge; |
| 2071 | |
| 2072 | bridge = lm->parent->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2073 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2074 | mutex_lock(&lm->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2075 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2076 | lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU); |
| 2077 | lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL); |
| 2078 | lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2079 | |
| 2080 | reg_join(lm_base_high, lm_base_low, lm_base); |
| 2081 | |
| 2082 | if (lm_ctl & TSI148_LCSR_LMAT_EN) |
| 2083 | enabled = 1; |
| 2084 | |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2085 | if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2086 | *aspace |= VME_A16; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2087 | |
| 2088 | if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2089 | *aspace |= VME_A24; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2090 | |
| 2091 | if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2092 | *aspace |= VME_A32; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2093 | |
| 2094 | if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2095 | *aspace |= VME_A64; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2096 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2097 | |
| 2098 | if (lm_ctl & TSI148_LCSR_LMAT_SUPR) |
| 2099 | *cycle |= VME_SUPER; |
| 2100 | if (lm_ctl & TSI148_LCSR_LMAT_NPRIV) |
| 2101 | *cycle |= VME_USER; |
| 2102 | if (lm_ctl & TSI148_LCSR_LMAT_PGM) |
| 2103 | *cycle |= VME_PROG; |
| 2104 | if (lm_ctl & TSI148_LCSR_LMAT_DATA) |
| 2105 | *cycle |= VME_DATA; |
| 2106 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2107 | mutex_unlock(&lm->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2108 | |
| 2109 | return enabled; |
| 2110 | } |
| 2111 | |
| 2112 | /* |
| 2113 | * Attach a callback to a specific location monitor. |
| 2114 | * |
| 2115 | * Callback will be passed the monitor triggered. |
| 2116 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 2117 | static int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor, |
Martyn Welch | 42fb503 | 2009-08-11 17:44:56 +0100 | [diff] [blame] | 2118 | void (*callback)(int)) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2119 | { |
| 2120 | u32 lm_ctl, tmp; |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2121 | struct vme_bridge *tsi148_bridge; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2122 | struct tsi148_driver *bridge; |
| 2123 | |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2124 | tsi148_bridge = lm->parent; |
| 2125 | |
| 2126 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2127 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2128 | mutex_lock(&lm->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2129 | |
| 2130 | /* Ensure that the location monitor is configured - need PGM or DATA */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2131 | lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2132 | if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) { |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2133 | mutex_unlock(&lm->mtx); |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2134 | dev_err(tsi148_bridge->parent, "Location monitor not properly " |
| 2135 | "configured\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2136 | return -EINVAL; |
| 2137 | } |
| 2138 | |
| 2139 | /* Check that a callback isn't already attached */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2140 | if (bridge->lm_callback[monitor] != NULL) { |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2141 | mutex_unlock(&lm->mtx); |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2142 | dev_err(tsi148_bridge->parent, "Existing callback attached\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2143 | return -EBUSY; |
| 2144 | } |
| 2145 | |
| 2146 | /* Attach callback */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2147 | bridge->lm_callback[monitor] = callback; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2148 | |
| 2149 | /* Enable Location Monitor interrupt */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2150 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2151 | tmp |= TSI148_LCSR_INTEN_LMEN[monitor]; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2152 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2153 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2154 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2155 | tmp |= TSI148_LCSR_INTEO_LMEO[monitor]; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2156 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2157 | |
| 2158 | /* Ensure that global Location Monitor Enable set */ |
| 2159 | if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) { |
| 2160 | lm_ctl |= TSI148_LCSR_LMAT_EN; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2161 | iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2162 | } |
| 2163 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2164 | mutex_unlock(&lm->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2165 | |
| 2166 | return 0; |
| 2167 | } |
| 2168 | |
| 2169 | /* |
| 2170 | * Detach a callback function forn a specific location monitor. |
| 2171 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 2172 | static int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2173 | { |
| 2174 | u32 lm_en, tmp; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2175 | struct tsi148_driver *bridge; |
| 2176 | |
| 2177 | bridge = lm->parent->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2178 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2179 | mutex_lock(&lm->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2180 | |
| 2181 | /* Disable Location Monitor and ensure previous interrupts are clear */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2182 | lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2183 | lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor]; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2184 | iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2185 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2186 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2187 | tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor]; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2188 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2189 | |
| 2190 | iowrite32be(TSI148_LCSR_INTC_LMC[monitor], |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2191 | bridge->base + TSI148_LCSR_INTC); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2192 | |
| 2193 | /* Detach callback */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2194 | bridge->lm_callback[monitor] = NULL; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2195 | |
| 2196 | /* If all location monitors disabled, disable global Location Monitor */ |
| 2197 | if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S | |
| 2198 | TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2199 | tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2200 | tmp &= ~TSI148_LCSR_LMAT_EN; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2201 | iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2202 | } |
| 2203 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2204 | mutex_unlock(&lm->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2205 | |
| 2206 | return 0; |
| 2207 | } |
| 2208 | |
| 2209 | /* |
| 2210 | * Determine Geographical Addressing |
| 2211 | */ |
Emilio G. Cota | 5ade6c4 | 2010-11-12 11:15:00 +0000 | [diff] [blame] | 2212 | static int tsi148_slot_get(struct vme_bridge *tsi148_bridge) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2213 | { |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2214 | u32 slot = 0; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2215 | struct tsi148_driver *bridge; |
| 2216 | |
| 2217 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2218 | |
Martyn Welch | 638f199 | 2009-12-15 08:42:49 +0000 | [diff] [blame] | 2219 | if (!geoid) { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2220 | slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT); |
Martyn Welch | 638f199 | 2009-12-15 08:42:49 +0000 | [diff] [blame] | 2221 | slot = slot & TSI148_LCSR_VSTAT_GA_M; |
| 2222 | } else |
| 2223 | slot = geoid; |
| 2224 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2225 | return (int)slot; |
| 2226 | } |
| 2227 | |
H Hartley Sweeten lin | 8a508ff | 2012-05-02 17:08:38 -0700 | [diff] [blame] | 2228 | static void *tsi148_alloc_consistent(struct device *parent, size_t size, |
Manohar Vanga | 7f58f02 | 2011-08-10 11:33:46 +0200 | [diff] [blame] | 2229 | dma_addr_t *dma) |
| 2230 | { |
| 2231 | struct pci_dev *pdev; |
| 2232 | |
| 2233 | /* Find pci_dev container of dev */ |
Aaron Sierra | 177581fa | 2014-04-03 14:48:27 -0500 | [diff] [blame] | 2234 | pdev = to_pci_dev(parent); |
Manohar Vanga | 7f58f02 | 2011-08-10 11:33:46 +0200 | [diff] [blame] | 2235 | |
| 2236 | return pci_alloc_consistent(pdev, size, dma); |
| 2237 | } |
| 2238 | |
H Hartley Sweeten lin | 8a508ff | 2012-05-02 17:08:38 -0700 | [diff] [blame] | 2239 | static void tsi148_free_consistent(struct device *parent, size_t size, |
| 2240 | void *vaddr, dma_addr_t dma) |
Manohar Vanga | 7f58f02 | 2011-08-10 11:33:46 +0200 | [diff] [blame] | 2241 | { |
| 2242 | struct pci_dev *pdev; |
| 2243 | |
| 2244 | /* Find pci_dev container of dev */ |
Aaron Sierra | 177581fa | 2014-04-03 14:48:27 -0500 | [diff] [blame] | 2245 | pdev = to_pci_dev(parent); |
Manohar Vanga | 7f58f02 | 2011-08-10 11:33:46 +0200 | [diff] [blame] | 2246 | |
| 2247 | pci_free_consistent(pdev, size, vaddr, dma); |
| 2248 | } |
| 2249 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2250 | /* |
| 2251 | * Configure CR/CSR space |
| 2252 | * |
| 2253 | * Access to the CR/CSR can be configured at power-up. The location of the |
| 2254 | * CR/CSR registers in the CR/CSR address space is determined by the boards |
| 2255 | * Auto-ID or Geographic address. This function ensures that the window is |
| 2256 | * enabled at an offset consistent with the boards geopgraphic address. |
| 2257 | * |
| 2258 | * Each board has a 512kB window, with the highest 4kB being used for the |
| 2259 | * boards registers, this means there is a fix length 508kB window which must |
| 2260 | * be mapped onto PCI memory. |
| 2261 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2262 | static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge, |
| 2263 | struct pci_dev *pdev) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2264 | { |
| 2265 | u32 cbar, crat, vstat; |
| 2266 | u32 crcsr_bus_high, crcsr_bus_low; |
| 2267 | int retval; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2268 | struct tsi148_driver *bridge; |
| 2269 | |
| 2270 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2271 | |
| 2272 | /* Allocate mem for CR/CSR image */ |
Joe Perches | 88b2608 | 2014-08-08 14:24:53 -0700 | [diff] [blame] | 2273 | bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE, |
| 2274 | &bridge->crcsr_bus); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2275 | if (bridge->crcsr_kernel == NULL) { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2276 | dev_err(tsi148_bridge->parent, "Failed to allocate memory for " |
| 2277 | "CR/CSR image\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2278 | return -ENOMEM; |
| 2279 | } |
| 2280 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2281 | reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2282 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2283 | iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU); |
| 2284 | iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2285 | |
| 2286 | /* Ensure that the CR/CSR is configured at the correct offset */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2287 | cbar = ioread32be(bridge->base + TSI148_CBAR); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2288 | cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3; |
| 2289 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2290 | vstat = tsi148_slot_get(tsi148_bridge); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2291 | |
| 2292 | if (cbar != vstat) { |
Martyn Welch | 638f199 | 2009-12-15 08:42:49 +0000 | [diff] [blame] | 2293 | cbar = vstat; |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2294 | dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n"); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2295 | iowrite32be(cbar<<3, bridge->base + TSI148_CBAR); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2296 | } |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2297 | dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2298 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2299 | crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); |
Martyn Welch | 2981795 | 2013-06-11 17:03:14 +0100 | [diff] [blame] | 2300 | if (crat & TSI148_LCSR_CRAT_EN) |
| 2301 | dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n"); |
| 2302 | else { |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2303 | dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2304 | iowrite32be(crat | TSI148_LCSR_CRAT_EN, |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2305 | bridge->base + TSI148_LCSR_CRAT); |
Martyn Welch | 2981795 | 2013-06-11 17:03:14 +0100 | [diff] [blame] | 2306 | } |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2307 | |
| 2308 | /* If we want flushed, error-checked writes, set up a window |
| 2309 | * over the CR/CSR registers. We read from here to safely flush |
| 2310 | * through VME writes. |
| 2311 | */ |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2312 | if (err_chk) { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2313 | retval = tsi148_master_set(bridge->flush_image, 1, |
| 2314 | (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT, |
| 2315 | VME_D16); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2316 | if (retval) |
Martyn Welch | 48d9356 | 2010-03-22 14:58:50 +0000 | [diff] [blame] | 2317 | dev_err(tsi148_bridge->parent, "Configuring flush image" |
| 2318 | " failed\n"); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2319 | } |
| 2320 | |
| 2321 | return 0; |
| 2322 | |
| 2323 | } |
| 2324 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2325 | static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge, |
| 2326 | struct pci_dev *pdev) |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2327 | { |
| 2328 | u32 crat; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2329 | struct tsi148_driver *bridge; |
| 2330 | |
| 2331 | bridge = tsi148_bridge->driver_priv; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2332 | |
| 2333 | /* Turn off CR/CSR space */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2334 | crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2335 | iowrite32be(crat & ~TSI148_LCSR_CRAT_EN, |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2336 | bridge->base + TSI148_LCSR_CRAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2337 | |
| 2338 | /* Free image */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2339 | iowrite32be(0, bridge->base + TSI148_LCSR_CROU); |
| 2340 | iowrite32be(0, bridge->base + TSI148_LCSR_CROL); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2341 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2342 | pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, |
| 2343 | bridge->crcsr_bus); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2344 | } |
| 2345 | |
| 2346 | static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
| 2347 | { |
| 2348 | int retval, i, master_num; |
| 2349 | u32 data; |
Wei Yongjun | b49c32b | 2012-08-21 12:19:01 +0800 | [diff] [blame] | 2350 | struct list_head *pos = NULL, *n; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2351 | struct vme_bridge *tsi148_bridge; |
| 2352 | struct tsi148_driver *tsi148_device; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2353 | struct vme_master_resource *master_image; |
| 2354 | struct vme_slave_resource *slave_image; |
| 2355 | struct vme_dma_resource *dma_ctrlr; |
Martyn Welch | 42fb503 | 2009-08-11 17:44:56 +0100 | [diff] [blame] | 2356 | struct vme_lm_resource *lm; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2357 | |
| 2358 | /* If we want to support more than one of each bridge, we need to |
| 2359 | * dynamically generate this so we get one per device |
| 2360 | */ |
Julia Lawall | 7a6cb0d | 2010-05-13 22:00:05 +0200 | [diff] [blame] | 2361 | tsi148_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2362 | if (tsi148_bridge == NULL) { |
| 2363 | dev_err(&pdev->dev, "Failed to allocate memory for device " |
| 2364 | "structure\n"); |
| 2365 | retval = -ENOMEM; |
| 2366 | goto err_struct; |
| 2367 | } |
| 2368 | |
Julia Lawall | 7a6cb0d | 2010-05-13 22:00:05 +0200 | [diff] [blame] | 2369 | tsi148_device = kzalloc(sizeof(struct tsi148_driver), GFP_KERNEL); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2370 | if (tsi148_device == NULL) { |
| 2371 | dev_err(&pdev->dev, "Failed to allocate memory for device " |
| 2372 | "structure\n"); |
| 2373 | retval = -ENOMEM; |
| 2374 | goto err_driver; |
| 2375 | } |
| 2376 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2377 | tsi148_bridge->driver_priv = tsi148_device; |
| 2378 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2379 | /* Enable the device */ |
| 2380 | retval = pci_enable_device(pdev); |
| 2381 | if (retval) { |
| 2382 | dev_err(&pdev->dev, "Unable to enable device\n"); |
| 2383 | goto err_enable; |
| 2384 | } |
| 2385 | |
| 2386 | /* Map Registers */ |
| 2387 | retval = pci_request_regions(pdev, driver_name); |
| 2388 | if (retval) { |
| 2389 | dev_err(&pdev->dev, "Unable to reserve resources\n"); |
| 2390 | goto err_resource; |
| 2391 | } |
| 2392 | |
| 2393 | /* map registers in BAR 0 */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2394 | tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0), |
| 2395 | 4096); |
| 2396 | if (!tsi148_device->base) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2397 | dev_err(&pdev->dev, "Unable to remap CRG region\n"); |
| 2398 | retval = -EIO; |
| 2399 | goto err_remap; |
| 2400 | } |
| 2401 | |
| 2402 | /* Check to see if the mapping worked out */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2403 | data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2404 | if (data != PCI_VENDOR_ID_TUNDRA) { |
| 2405 | dev_err(&pdev->dev, "CRG region check failed\n"); |
| 2406 | retval = -EIO; |
| 2407 | goto err_test; |
| 2408 | } |
| 2409 | |
| 2410 | /* Initialize wait queues & mutual exclusion flags */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2411 | init_waitqueue_head(&tsi148_device->dma_queue[0]); |
| 2412 | init_waitqueue_head(&tsi148_device->dma_queue[1]); |
| 2413 | init_waitqueue_head(&tsi148_device->iack_queue); |
| 2414 | mutex_init(&tsi148_device->vme_int); |
| 2415 | mutex_init(&tsi148_device->vme_rmw); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2416 | |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2417 | tsi148_bridge->parent = &pdev->dev; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2418 | strcpy(tsi148_bridge->name, driver_name); |
| 2419 | |
| 2420 | /* Setup IRQ */ |
| 2421 | retval = tsi148_irq_init(tsi148_bridge); |
| 2422 | if (retval != 0) { |
| 2423 | dev_err(&pdev->dev, "Chip Initialization failed.\n"); |
| 2424 | goto err_irq; |
| 2425 | } |
| 2426 | |
| 2427 | /* If we are going to flush writes, we need to read from the VME bus. |
| 2428 | * We need to do this safely, thus we read the devices own CR/CSR |
| 2429 | * register. To do this we must set up a window in CR/CSR space and |
| 2430 | * hence have one less master window resource available. |
| 2431 | */ |
| 2432 | master_num = TSI148_MAX_MASTER; |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2433 | if (err_chk) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2434 | master_num--; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2435 | |
Julia Lawall | 3241487 | 2010-05-11 20:26:57 +0200 | [diff] [blame] | 2436 | tsi148_device->flush_image = |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2437 | kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL); |
| 2438 | if (tsi148_device->flush_image == NULL) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2439 | dev_err(&pdev->dev, "Failed to allocate memory for " |
| 2440 | "flush resource structure\n"); |
| 2441 | retval = -ENOMEM; |
| 2442 | goto err_master; |
| 2443 | } |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2444 | tsi148_device->flush_image->parent = tsi148_bridge; |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2445 | spin_lock_init(&tsi148_device->flush_image->lock); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2446 | tsi148_device->flush_image->locked = 1; |
| 2447 | tsi148_device->flush_image->number = master_num; |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2448 | memset(&tsi148_device->flush_image->bus_resource, 0, |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2449 | sizeof(struct resource)); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2450 | tsi148_device->flush_image->kern_base = NULL; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2451 | } |
| 2452 | |
| 2453 | /* Add master windows to list */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2454 | INIT_LIST_HEAD(&tsi148_bridge->master_resources); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2455 | for (i = 0; i < master_num; i++) { |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2456 | master_image = kmalloc(sizeof(struct vme_master_resource), |
| 2457 | GFP_KERNEL); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2458 | if (master_image == NULL) { |
| 2459 | dev_err(&pdev->dev, "Failed to allocate memory for " |
| 2460 | "master resource structure\n"); |
| 2461 | retval = -ENOMEM; |
| 2462 | goto err_master; |
| 2463 | } |
| 2464 | master_image->parent = tsi148_bridge; |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2465 | spin_lock_init(&master_image->lock); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2466 | master_image->locked = 0; |
| 2467 | master_image->number = i; |
| 2468 | master_image->address_attr = VME_A16 | VME_A24 | VME_A32 | |
Martyn Welch | 08e03c2 | 2015-02-26 18:53:11 +0300 | [diff] [blame^] | 2469 | VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 | |
| 2470 | VME_USER3 | VME_USER4; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2471 | master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | |
| 2472 | VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 | |
| 2473 | VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | |
| 2474 | VME_PROG | VME_DATA; |
| 2475 | master_image->width_attr = VME_D16 | VME_D32; |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2476 | memset(&master_image->bus_resource, 0, |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2477 | sizeof(struct resource)); |
| 2478 | master_image->kern_base = NULL; |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2479 | list_add_tail(&master_image->list, |
| 2480 | &tsi148_bridge->master_resources); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2481 | } |
| 2482 | |
| 2483 | /* Add slave windows to list */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2484 | INIT_LIST_HEAD(&tsi148_bridge->slave_resources); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2485 | for (i = 0; i < TSI148_MAX_SLAVE; i++) { |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2486 | slave_image = kmalloc(sizeof(struct vme_slave_resource), |
| 2487 | GFP_KERNEL); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2488 | if (slave_image == NULL) { |
| 2489 | dev_err(&pdev->dev, "Failed to allocate memory for " |
| 2490 | "slave resource structure\n"); |
| 2491 | retval = -ENOMEM; |
| 2492 | goto err_slave; |
| 2493 | } |
| 2494 | slave_image->parent = tsi148_bridge; |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2495 | mutex_init(&slave_image->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2496 | slave_image->locked = 0; |
| 2497 | slave_image->number = i; |
| 2498 | slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 | |
Martyn Welch | 08e03c2 | 2015-02-26 18:53:11 +0300 | [diff] [blame^] | 2499 | VME_A64; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2500 | slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | |
| 2501 | VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 | |
| 2502 | VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | |
| 2503 | VME_PROG | VME_DATA; |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2504 | list_add_tail(&slave_image->list, |
| 2505 | &tsi148_bridge->slave_resources); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2506 | } |
| 2507 | |
| 2508 | /* Add dma engines to list */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2509 | INIT_LIST_HEAD(&tsi148_bridge->dma_resources); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2510 | for (i = 0; i < TSI148_MAX_DMA; i++) { |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2511 | dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource), |
| 2512 | GFP_KERNEL); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2513 | if (dma_ctrlr == NULL) { |
| 2514 | dev_err(&pdev->dev, "Failed to allocate memory for " |
| 2515 | "dma resource structure\n"); |
| 2516 | retval = -ENOMEM; |
| 2517 | goto err_dma; |
| 2518 | } |
| 2519 | dma_ctrlr->parent = tsi148_bridge; |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2520 | mutex_init(&dma_ctrlr->mtx); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2521 | dma_ctrlr->locked = 0; |
| 2522 | dma_ctrlr->number = i; |
Martyn Welch | 4f723df | 2010-02-18 15:12:58 +0000 | [diff] [blame] | 2523 | dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | |
| 2524 | VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME | |
| 2525 | VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME | |
| 2526 | VME_DMA_PATTERN_TO_MEM; |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2527 | INIT_LIST_HEAD(&dma_ctrlr->pending); |
| 2528 | INIT_LIST_HEAD(&dma_ctrlr->running); |
| 2529 | list_add_tail(&dma_ctrlr->list, |
| 2530 | &tsi148_bridge->dma_resources); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2531 | } |
| 2532 | |
Martyn Welch | 42fb503 | 2009-08-11 17:44:56 +0100 | [diff] [blame] | 2533 | /* Add location monitor to list */ |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2534 | INIT_LIST_HEAD(&tsi148_bridge->lm_resources); |
Martyn Welch | 42fb503 | 2009-08-11 17:44:56 +0100 | [diff] [blame] | 2535 | lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL); |
| 2536 | if (lm == NULL) { |
| 2537 | dev_err(&pdev->dev, "Failed to allocate memory for " |
| 2538 | "location monitor resource structure\n"); |
| 2539 | retval = -ENOMEM; |
| 2540 | goto err_lm; |
| 2541 | } |
| 2542 | lm->parent = tsi148_bridge; |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2543 | mutex_init(&lm->mtx); |
Martyn Welch | 42fb503 | 2009-08-11 17:44:56 +0100 | [diff] [blame] | 2544 | lm->locked = 0; |
| 2545 | lm->number = 1; |
| 2546 | lm->monitors = 4; |
Emilio G. Cota | 886953e | 2010-11-12 11:14:07 +0000 | [diff] [blame] | 2547 | list_add_tail(&lm->list, &tsi148_bridge->lm_resources); |
Martyn Welch | 42fb503 | 2009-08-11 17:44:56 +0100 | [diff] [blame] | 2548 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2549 | tsi148_bridge->slave_get = tsi148_slave_get; |
| 2550 | tsi148_bridge->slave_set = tsi148_slave_set; |
| 2551 | tsi148_bridge->master_get = tsi148_master_get; |
| 2552 | tsi148_bridge->master_set = tsi148_master_set; |
| 2553 | tsi148_bridge->master_read = tsi148_master_read; |
| 2554 | tsi148_bridge->master_write = tsi148_master_write; |
| 2555 | tsi148_bridge->master_rmw = tsi148_master_rmw; |
| 2556 | tsi148_bridge->dma_list_add = tsi148_dma_list_add; |
| 2557 | tsi148_bridge->dma_list_exec = tsi148_dma_list_exec; |
| 2558 | tsi148_bridge->dma_list_empty = tsi148_dma_list_empty; |
Martyn Welch | c813f59 | 2009-10-29 16:34:54 +0000 | [diff] [blame] | 2559 | tsi148_bridge->irq_set = tsi148_irq_set; |
| 2560 | tsi148_bridge->irq_generate = tsi148_irq_generate; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2561 | tsi148_bridge->lm_set = tsi148_lm_set; |
| 2562 | tsi148_bridge->lm_get = tsi148_lm_get; |
| 2563 | tsi148_bridge->lm_attach = tsi148_lm_attach; |
| 2564 | tsi148_bridge->lm_detach = tsi148_lm_detach; |
| 2565 | tsi148_bridge->slot_get = tsi148_slot_get; |
Manohar Vanga | 7f58f02 | 2011-08-10 11:33:46 +0200 | [diff] [blame] | 2566 | tsi148_bridge->alloc_consistent = tsi148_alloc_consistent; |
| 2567 | tsi148_bridge->free_consistent = tsi148_free_consistent; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2568 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2569 | data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2570 | dev_info(&pdev->dev, "Board is%s the VME system controller\n", |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2571 | (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not"); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2572 | if (!geoid) |
Martyn Welch | 638f199 | 2009-12-15 08:42:49 +0000 | [diff] [blame] | 2573 | dev_info(&pdev->dev, "VME geographical address is %d\n", |
| 2574 | data & TSI148_LCSR_VSTAT_GA_M); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2575 | else |
Martyn Welch | 638f199 | 2009-12-15 08:42:49 +0000 | [diff] [blame] | 2576 | dev_info(&pdev->dev, "VME geographical address is set to %d\n", |
| 2577 | geoid); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2578 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2579 | dev_info(&pdev->dev, "VME Write and flush and error check is %s\n", |
| 2580 | err_chk ? "enabled" : "disabled"); |
| 2581 | |
Wei Yongjun | 0686ab7 | 2013-06-19 10:42:35 +0800 | [diff] [blame] | 2582 | retval = tsi148_crcsr_init(tsi148_bridge, pdev); |
| 2583 | if (retval) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2584 | dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); |
| 2585 | goto err_crcsr; |
Martyn Welch | 4839737 | 2010-03-22 14:58:43 +0000 | [diff] [blame] | 2586 | } |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2587 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2588 | retval = vme_register_bridge(tsi148_bridge); |
| 2589 | if (retval != 0) { |
| 2590 | dev_err(&pdev->dev, "Chip Registration failed.\n"); |
| 2591 | goto err_reg; |
| 2592 | } |
| 2593 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2594 | pci_set_drvdata(pdev, tsi148_bridge); |
| 2595 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2596 | /* Clear VME bus "board fail", and "power-up reset" lines */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2597 | data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2598 | data &= ~TSI148_LCSR_VSTAT_BRDFL; |
| 2599 | data |= TSI148_LCSR_VSTAT_CPURST; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2600 | iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2601 | |
| 2602 | return 0; |
| 2603 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2604 | err_reg: |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2605 | tsi148_crcsr_exit(tsi148_bridge, pdev); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2606 | err_crcsr: |
Martyn Welch | 42fb503 | 2009-08-11 17:44:56 +0100 | [diff] [blame] | 2607 | err_lm: |
| 2608 | /* resources are stored in link list */ |
Wei Yongjun | b49c32b | 2012-08-21 12:19:01 +0800 | [diff] [blame] | 2609 | list_for_each_safe(pos, n, &tsi148_bridge->lm_resources) { |
Martyn Welch | 42fb503 | 2009-08-11 17:44:56 +0100 | [diff] [blame] | 2610 | lm = list_entry(pos, struct vme_lm_resource, list); |
| 2611 | list_del(pos); |
| 2612 | kfree(lm); |
| 2613 | } |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2614 | err_dma: |
| 2615 | /* resources are stored in link list */ |
Wei Yongjun | b49c32b | 2012-08-21 12:19:01 +0800 | [diff] [blame] | 2616 | list_for_each_safe(pos, n, &tsi148_bridge->dma_resources) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2617 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); |
| 2618 | list_del(pos); |
| 2619 | kfree(dma_ctrlr); |
| 2620 | } |
| 2621 | err_slave: |
| 2622 | /* resources are stored in link list */ |
Wei Yongjun | b49c32b | 2012-08-21 12:19:01 +0800 | [diff] [blame] | 2623 | list_for_each_safe(pos, n, &tsi148_bridge->slave_resources) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2624 | slave_image = list_entry(pos, struct vme_slave_resource, list); |
| 2625 | list_del(pos); |
| 2626 | kfree(slave_image); |
| 2627 | } |
| 2628 | err_master: |
| 2629 | /* resources are stored in link list */ |
Wei Yongjun | b49c32b | 2012-08-21 12:19:01 +0800 | [diff] [blame] | 2630 | list_for_each_safe(pos, n, &tsi148_bridge->master_resources) { |
Martyn Welch | 7946328 | 2010-03-22 14:58:57 +0000 | [diff] [blame] | 2631 | master_image = list_entry(pos, struct vme_master_resource, |
| 2632 | list); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2633 | list_del(pos); |
| 2634 | kfree(master_image); |
| 2635 | } |
| 2636 | |
Emilio G. Cota | a82ad05 | 2010-11-12 11:14:47 +0000 | [diff] [blame] | 2637 | tsi148_irq_exit(tsi148_bridge, pdev); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2638 | err_irq: |
| 2639 | err_test: |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2640 | iounmap(tsi148_device->base); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2641 | err_remap: |
| 2642 | pci_release_regions(pdev); |
| 2643 | err_resource: |
| 2644 | pci_disable_device(pdev); |
| 2645 | err_enable: |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2646 | kfree(tsi148_device); |
| 2647 | err_driver: |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2648 | kfree(tsi148_bridge); |
| 2649 | err_struct: |
| 2650 | return retval; |
| 2651 | |
| 2652 | } |
| 2653 | |
| 2654 | static void tsi148_remove(struct pci_dev *pdev) |
| 2655 | { |
| 2656 | struct list_head *pos = NULL; |
Emilio G. Cota | b558ba2 | 2010-11-12 11:14:34 +0000 | [diff] [blame] | 2657 | struct list_head *tmplist; |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2658 | struct vme_master_resource *master_image; |
| 2659 | struct vme_slave_resource *slave_image; |
| 2660 | struct vme_dma_resource *dma_ctrlr; |
| 2661 | int i; |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2662 | struct tsi148_driver *bridge; |
| 2663 | struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev); |
| 2664 | |
| 2665 | bridge = tsi148_bridge->driver_priv; |
| 2666 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2667 | |
| 2668 | dev_dbg(&pdev->dev, "Driver is being unloaded.\n"); |
| 2669 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2670 | /* |
| 2671 | * Shutdown all inbound and outbound windows. |
| 2672 | */ |
| 2673 | for (i = 0; i < 8; i++) { |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2674 | iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2675 | TSI148_LCSR_OFFSET_ITAT); |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2676 | iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] + |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2677 | TSI148_LCSR_OFFSET_OTAT); |
| 2678 | } |
| 2679 | |
| 2680 | /* |
| 2681 | * Shutdown Location monitor. |
| 2682 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2683 | iowrite32be(0, bridge->base + TSI148_LCSR_LMAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2684 | |
| 2685 | /* |
| 2686 | * Shutdown CRG map. |
| 2687 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2688 | iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2689 | |
| 2690 | /* |
| 2691 | * Clear error status. |
| 2692 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2693 | iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT); |
| 2694 | iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT); |
| 2695 | iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2696 | |
| 2697 | /* |
| 2698 | * Remove VIRQ interrupt (if any) |
| 2699 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2700 | if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800) |
| 2701 | iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2702 | |
| 2703 | /* |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2704 | * Map all Interrupts to PCI INTA |
| 2705 | */ |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2706 | iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1); |
| 2707 | iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2708 | |
Emilio G. Cota | a82ad05 | 2010-11-12 11:14:47 +0000 | [diff] [blame] | 2709 | tsi148_irq_exit(tsi148_bridge, pdev); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2710 | |
| 2711 | vme_unregister_bridge(tsi148_bridge); |
| 2712 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2713 | tsi148_crcsr_exit(tsi148_bridge, pdev); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2714 | |
| 2715 | /* resources are stored in link list */ |
Emilio G. Cota | b558ba2 | 2010-11-12 11:14:34 +0000 | [diff] [blame] | 2716 | list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2717 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); |
| 2718 | list_del(pos); |
| 2719 | kfree(dma_ctrlr); |
| 2720 | } |
| 2721 | |
| 2722 | /* resources are stored in link list */ |
Emilio G. Cota | b558ba2 | 2010-11-12 11:14:34 +0000 | [diff] [blame] | 2723 | list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) { |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2724 | slave_image = list_entry(pos, struct vme_slave_resource, list); |
| 2725 | list_del(pos); |
| 2726 | kfree(slave_image); |
| 2727 | } |
| 2728 | |
| 2729 | /* resources are stored in link list */ |
Emilio G. Cota | b558ba2 | 2010-11-12 11:14:34 +0000 | [diff] [blame] | 2730 | list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) { |
Martyn Welch | 638f199 | 2009-12-15 08:42:49 +0000 | [diff] [blame] | 2731 | master_image = list_entry(pos, struct vme_master_resource, |
| 2732 | list); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2733 | list_del(pos); |
| 2734 | kfree(master_image); |
| 2735 | } |
| 2736 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2737 | iounmap(bridge->base); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2738 | |
| 2739 | pci_release_regions(pdev); |
| 2740 | |
| 2741 | pci_disable_device(pdev); |
| 2742 | |
Martyn Welch | 29848ac | 2010-02-18 15:13:05 +0000 | [diff] [blame] | 2743 | kfree(tsi148_bridge->driver_priv); |
| 2744 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2745 | kfree(tsi148_bridge); |
| 2746 | } |
| 2747 | |
Wei Yongjun | 01c0714 | 2012-10-18 23:12:50 +0800 | [diff] [blame] | 2748 | module_pci_driver(tsi148_driver); |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2749 | |
| 2750 | MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes"); |
| 2751 | module_param(err_chk, bool, 0); |
| 2752 | |
Martyn Welch | 638f199 | 2009-12-15 08:42:49 +0000 | [diff] [blame] | 2753 | MODULE_PARM_DESC(geoid, "Override geographical addressing"); |
| 2754 | module_param(geoid, int, 0); |
| 2755 | |
Martyn Welch | d22b8ed | 2009-07-31 09:28:17 +0100 | [diff] [blame] | 2756 | MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge"); |
| 2757 | MODULE_LICENSE("GPL"); |