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Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -03001/* Intel i7 core/Nehalem Memory Controller kernel module
2 *
David Sterbae7bf0682010-12-27 16:51:15 +01003 * This driver supports the memory controllers found on the Intel
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -03004 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
5 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
6 * and Westmere-EP.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03007 *
8 * This file may be distributed under the terms of the
9 * GNU General Public License version 2 only.
10 *
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -030011 * Copyright (c) 2009-2010 by:
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030012 * Mauro Carvalho Chehab <mchehab@redhat.com>
13 *
14 * Red Hat Inc. http://www.redhat.com
15 *
16 * Forked and adapted from the i5400_edac driver
17 *
18 * Based on the following public Intel datasheets:
19 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
20 * Datasheet, Volume 2:
21 * http://download.intel.com/design/processor/datashts/320835.pdf
22 * Intel Xeon Processor 5500 Series Datasheet Volume 2
23 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
24 * also available at:
25 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
26 */
27
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030028#include <linux/module.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/pci_ids.h>
32#include <linux/slab.h>
Randy Dunlap3b918c12009-11-08 01:36:40 -020033#include <linux/delay.h>
Nils Carlson535e9c72011-08-08 06:21:26 -030034#include <linux/dmi.h>
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030035#include <linux/edac.h>
36#include <linux/mmzone.h>
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -030037#include <linux/smp.h>
Borislav Petkov4140c542011-07-18 11:24:46 -030038#include <asm/mce.h>
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -030039#include <asm/processor.h>
Sedat Dilek4fad8092011-09-21 23:44:52 -030040#include <asm/div64.h>
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030041
42#include "edac_core.h"
43
Mauro Carvalho Chehab18c29002010-08-10 18:33:27 -030044/* Static vars */
45static LIST_HEAD(i7core_edac_list);
46static DEFINE_MUTEX(i7core_edac_lock);
47static int probed;
48
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -030049static int use_pci_fixup;
50module_param(use_pci_fixup, int, 0444);
51MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030052/*
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -030053 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
54 * registers start at bus 255, and are not reported by BIOS.
55 * We currently find devices with only 2 sockets. In order to support more QPI
56 * Quick Path Interconnect, just increment this number.
57 */
58#define MAX_SOCKET_BUSES 2
59
60
61/*
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030062 * Alter this version for the module when modifications are made
63 */
Michal Marek152ba392011-04-01 12:41:20 +020064#define I7CORE_REVISION " Ver: 1.0.0"
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030065#define EDAC_MOD_STR "i7core_edac"
66
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030067/*
68 * Debug macros
69 */
70#define i7core_printk(level, fmt, arg...) \
71 edac_printk(level, "i7core", fmt, ##arg)
72
73#define i7core_mc_printk(mci, level, fmt, arg...) \
74 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
75
76/*
77 * i7core Memory Controller Registers
78 */
79
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -030080 /* OFFSETS for Device 0 Function 0 */
81
82#define MC_CFG_CONTROL 0x90
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -030083 #define MC_CFG_UNLOCK 0x02
84 #define MC_CFG_LOCK 0x00
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -030085
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030086 /* OFFSETS for Device 3 Function 0 */
87
88#define MC_CONTROL 0x48
89#define MC_STATUS 0x4c
90#define MC_MAX_DOD 0x64
91
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -030092/*
93 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
94 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
95 */
96
97#define MC_TEST_ERR_RCV1 0x60
98 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
99
100#define MC_TEST_ERR_RCV0 0x64
101 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
102 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
103
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300104/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -0300105#define MC_SSRCONTROL 0x48
106 #define SSR_MODE_DISABLE 0x00
107 #define SSR_MODE_ENABLE 0x01
108 #define SSR_MODE_MASK 0x03
109
110#define MC_SCRUB_CONTROL 0x4c
111 #define STARTSCRUB (1 << 24)
Nils Carlson535e9c72011-08-08 06:21:26 -0300112 #define SCRUBINTERVAL_MASK 0xffffff
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -0300113
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300114#define MC_COR_ECC_CNT_0 0x80
115#define MC_COR_ECC_CNT_1 0x84
116#define MC_COR_ECC_CNT_2 0x88
117#define MC_COR_ECC_CNT_3 0x8c
118#define MC_COR_ECC_CNT_4 0x90
119#define MC_COR_ECC_CNT_5 0x94
120
121#define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
122#define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
123
124
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300125 /* OFFSETS for Devices 4,5 and 6 Function 0 */
126
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300127#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
128 #define THREE_DIMMS_PRESENT (1 << 24)
129 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
130 #define QUAD_RANK_PRESENT (1 << 22)
131 #define REGISTERED_DIMM (1 << 15)
132
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300133#define MC_CHANNEL_MAPPER 0x60
134 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
135 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
136
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300137#define MC_CHANNEL_RANK_PRESENT 0x7c
138 #define RANK_PRESENT_MASK 0xffff
139
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300140#define MC_CHANNEL_ADDR_MATCH 0xf0
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300141#define MC_CHANNEL_ERROR_MASK 0xf8
142#define MC_CHANNEL_ERROR_INJECT 0xfc
143 #define INJECT_ADDR_PARITY 0x10
144 #define INJECT_ECC 0x08
145 #define MASK_CACHELINE 0x06
146 #define MASK_FULL_CACHELINE 0x06
147 #define MASK_MSB32_CACHELINE 0x04
148 #define MASK_LSB32_CACHELINE 0x02
149 #define NO_MASK_CACHELINE 0x00
150 #define REPEAT_EN 0x01
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300151
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300152 /* OFFSETS for Devices 4,5 and 6 Function 1 */
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -0300153
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300154#define MC_DOD_CH_DIMM0 0x48
155#define MC_DOD_CH_DIMM1 0x4c
156#define MC_DOD_CH_DIMM2 0x50
157 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
158 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
159 #define DIMM_PRESENT_MASK (1 << 9)
160 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300161 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
162 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
163 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
164 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300165 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300166 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300167 #define MC_DOD_NUMCOL_MASK 3
168 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300169
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300170#define MC_RANK_PRESENT 0x7c
171
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300172#define MC_SAG_CH_0 0x80
173#define MC_SAG_CH_1 0x84
174#define MC_SAG_CH_2 0x88
175#define MC_SAG_CH_3 0x8c
176#define MC_SAG_CH_4 0x90
177#define MC_SAG_CH_5 0x94
178#define MC_SAG_CH_6 0x98
179#define MC_SAG_CH_7 0x9c
180
181#define MC_RIR_LIMIT_CH_0 0x40
182#define MC_RIR_LIMIT_CH_1 0x44
183#define MC_RIR_LIMIT_CH_2 0x48
184#define MC_RIR_LIMIT_CH_3 0x4C
185#define MC_RIR_LIMIT_CH_4 0x50
186#define MC_RIR_LIMIT_CH_5 0x54
187#define MC_RIR_LIMIT_CH_6 0x58
188#define MC_RIR_LIMIT_CH_7 0x5C
189#define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
190
191#define MC_RIR_WAY_CH 0x80
192 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
193 #define MC_RIR_WAY_RANK_MASK 0x7
194
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300195/*
196 * i7core structs
197 */
198
199#define NUM_CHANS 3
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300200#define MAX_DIMMS 3 /* Max DIMMS per channel */
201#define MAX_MCR_FUNC 4
202#define MAX_CHAN_FUNC 3
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300203
204struct i7core_info {
205 u32 mc_control;
206 u32 mc_status;
207 u32 max_dod;
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300208 u32 ch_map;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300209};
210
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300211
212struct i7core_inject {
213 int enable;
214
215 u32 section;
216 u32 type;
217 u32 eccmask;
218
219 /* Error address mask */
220 int channel, dimm, rank, bank, page, col;
221};
222
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300223struct i7core_channel {
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300224 u32 ranks;
225 u32 dimms;
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300226};
227
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300228struct pci_id_descr {
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300229 int dev;
230 int func;
231 int dev_id;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300232 int optional;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300233};
234
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300235struct pci_id_table {
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300236 const struct pci_id_descr *descr;
237 int n_devs;
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300238};
239
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300240struct i7core_dev {
241 struct list_head list;
242 u8 socket;
243 struct pci_dev **pdev;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300244 int n_devs;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300245 struct mem_ctl_info *mci;
246};
247
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300248struct i7core_pvt {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300249 struct pci_dev *pci_noncore;
250 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
251 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
252
253 struct i7core_dev *i7core_dev;
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300254
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300255 struct i7core_info info;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300256 struct i7core_inject inject;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300257 struct i7core_channel channel[NUM_CHANS];
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300258
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300259 int ce_count_available;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300260
261 /* ECC corrected errors counts per udimm */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300262 unsigned long udimm_ce_count[MAX_DIMMS];
263 int udimm_last_ce_count[MAX_DIMMS];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300264 /* ECC corrected errors counts per rdimm */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300265 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
266 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300267
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -0300268 bool is_registered, enable_scrub;
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -0300269
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -0300270 /* Fifo double buffers */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -0300271 struct mce mce_entry[MCE_LOG_LEN];
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -0300272 struct mce mce_outentry[MCE_LOG_LEN];
273
274 /* Fifo in/out counters */
275 unsigned mce_in, mce_out;
276
277 /* Count indicator to show errors not got */
278 unsigned mce_overrun;
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -0300279
Nils Carlson535e9c72011-08-08 06:21:26 -0300280 /* DCLK Frequency used for computing scrub rate */
281 int dclk_freq;
282
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -0300283 /* Struct to control EDAC polling */
284 struct edac_pci_ctl_info *i7core_pci;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300285};
286
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300287#define PCI_DESCR(device, function, device_id) \
288 .dev = (device), \
289 .func = (function), \
290 .dev_id = (device_id)
291
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300292static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300293 /* Memory controller */
294 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
295 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300296 /* Exists only for RDIMM */
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300297 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300298 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
299
300 /* Channel 0 */
301 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
302 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
303 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
304 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
305
306 /* Channel 1 */
307 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
308 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
309 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
310 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
311
312 /* Channel 2 */
313 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
314 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
315 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
316 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300317
318 /* Generic Non-core registers */
319 /*
320 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
321 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
322 * the probing code needs to test for the other address in case of
323 * failure of this one
324 */
325 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
326
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300327};
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300328
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300329static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300330 { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
331 { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
332 { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
333
334 { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
335 { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
336 { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
337 { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
338
Mauro Carvalho Chehab508fa172009-10-14 13:44:37 -0300339 { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
340 { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
341 { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
342 { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300343
344 /*
345 * This is the PCI device has an alternate address on some
346 * processors like Core i7 860
347 */
348 { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300349};
350
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300351static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300352 /* Memory controller */
353 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
354 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
355 /* Exists only for RDIMM */
356 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
357 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
358
359 /* Channel 0 */
360 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
361 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
362 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
363 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
364
365 /* Channel 1 */
366 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
367 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
368 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
369 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
370
371 /* Channel 2 */
372 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
373 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
374 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
375 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300376
377 /* Generic Non-core registers */
378 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
379
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300380};
381
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300382#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
383static const struct pci_id_table pci_dev_table[] = {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300384 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
385 PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
386 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -0200387 {0,} /* 0 terminated list. */
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300388};
389
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300390/*
391 * pci_device_id table for which devices we are looking for
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300392 */
Lionel Debroux36c46f32012-02-27 07:41:47 +0100393static DEFINE_PCI_DEVICE_TABLE(i7core_pci_tbl) = {
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -0300394 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
Mauro Carvalho Chehabf05da2f2009-10-14 13:31:06 -0300395 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300396 {0,} /* 0 terminated list. */
397};
398
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300399/****************************************************************************
400 Anciliary status routines
401 ****************************************************************************/
402
403 /* MC_CONTROL bits */
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300404#define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
405#define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300406
407 /* MC_STATUS bits */
Keith Mannthey61053fd2009-09-02 23:46:59 -0300408#define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300409#define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300410
411 /* MC_MAX_DOD read functions */
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300412static inline int numdimms(u32 dimms)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300413{
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300414 return (dimms & 0x3) + 1;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300415}
416
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300417static inline int numrank(u32 rank)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300418{
419 static int ranks[4] = { 1, 2, 4, -EINVAL };
420
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300421 return ranks[rank & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300422}
423
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300424static inline int numbank(u32 bank)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300425{
426 static int banks[4] = { 4, 8, 16, -EINVAL };
427
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300428 return banks[bank & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300429}
430
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300431static inline int numrow(u32 row)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300432{
433 static int rows[8] = {
434 1 << 12, 1 << 13, 1 << 14, 1 << 15,
435 1 << 16, -EINVAL, -EINVAL, -EINVAL,
436 };
437
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300438 return rows[row & 0x7];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300439}
440
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300441static inline int numcol(u32 col)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300442{
443 static int cols[8] = {
444 1 << 10, 1 << 11, 1 << 12, -EINVAL,
445 };
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300446 return cols[col & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300447}
448
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300449static struct i7core_dev *get_i7core_dev(u8 socket)
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300450{
451 struct i7core_dev *i7core_dev;
452
453 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
454 if (i7core_dev->socket == socket)
455 return i7core_dev;
456 }
457
458 return NULL;
459}
460
Hidetoshi Seto848b2f72010-08-20 04:24:44 -0300461static struct i7core_dev *alloc_i7core_dev(u8 socket,
462 const struct pci_id_table *table)
463{
464 struct i7core_dev *i7core_dev;
465
466 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
467 if (!i7core_dev)
468 return NULL;
469
470 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
471 GFP_KERNEL);
472 if (!i7core_dev->pdev) {
473 kfree(i7core_dev);
474 return NULL;
475 }
476
477 i7core_dev->socket = socket;
478 i7core_dev->n_devs = table->n_devs;
479 list_add_tail(&i7core_dev->list, &i7core_edac_list);
480
481 return i7core_dev;
482}
483
Hidetoshi Seto2aa9be42010-08-20 04:25:00 -0300484static void free_i7core_dev(struct i7core_dev *i7core_dev)
485{
486 list_del(&i7core_dev->list);
487 kfree(i7core_dev->pdev);
488 kfree(i7core_dev);
489}
490
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300491/****************************************************************************
492 Memory check routines
493 ****************************************************************************/
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300494
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300495static int get_dimm_config(struct mem_ctl_info *mci)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300496{
497 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300498 struct pci_dev *pdev;
Mauro Carvalho Chehabba6c5c62009-07-15 09:02:32 -0300499 int i, j;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300500 enum edac_type mode;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300501 enum mem_type mtype;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300502 struct dimm_info *dimm;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300503
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300504 /* Get data from the MC register, function 0 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300505 pdev = pvt->pci_mcr[0];
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300506 if (!pdev)
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300507 return -ENODEV;
508
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300509 /* Device 3 function 0 reads */
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300510 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
511 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
512 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
513 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300514
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300515 debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
Mauro Carvalho Chehab4af91882009-09-24 09:58:26 -0300516 pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300517 pvt->info.max_dod, pvt->info.ch_map);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300518
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300519 if (ECC_ENABLED(pvt)) {
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300520 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300521 if (ECCx8(pvt))
522 mode = EDAC_S8ECD8ED;
523 else
524 mode = EDAC_S4ECD4ED;
525 } else {
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300526 debugf0("ECC disabled\n");
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300527 mode = EDAC_NONE;
528 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300529
530 /* FIXME: need to handle the error codes */
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300531 debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
532 "x%x x 0x%x\n",
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300533 numdimms(pvt->info.max_dod),
534 numrank(pvt->info.max_dod >> 2),
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300535 numbank(pvt->info.max_dod >> 4),
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300536 numrow(pvt->info.max_dod >> 6),
537 numcol(pvt->info.max_dod >> 9));
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300538
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300539 for (i = 0; i < NUM_CHANS; i++) {
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300540 u32 data, dimm_dod[3], value[8];
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300541
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300542 if (!pvt->pci_ch[i][0])
543 continue;
544
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300545 if (!CH_ACTIVE(pvt, i)) {
546 debugf0("Channel %i is not active\n", i);
547 continue;
548 }
549 if (CH_DISABLED(pvt, i)) {
550 debugf0("Channel %i is disabled\n", i);
551 continue;
552 }
553
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300554 /* Devices 4-6 function 0 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300555 pci_read_config_dword(pvt->pci_ch[i][0],
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300556 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
557
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300558 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300559 4 : 2;
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300560
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300561 if (data & REGISTERED_DIMM)
562 mtype = MEM_RDDR3;
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -0300563 else
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300564 mtype = MEM_DDR3;
565#if 0
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300566 if (data & THREE_DIMMS_PRESENT)
567 pvt->channel[i].dimms = 3;
568 else if (data & SINGLE_QUAD_RANK_PRESENT)
569 pvt->channel[i].dimms = 1;
570 else
571 pvt->channel[i].dimms = 2;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300572#endif
573
574 /* Devices 4-6 function 1 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300575 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300576 MC_DOD_CH_DIMM0, &dimm_dod[0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300577 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300578 MC_DOD_CH_DIMM1, &dimm_dod[1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300579 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300580 MC_DOD_CH_DIMM2, &dimm_dod[2]);
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300581
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300582 debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300583 "%d ranks, %cDIMMs\n",
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300584 i,
585 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
586 data,
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300587 pvt->channel[i].ranks,
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300588 (data & REGISTERED_DIMM) ? 'R' : 'U');
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300589
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300590 for (j = 0; j < 3; j++) {
591 u32 banks, ranks, rows, cols;
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300592 u32 size, npages;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300593
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300594 if (!DIMM_PRESENT(dimm_dod[j]))
595 continue;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300596
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -0300597 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
598 i, j, 0);
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300599 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
600 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
601 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
602 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300603
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300604 /* DDR3 has 8 I/O banks */
605 size = (rows * cols * banks * ranks) >> (20 - 3);
606
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300607 debugf0("\tdimm %d %d Mb offset: %x, "
608 "bank: %d, rank: %d, row: %#x, col: %#x\n",
609 j, size,
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300610 RANKOFFSET(dimm_dod[j]),
611 banks, ranks, rows, cols);
612
Mauro Carvalho Chehabe9144602010-08-10 20:26:35 -0300613 npages = MiB_TO_PAGES(size);
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300614
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300615 dimm->nr_pages = npages;
616
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300617 switch (banks) {
618 case 4:
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300619 dimm->dtype = DEV_X4;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300620 break;
621 case 8:
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300622 dimm->dtype = DEV_X8;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300623 break;
624 case 16:
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300625 dimm->dtype = DEV_X16;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300626 break;
627 default:
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300628 dimm->dtype = DEV_UNKNOWN;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300629 }
630
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300631 snprintf(dimm->label, sizeof(dimm->label),
632 "CPU#%uChannel#%u_DIMM#%u",
633 pvt->i7core_dev->socket, i, j);
634 dimm->grain = 8;
635 dimm->edac_mode = mode;
636 dimm->mtype = mtype;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300637 }
638
639 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
640 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
641 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
642 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
643 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
644 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
645 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
646 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300647 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300648 for (j = 0; j < 8; j++)
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300649 debugf1("\t\t%#x\t%#x\t%#x\n",
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300650 (value[j] >> 27) & 0x1,
651 (value[j] >> 24) & 0x7,
David Sterba80b8ce82010-12-27 15:39:12 +0000652 (value[j] & ((1 << 24) - 1)));
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300653 }
654
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300655 return 0;
656}
657
658/****************************************************************************
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300659 Error insertion routines
660 ****************************************************************************/
661
662/* The i7core has independent error injection features per channel.
663 However, to have a simpler code, we don't allow enabling error injection
664 on more than one channel.
665 Also, since a change at an inject parameter will be applied only at enable,
666 we're disabling error injection on all write calls to the sysfs nodes that
667 controls the error code injection.
668 */
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300669static int disable_inject(const struct mem_ctl_info *mci)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300670{
671 struct i7core_pvt *pvt = mci->pvt_info;
672
673 pvt->inject.enable = 0;
674
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300675 if (!pvt->pci_ch[pvt->inject.channel][0])
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300676 return -ENODEV;
677
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300678 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300679 MC_CHANNEL_ERROR_INJECT, 0);
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300680
681 return 0;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300682}
683
684/*
685 * i7core inject inject.section
686 *
687 * accept and store error injection inject.section value
688 * bit 0 - refers to the lower 32-byte half cacheline
689 * bit 1 - refers to the upper 32-byte half cacheline
690 */
691static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
692 const char *data, size_t count)
693{
694 struct i7core_pvt *pvt = mci->pvt_info;
695 unsigned long value;
696 int rc;
697
698 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300699 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300700
701 rc = strict_strtoul(data, 10, &value);
702 if ((rc < 0) || (value > 3))
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300703 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300704
705 pvt->inject.section = (u32) value;
706 return count;
707}
708
709static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
710 char *data)
711{
712 struct i7core_pvt *pvt = mci->pvt_info;
713 return sprintf(data, "0x%08x\n", pvt->inject.section);
714}
715
716/*
717 * i7core inject.type
718 *
719 * accept and store error injection inject.section value
720 * bit 0 - repeat enable - Enable error repetition
721 * bit 1 - inject ECC error
722 * bit 2 - inject parity error
723 */
724static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
725 const char *data, size_t count)
726{
727 struct i7core_pvt *pvt = mci->pvt_info;
728 unsigned long value;
729 int rc;
730
731 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300732 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300733
734 rc = strict_strtoul(data, 10, &value);
735 if ((rc < 0) || (value > 7))
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300736 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300737
738 pvt->inject.type = (u32) value;
739 return count;
740}
741
742static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
743 char *data)
744{
745 struct i7core_pvt *pvt = mci->pvt_info;
746 return sprintf(data, "0x%08x\n", pvt->inject.type);
747}
748
749/*
750 * i7core_inject_inject.eccmask_store
751 *
752 * The type of error (UE/CE) will depend on the inject.eccmask value:
753 * Any bits set to a 1 will flip the corresponding ECC bit
754 * Correctable errors can be injected by flipping 1 bit or the bits within
755 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
756 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
757 * uncorrectable error to be injected.
758 */
759static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
760 const char *data, size_t count)
761{
762 struct i7core_pvt *pvt = mci->pvt_info;
763 unsigned long value;
764 int rc;
765
766 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300767 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300768
769 rc = strict_strtoul(data, 10, &value);
770 if (rc < 0)
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300771 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300772
773 pvt->inject.eccmask = (u32) value;
774 return count;
775}
776
777static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
778 char *data)
779{
780 struct i7core_pvt *pvt = mci->pvt_info;
781 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
782}
783
784/*
785 * i7core_addrmatch
786 *
787 * The type of error (UE/CE) will depend on the inject.eccmask value:
788 * Any bits set to a 1 will flip the corresponding ECC bit
789 * Correctable errors can be injected by flipping 1 bit or the bits within
790 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
791 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
792 * uncorrectable error to be injected.
793 */
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300794
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300795#define DECLARE_ADDR_MATCH(param, limit) \
796static ssize_t i7core_inject_store_##param( \
797 struct mem_ctl_info *mci, \
798 const char *data, size_t count) \
799{ \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300800 struct i7core_pvt *pvt; \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300801 long value; \
802 int rc; \
803 \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300804 debugf1("%s()\n", __func__); \
805 pvt = mci->pvt_info; \
806 \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300807 if (pvt->inject.enable) \
808 disable_inject(mci); \
809 \
Mauro Carvalho Chehab4f87fad2009-10-04 11:54:56 -0300810 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300811 value = -1; \
812 else { \
813 rc = strict_strtoul(data, 10, &value); \
814 if ((rc < 0) || (value >= limit)) \
815 return -EIO; \
816 } \
817 \
818 pvt->inject.param = value; \
819 \
820 return count; \
821} \
822 \
823static ssize_t i7core_inject_show_##param( \
824 struct mem_ctl_info *mci, \
825 char *data) \
826{ \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300827 struct i7core_pvt *pvt; \
828 \
829 pvt = mci->pvt_info; \
830 debugf1("%s() pvt=%p\n", __func__, pvt); \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300831 if (pvt->inject.param < 0) \
832 return sprintf(data, "any\n"); \
833 else \
834 return sprintf(data, "%d\n", pvt->inject.param);\
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300835}
836
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300837#define ATTR_ADDR_MATCH(param) \
838 { \
839 .attr = { \
840 .name = #param, \
841 .mode = (S_IRUGO | S_IWUSR) \
842 }, \
843 .show = i7core_inject_show_##param, \
844 .store = i7core_inject_store_##param, \
845 }
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300846
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300847DECLARE_ADDR_MATCH(channel, 3);
848DECLARE_ADDR_MATCH(dimm, 3);
849DECLARE_ADDR_MATCH(rank, 4);
850DECLARE_ADDR_MATCH(bank, 32);
851DECLARE_ADDR_MATCH(page, 0x10000);
852DECLARE_ADDR_MATCH(col, 0x4000);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300853
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300854static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300855{
856 u32 read;
857 int count;
858
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300859 debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
860 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
861 where, val);
862
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300863 for (count = 0; count < 10; count++) {
864 if (count)
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -0300865 msleep(100);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300866 pci_write_config_dword(dev, where, val);
867 pci_read_config_dword(dev, where, &read);
868
869 if (read == val)
870 return 0;
871 }
872
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300873 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
874 "write=%08x. Read=%08x\n",
875 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
876 where, val, read);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300877
878 return -EINVAL;
879}
880
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300881/*
882 * This routine prepares the Memory Controller for error injection.
883 * The error will be injected when some process tries to write to the
884 * memory that matches the given criteria.
885 * The criteria can be set in terms of a mask where dimm, rank, bank, page
886 * and col can be specified.
887 * A -1 value for any of the mask items will make the MCU to ignore
888 * that matching criteria for error injection.
889 *
890 * It should be noticed that the error will only happen after a write operation
891 * on a memory that matches the condition. if REPEAT_EN is not enabled at
892 * inject mask, then it will produce just one error. Otherwise, it will repeat
893 * until the injectmask would be cleaned.
894 *
895 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
896 * is reliable enough to check if the MC is using the
897 * three channels. However, this is not clear at the datasheet.
898 */
899static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
900 const char *data, size_t count)
901{
902 struct i7core_pvt *pvt = mci->pvt_info;
903 u32 injectmask;
904 u64 mask = 0;
905 int rc;
906 long enable;
907
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300908 if (!pvt->pci_ch[pvt->inject.channel][0])
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300909 return 0;
910
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300911 rc = strict_strtoul(data, 10, &enable);
912 if ((rc < 0))
913 return 0;
914
915 if (enable) {
916 pvt->inject.enable = 1;
917 } else {
918 disable_inject(mci);
919 return count;
920 }
921
922 /* Sets pvt->inject.dimm mask */
923 if (pvt->inject.dimm < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200924 mask |= 1LL << 41;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300925 else {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300926 if (pvt->channel[pvt->inject.channel].dimms > 2)
Alan Cox486dd092009-11-08 01:34:27 -0200927 mask |= (pvt->inject.dimm & 0x3LL) << 35;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300928 else
Alan Cox486dd092009-11-08 01:34:27 -0200929 mask |= (pvt->inject.dimm & 0x1LL) << 36;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300930 }
931
932 /* Sets pvt->inject.rank mask */
933 if (pvt->inject.rank < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200934 mask |= 1LL << 40;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300935 else {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300936 if (pvt->channel[pvt->inject.channel].dimms > 2)
Alan Cox486dd092009-11-08 01:34:27 -0200937 mask |= (pvt->inject.rank & 0x1LL) << 34;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300938 else
Alan Cox486dd092009-11-08 01:34:27 -0200939 mask |= (pvt->inject.rank & 0x3LL) << 34;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300940 }
941
942 /* Sets pvt->inject.bank mask */
943 if (pvt->inject.bank < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200944 mask |= 1LL << 39;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300945 else
Alan Cox486dd092009-11-08 01:34:27 -0200946 mask |= (pvt->inject.bank & 0x15LL) << 30;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300947
948 /* Sets pvt->inject.page mask */
949 if (pvt->inject.page < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200950 mask |= 1LL << 38;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300951 else
Alan Cox486dd092009-11-08 01:34:27 -0200952 mask |= (pvt->inject.page & 0xffff) << 14;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300953
954 /* Sets pvt->inject.column mask */
955 if (pvt->inject.col < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200956 mask |= 1LL << 37;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300957 else
Alan Cox486dd092009-11-08 01:34:27 -0200958 mask |= (pvt->inject.col & 0x3fff);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300959
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300960 /*
961 * bit 0: REPEAT_EN
962 * bits 1-2: MASK_HALF_CACHELINE
963 * bit 3: INJECT_ECC
964 * bit 4: INJECT_ADDR_PARITY
965 */
966
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -0300967 injectmask = (pvt->inject.type & 1) |
968 (pvt->inject.section & 0x3) << 1 |
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300969 (pvt->inject.type & 0x6) << (3 - 1);
970
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300971 /* Unlock writes to registers - this register is write only */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300972 pci_write_config_dword(pvt->pci_noncore,
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300973 MC_CFG_CONTROL, 0x2);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300974
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300975 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300976 MC_CHANNEL_ADDR_MATCH, mask);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300977 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300978 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
979
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300980 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300981 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
982
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300983 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300984 MC_CHANNEL_ERROR_INJECT, injectmask);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300985
986 /*
987 * This is something undocumented, based on my tests
988 * Without writing 8 to this register, errors aren't injected. Not sure
989 * why.
990 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300991 pci_write_config_dword(pvt->pci_noncore,
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300992 MC_CFG_CONTROL, 8);
993
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300994 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
995 " inject 0x%08x\n",
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300996 mask, pvt->inject.eccmask, injectmask);
997
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -0300998
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300999 return count;
1000}
1001
1002static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
1003 char *data)
1004{
1005 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001006 u32 injectmask;
1007
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -03001008 if (!pvt->pci_ch[pvt->inject.channel][0])
1009 return 0;
1010
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001011 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -03001012 MC_CHANNEL_ERROR_INJECT, &injectmask);
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001013
1014 debugf0("Inject error read: 0x%018x\n", injectmask);
1015
1016 if (injectmask & 0x0c)
1017 pvt->inject.enable = 1;
1018
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001019 return sprintf(data, "%d\n", pvt->inject.enable);
1020}
1021
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001022#define DECLARE_COUNTER(param) \
1023static ssize_t i7core_show_counter_##param( \
1024 struct mem_ctl_info *mci, \
1025 char *data) \
1026{ \
1027 struct i7core_pvt *pvt = mci->pvt_info; \
1028 \
1029 debugf1("%s() \n", __func__); \
1030 if (!pvt->ce_count_available || (pvt->is_registered)) \
1031 return sprintf(data, "data unavailable\n"); \
1032 return sprintf(data, "%lu\n", \
1033 pvt->udimm_ce_count[param]); \
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001034}
1035
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001036#define ATTR_COUNTER(param) \
1037 { \
1038 .attr = { \
1039 .name = __stringify(udimm##param), \
1040 .mode = (S_IRUGO | S_IWUSR) \
1041 }, \
1042 .show = i7core_show_counter_##param \
1043 }
1044
1045DECLARE_COUNTER(0);
1046DECLARE_COUNTER(1);
1047DECLARE_COUNTER(2);
1048
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001049/*
1050 * Sysfs struct
1051 */
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001052
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001053static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001054 ATTR_ADDR_MATCH(channel),
1055 ATTR_ADDR_MATCH(dimm),
1056 ATTR_ADDR_MATCH(rank),
1057 ATTR_ADDR_MATCH(bank),
1058 ATTR_ADDR_MATCH(page),
1059 ATTR_ADDR_MATCH(col),
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001060 { } /* End of list */
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001061};
1062
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001063static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001064 .name = "inject_addrmatch",
1065 .mcidev_attr = i7core_addrmatch_attrs,
1066};
1067
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001068static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001069 ATTR_COUNTER(0),
1070 ATTR_COUNTER(1),
1071 ATTR_COUNTER(2),
Marcin Slusarz64aab722010-09-30 15:15:30 -07001072 { .attr = { .name = NULL } }
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001073};
1074
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001075static const struct mcidev_sysfs_group i7core_udimm_counters = {
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001076 .name = "all_channel_counts",
1077 .mcidev_attr = i7core_udimm_counters_attrs,
1078};
1079
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001080static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001081 {
1082 .attr = {
1083 .name = "inject_section",
1084 .mode = (S_IRUGO | S_IWUSR)
1085 },
1086 .show = i7core_inject_section_show,
1087 .store = i7core_inject_section_store,
1088 }, {
1089 .attr = {
1090 .name = "inject_type",
1091 .mode = (S_IRUGO | S_IWUSR)
1092 },
1093 .show = i7core_inject_type_show,
1094 .store = i7core_inject_type_store,
1095 }, {
1096 .attr = {
1097 .name = "inject_eccmask",
1098 .mode = (S_IRUGO | S_IWUSR)
1099 },
1100 .show = i7core_inject_eccmask_show,
1101 .store = i7core_inject_eccmask_store,
1102 }, {
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001103 .grp = &i7core_inject_addrmatch,
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001104 }, {
1105 .attr = {
1106 .name = "inject_enable",
1107 .mode = (S_IRUGO | S_IWUSR)
1108 },
1109 .show = i7core_inject_enable_show,
1110 .store = i7core_inject_enable_store,
1111 },
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001112 { } /* End of list */
1113};
1114
1115static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
1116 {
1117 .attr = {
1118 .name = "inject_section",
1119 .mode = (S_IRUGO | S_IWUSR)
1120 },
1121 .show = i7core_inject_section_show,
1122 .store = i7core_inject_section_store,
1123 }, {
1124 .attr = {
1125 .name = "inject_type",
1126 .mode = (S_IRUGO | S_IWUSR)
1127 },
1128 .show = i7core_inject_type_show,
1129 .store = i7core_inject_type_store,
1130 }, {
1131 .attr = {
1132 .name = "inject_eccmask",
1133 .mode = (S_IRUGO | S_IWUSR)
1134 },
1135 .show = i7core_inject_eccmask_show,
1136 .store = i7core_inject_eccmask_store,
1137 }, {
1138 .grp = &i7core_inject_addrmatch,
1139 }, {
1140 .attr = {
1141 .name = "inject_enable",
1142 .mode = (S_IRUGO | S_IWUSR)
1143 },
1144 .show = i7core_inject_enable_show,
1145 .store = i7core_inject_enable_store,
1146 }, {
1147 .grp = &i7core_udimm_counters,
1148 },
1149 { } /* End of list */
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001150};
1151
1152/****************************************************************************
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001153 Device initialization routines: put/get, init/exit
1154 ****************************************************************************/
1155
1156/*
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001157 * i7core_put_all_devices 'put' all the devices that we have
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001158 * reserved via 'get'
1159 */
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001160static void i7core_put_devices(struct i7core_dev *i7core_dev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001161{
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001162 int i;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001163
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03001164 debugf0(__FILE__ ": %s()\n", __func__);
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001165 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03001166 struct pci_dev *pdev = i7core_dev->pdev[i];
1167 if (!pdev)
1168 continue;
1169 debugf0("Removing dev %02x:%02x.%d\n",
1170 pdev->bus->number,
1171 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1172 pci_dev_put(pdev);
1173 }
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001174}
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001175
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001176static void i7core_put_all_devices(void)
1177{
Mauro Carvalho Chehab42538682009-09-24 09:59:13 -03001178 struct i7core_dev *i7core_dev, *tmp;
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001179
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03001180 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001181 i7core_put_devices(i7core_dev);
Hidetoshi Seto2aa9be42010-08-20 04:25:00 -03001182 free_i7core_dev(i7core_dev);
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03001183 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001184}
1185
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001186static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
Keith Manntheybc2d7242009-09-03 00:05:05 -03001187{
1188 struct pci_dev *pdev = NULL;
1189 int i;
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -03001190
Keith Manntheybc2d7242009-09-03 00:05:05 -03001191 /*
David Sterbae7bf0682010-12-27 16:51:15 +01001192 * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses
Keith Manntheybc2d7242009-09-03 00:05:05 -03001193 * aren't announced by acpi. So, we need to use a legacy scan probing
1194 * to detect them
1195 */
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001196 while (table && table->descr) {
1197 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
1198 if (unlikely(!pdev)) {
1199 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1200 pcibios_scan_specific_bus(255-i);
1201 }
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001202 pci_dev_put(pdev);
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001203 table++;
Keith Manntheybc2d7242009-09-03 00:05:05 -03001204 }
1205}
1206
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001207static unsigned i7core_pci_lastbus(void)
1208{
1209 int last_bus = 0, bus;
1210 struct pci_bus *b = NULL;
1211
1212 while ((b = pci_find_next_bus(b)) != NULL) {
1213 bus = b->number;
1214 debugf0("Found bus %d\n", bus);
1215 if (bus > last_bus)
1216 last_bus = bus;
1217 }
1218
1219 debugf0("Last bus %d\n", last_bus);
1220
1221 return last_bus;
1222}
1223
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001224/*
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001225 * i7core_get_all_devices Find and perform 'get' operation on the MCH's
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001226 * device/functions we want to reference for this driver
1227 *
1228 * Need to 'get' device 16 func 1 and func 2
1229 */
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001230static int i7core_get_onedevice(struct pci_dev **prev,
1231 const struct pci_id_table *table,
1232 const unsigned devno,
1233 const unsigned last_bus)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001234{
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001235 struct i7core_dev *i7core_dev;
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001236 const struct pci_id_descr *dev_descr = &table->descr[devno];
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001237
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001238 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -03001239 u8 bus = 0;
1240 u8 socket = 0;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001241
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001242 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001243 dev_descr->dev_id, *prev);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001244
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -03001245 /*
1246 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
1247 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1248 * to probe for the alternate address in case of failure
1249 */
1250 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
1251 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1252 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
1253
1254 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
1255 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1256 PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
1257 *prev);
1258
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001259 if (!pdev) {
1260 if (*prev) {
1261 *prev = pdev;
1262 return 0;
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -03001263 }
1264
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001265 if (dev_descr->optional)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001266 return 0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001267
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001268 if (devno == 0)
1269 return -ENODEV;
1270
Daniel J Bluemanab089372010-07-23 23:16:52 +01001271 i7core_printk(KERN_INFO,
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001272 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001273 dev_descr->dev, dev_descr->func,
1274 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001275
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001276 /* End of list, leave */
1277 return -ENODEV;
1278 }
1279 bus = pdev->bus->number;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001280
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001281 socket = last_bus - bus;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001282
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001283 i7core_dev = get_i7core_dev(socket);
1284 if (!i7core_dev) {
Hidetoshi Seto848b2f72010-08-20 04:24:44 -03001285 i7core_dev = alloc_i7core_dev(socket, table);
Hidetoshi Seto28966372010-08-20 04:28:51 -03001286 if (!i7core_dev) {
1287 pci_dev_put(pdev);
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001288 return -ENOMEM;
Hidetoshi Seto28966372010-08-20 04:28:51 -03001289 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001290 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001291
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001292 if (i7core_dev->pdev[devno]) {
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001293 i7core_printk(KERN_ERR,
1294 "Duplicated device for "
1295 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001296 bus, dev_descr->dev, dev_descr->func,
1297 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001298 pci_dev_put(pdev);
1299 return -ENODEV;
1300 }
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001301
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001302 i7core_dev->pdev[devno] = pdev;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001303
1304 /* Sanity check */
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001305 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1306 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001307 i7core_printk(KERN_ERR,
1308 "Device PCI ID %04x:%04x "
1309 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001310 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001311 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001312 bus, dev_descr->dev, dev_descr->func);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001313 return -ENODEV;
1314 }
1315
1316 /* Be sure that the device is enabled */
1317 if (unlikely(pci_enable_device(pdev) < 0)) {
1318 i7core_printk(KERN_ERR,
1319 "Couldn't enable "
1320 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001321 bus, dev_descr->dev, dev_descr->func,
1322 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001323 return -ENODEV;
1324 }
1325
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03001326 debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001327 socket, bus, dev_descr->dev,
1328 dev_descr->func,
1329 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001330
Mauro Carvalho Chehaba3e15412010-08-21 08:52:41 -03001331 /*
1332 * As stated on drivers/pci/search.c, the reference count for
1333 * @from is always decremented if it is not %NULL. So, as we need
1334 * to get all devices up to null, we need to do a get for the device
1335 */
1336 pci_dev_get(pdev);
1337
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001338 *prev = pdev;
1339
1340 return 0;
1341}
1342
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001343static int i7core_get_all_devices(void)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001344{
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001345 int i, rc, last_bus;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001346 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001347 const struct pci_id_table *table = pci_dev_table;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001348
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001349 last_bus = i7core_pci_lastbus();
1350
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001351 while (table && table->descr) {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001352 for (i = 0; i < table->n_devs; i++) {
1353 pdev = NULL;
1354 do {
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001355 rc = i7core_get_onedevice(&pdev, table, i,
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001356 last_bus);
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001357 if (rc < 0) {
1358 if (i == 0) {
1359 i = table->n_devs;
1360 break;
1361 }
1362 i7core_put_all_devices();
1363 return -ENODEV;
1364 }
1365 } while (pdev);
1366 }
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001367 table++;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001368 }
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001369
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001370 return 0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001371}
1372
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001373static int mci_bind_devs(struct mem_ctl_info *mci,
1374 struct i7core_dev *i7core_dev)
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001375{
1376 struct i7core_pvt *pvt = mci->pvt_info;
1377 struct pci_dev *pdev;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001378 int i, func, slot;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001379 char *family;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001380
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001381 pvt->is_registered = false;
1382 pvt->enable_scrub = false;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001383 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001384 pdev = i7core_dev->pdev[i];
1385 if (!pdev)
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001386 continue;
1387
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001388 func = PCI_FUNC(pdev->devfn);
1389 slot = PCI_SLOT(pdev->devfn);
1390 if (slot == 3) {
1391 if (unlikely(func > MAX_MCR_FUNC))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001392 goto error;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001393 pvt->pci_mcr[func] = pdev;
1394 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1395 if (unlikely(func > MAX_CHAN_FUNC))
1396 goto error;
1397 pvt->pci_ch[slot - 4][func] = pdev;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001398 } else if (!slot && !func) {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001399 pvt->pci_noncore = pdev;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001400
1401 /* Detect the processor family */
1402 switch (pdev->device) {
1403 case PCI_DEVICE_ID_INTEL_I7_NONCORE:
1404 family = "Xeon 35xx/ i7core";
1405 pvt->enable_scrub = false;
1406 break;
1407 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT:
1408 family = "i7-800/i5-700";
1409 pvt->enable_scrub = false;
1410 break;
1411 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE:
1412 family = "Xeon 34xx";
1413 pvt->enable_scrub = false;
1414 break;
1415 case PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT:
1416 family = "Xeon 55xx";
1417 pvt->enable_scrub = true;
1418 break;
1419 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2:
1420 family = "Xeon 56xx / i7-900";
1421 pvt->enable_scrub = true;
1422 break;
1423 default:
1424 family = "unknown";
1425 pvt->enable_scrub = false;
1426 }
1427 debugf0("Detected a processor type %s\n", family);
1428 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001429 goto error;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001430
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001431 debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
1432 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1433 pdev, i7core_dev->socket);
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -03001434
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001435 if (PCI_SLOT(pdev->devfn) == 3 &&
1436 PCI_FUNC(pdev->devfn) == 2)
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001437 pvt->is_registered = true;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001438 }
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -03001439
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001440 return 0;
1441
1442error:
1443 i7core_printk(KERN_ERR, "Device %d, function %d "
1444 "is out of the expected range\n",
1445 slot, func);
1446 return -EINVAL;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001447}
1448
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001449/****************************************************************************
1450 Error check routines
1451 ****************************************************************************/
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001452static void i7core_rdimm_update_errcount(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001453 const int chan,
1454 const int dimm,
1455 const int add)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001456{
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001457 int i;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001458
1459 for (i = 0; i < add; i++) {
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001460 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
1461 chan, dimm, -1, "error", "", NULL);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001462 }
1463}
1464
1465static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001466 const int chan,
1467 const int new0,
1468 const int new1,
1469 const int new2)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001470{
1471 struct i7core_pvt *pvt = mci->pvt_info;
1472 int add0 = 0, add1 = 0, add2 = 0;
1473 /* Updates CE counters if it is not the first time here */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001474 if (pvt->ce_count_available) {
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001475 /* Updates CE counters */
1476
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001477 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1478 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1479 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001480
1481 if (add2 < 0)
1482 add2 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001483 pvt->rdimm_ce_count[chan][2] += add2;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001484
1485 if (add1 < 0)
1486 add1 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001487 pvt->rdimm_ce_count[chan][1] += add1;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001488
1489 if (add0 < 0)
1490 add0 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001491 pvt->rdimm_ce_count[chan][0] += add0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001492 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001493 pvt->ce_count_available = 1;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001494
1495 /* Store the new values */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001496 pvt->rdimm_last_ce_count[chan][2] = new2;
1497 pvt->rdimm_last_ce_count[chan][1] = new1;
1498 pvt->rdimm_last_ce_count[chan][0] = new0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001499
1500 /*updated the edac core */
1501 if (add0 != 0)
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001502 i7core_rdimm_update_errcount(mci, chan, 0, add0);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001503 if (add1 != 0)
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001504 i7core_rdimm_update_errcount(mci, chan, 1, add1);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001505 if (add2 != 0)
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001506 i7core_rdimm_update_errcount(mci, chan, 2, add2);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001507
1508}
1509
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001510static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001511{
1512 struct i7core_pvt *pvt = mci->pvt_info;
1513 u32 rcv[3][2];
1514 int i, new0, new1, new2;
1515
1516 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001517 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001518 &rcv[0][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001519 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001520 &rcv[0][1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001521 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001522 &rcv[1][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001523 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001524 &rcv[1][1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001525 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001526 &rcv[2][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001527 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001528 &rcv[2][1]);
1529 for (i = 0 ; i < 3; i++) {
1530 debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1531 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
1532 /*if the channel has 3 dimms*/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001533 if (pvt->channel[i].dimms > 2) {
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001534 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1535 new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1536 new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1537 } else {
1538 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1539 DIMM_BOT_COR_ERR(rcv[i][0]);
1540 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1541 DIMM_BOT_COR_ERR(rcv[i][1]);
1542 new2 = 0;
1543 }
1544
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001545 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001546 }
1547}
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001548
1549/* This function is based on the device 3 function 4 registers as described on:
1550 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1551 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1552 * also available at:
1553 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1554 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001555static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001556{
1557 struct i7core_pvt *pvt = mci->pvt_info;
1558 u32 rcv1, rcv0;
1559 int new0, new1, new2;
1560
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001561 if (!pvt->pci_mcr[4]) {
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -03001562 debugf0("%s MCR registers not found\n", __func__);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001563 return;
1564 }
1565
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001566 /* Corrected test errors */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001567 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1568 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001569
1570 /* Store the new values */
1571 new2 = DIMM2_COR_ERR(rcv1);
1572 new1 = DIMM1_COR_ERR(rcv0);
1573 new0 = DIMM0_COR_ERR(rcv0);
1574
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001575 /* Updates CE counters if it is not the first time here */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001576 if (pvt->ce_count_available) {
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001577 /* Updates CE counters */
1578 int add0, add1, add2;
1579
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001580 add2 = new2 - pvt->udimm_last_ce_count[2];
1581 add1 = new1 - pvt->udimm_last_ce_count[1];
1582 add0 = new0 - pvt->udimm_last_ce_count[0];
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001583
1584 if (add2 < 0)
1585 add2 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001586 pvt->udimm_ce_count[2] += add2;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001587
1588 if (add1 < 0)
1589 add1 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001590 pvt->udimm_ce_count[1] += add1;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001591
1592 if (add0 < 0)
1593 add0 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001594 pvt->udimm_ce_count[0] += add0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001595
1596 if (add0 | add1 | add2)
1597 i7core_printk(KERN_ERR, "New Corrected error(s): "
1598 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1599 add0, add1, add2);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001600 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001601 pvt->ce_count_available = 1;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001602
1603 /* Store the new values */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001604 pvt->udimm_last_ce_count[2] = new2;
1605 pvt->udimm_last_ce_count[1] = new1;
1606 pvt->udimm_last_ce_count[0] = new0;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001607}
1608
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001609/*
1610 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1611 * Architectures Software Developer’s Manual Volume 3B.
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001612 * Nehalem are defined as family 0x06, model 0x1a
1613 *
1614 * The MCA registers used here are the following ones:
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001615 * struct mce field MCA Register
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001616 * m->status MSR_IA32_MC8_STATUS
1617 * m->addr MSR_IA32_MC8_ADDR
1618 * m->misc MSR_IA32_MC8_MISC
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001619 * In the case of Nehalem, the error information is masked at .status and .misc
1620 * fields
1621 */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001622static void i7core_mce_output_error(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001623 const struct mce *m)
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001624{
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001625 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001626 char *type, *optype, *err, *msg;
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001627 enum hw_event_mc_err_type tp_event;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001628 unsigned long error = m->status & 0x1ff0000l;
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001629 bool uncorrected_error = m->mcgstatus & 1ll << 61;
1630 bool ripv = m->mcgstatus & 1;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001631 u32 optypenum = (m->status >> 4) & 0x07;
Mathias Krause8cf2d232011-08-18 09:17:00 +02001632 u32 core_err_cnt = (m->status >> 38) & 0x7fff;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001633 u32 dimm = (m->misc >> 16) & 0x3;
1634 u32 channel = (m->misc >> 18) & 0x3;
1635 u32 syndrome = m->misc >> 32;
1636 u32 errnum = find_first_bit(&error, 32);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001637
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001638 if (uncorrected_error) {
1639 if (ripv) {
1640 type = "FATAL";
1641 tp_event = HW_EVENT_ERR_FATAL;
1642 } else {
1643 type = "NON_FATAL";
1644 tp_event = HW_EVENT_ERR_UNCORRECTED;
1645 }
1646 } else {
1647 type = "CORRECTED";
1648 tp_event = HW_EVENT_ERR_CORRECTED;
1649 }
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001650
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001651 switch (optypenum) {
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -03001652 case 0:
1653 optype = "generic undef request";
1654 break;
1655 case 1:
1656 optype = "read error";
1657 break;
1658 case 2:
1659 optype = "write error";
1660 break;
1661 case 3:
1662 optype = "addr/cmd error";
1663 break;
1664 case 4:
1665 optype = "scrubbing error";
1666 break;
1667 default:
1668 optype = "reserved";
1669 break;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001670 }
1671
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001672 switch (errnum) {
1673 case 16:
1674 err = "read ECC error";
1675 break;
1676 case 17:
1677 err = "RAS ECC error";
1678 break;
1679 case 18:
1680 err = "write parity error";
1681 break;
1682 case 19:
1683 err = "redundacy loss";
1684 break;
1685 case 20:
1686 err = "reserved";
1687 break;
1688 case 21:
1689 err = "memory range error";
1690 break;
1691 case 22:
1692 err = "RTID out of range";
1693 break;
1694 case 23:
1695 err = "address parity error";
1696 break;
1697 case 24:
1698 err = "byte enable parity error";
1699 break;
1700 default:
1701 err = "unknown";
1702 }
1703
1704 msg = kasprintf(GFP_ATOMIC,
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001705 "addr=0x%08llx cpu=%d count=%d Err=%08llx:%08llx (%s: %s))\n",
1706 (long long) m->addr, m->cpu, core_err_cnt,
1707 (long long)m->status, (long long)m->misc, optype, err);
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001708
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001709 /*
1710 * Call the helper to output message
1711 * FIXME: what to do if core_err_cnt > 1? Currently, it generates
1712 * only one event
1713 */
1714 if (uncorrected_error || !pvt->is_registered)
1715 edac_mc_handle_error(tp_event, mci,
1716 m->addr >> PAGE_SHIFT,
1717 m->addr & ~PAGE_MASK,
1718 syndrome,
1719 channel, dimm, -1,
1720 err, msg, m);
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001721
1722 kfree(msg);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001723}
1724
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001725/*
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001726 * i7core_check_error Retrieve and process errors reported by the
1727 * hardware. Called by the Core module.
1728 */
1729static void i7core_check_error(struct mem_ctl_info *mci)
1730{
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001731 struct i7core_pvt *pvt = mci->pvt_info;
1732 int i;
1733 unsigned count = 0;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001734 struct mce *m;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001735
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001736 /*
1737 * MCE first step: Copy all mce errors into a temporary buffer
1738 * We use a double buffering here, to reduce the risk of
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001739 * losing an error.
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001740 */
1741 smp_rmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001742 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1743 % MCE_LOG_LEN;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001744 if (!count)
Vernon Mauery8a311e12010-04-16 19:40:19 -03001745 goto check_ce_error;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001746
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001747 m = pvt->mce_outentry;
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001748 if (pvt->mce_in + count > MCE_LOG_LEN) {
1749 unsigned l = MCE_LOG_LEN - pvt->mce_in;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001750
1751 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1752 smp_wmb();
1753 pvt->mce_in = 0;
1754 count -= l;
1755 m += l;
1756 }
1757 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1758 smp_wmb();
1759 pvt->mce_in += count;
1760
1761 smp_rmb();
1762 if (pvt->mce_overrun) {
1763 i7core_printk(KERN_ERR, "Lost %d memory errors\n",
1764 pvt->mce_overrun);
1765 smp_wmb();
1766 pvt->mce_overrun = 0;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001767 }
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001768
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001769 /*
1770 * MCE second step: parse errors and display
1771 */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001772 for (i = 0; i < count; i++)
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001773 i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001774
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001775 /*
1776 * Now, let's increment CE error counts
1777 */
Vernon Mauery8a311e12010-04-16 19:40:19 -03001778check_ce_error:
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001779 if (!pvt->is_registered)
1780 i7core_udimm_check_mc_ecc_err(mci);
1781 else
1782 i7core_rdimm_check_mc_ecc_err(mci);
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001783}
1784
1785/*
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001786 * i7core_mce_check_error Replicates mcelog routine to get errors
1787 * This routine simply queues mcelog errors, and
1788 * return. The error itself should be handled later
1789 * by i7core_check_error.
Mauro Carvalho Chehab6e103be2009-10-05 09:40:09 -03001790 * WARNING: As this routine should be called at NMI time, extra care should
1791 * be taken to avoid deadlocks, and to be as fast as possible.
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001792 */
Borislav Petkov4140c542011-07-18 11:24:46 -03001793static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val,
1794 void *data)
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001795{
Borislav Petkov4140c542011-07-18 11:24:46 -03001796 struct mce *mce = (struct mce *)data;
1797 struct i7core_dev *i7_dev;
1798 struct mem_ctl_info *mci;
1799 struct i7core_pvt *pvt;
1800
1801 i7_dev = get_i7core_dev(mce->socketid);
1802 if (!i7_dev)
1803 return NOTIFY_BAD;
1804
1805 mci = i7_dev->mci;
1806 pvt = mci->pvt_info;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001807
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001808 /*
1809 * Just let mcelog handle it if the error is
1810 * outside the memory controller
1811 */
1812 if (((mce->status & 0xffff) >> 7) != 1)
Borislav Petkov4140c542011-07-18 11:24:46 -03001813 return NOTIFY_DONE;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001814
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001815 /* Bank 8 registers are the only ones that we know how to handle */
1816 if (mce->bank != 8)
Borislav Petkov4140c542011-07-18 11:24:46 -03001817 return NOTIFY_DONE;
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001818
Randy Dunlap3b918c12009-11-08 01:36:40 -02001819#ifdef CONFIG_SMP
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001820 /* Only handle if it is the right mc controller */
Thomas Renninger50340862011-06-22 05:40:06 -03001821 if (mce->socketid != pvt->i7core_dev->socket)
Borislav Petkov4140c542011-07-18 11:24:46 -03001822 return NOTIFY_DONE;
Randy Dunlap3b918c12009-11-08 01:36:40 -02001823#endif
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001824
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001825 smp_rmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001826 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001827 smp_wmb();
1828 pvt->mce_overrun++;
Borislav Petkov4140c542011-07-18 11:24:46 -03001829 return NOTIFY_DONE;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001830 }
Mauro Carvalho Chehab6e103be2009-10-05 09:40:09 -03001831
1832 /* Copy memory error at the ringbuffer */
1833 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001834 smp_wmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001835 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001836
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001837 /* Handle fatal errors immediately */
1838 if (mce->mcgstatus & 1)
1839 i7core_check_error(mci);
1840
David Sterbae7bf0682010-12-27 16:51:15 +01001841 /* Advise mcelog that the errors were handled */
Borislav Petkov4140c542011-07-18 11:24:46 -03001842 return NOTIFY_STOP;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001843}
1844
Borislav Petkov4140c542011-07-18 11:24:46 -03001845static struct notifier_block i7_mce_dec = {
1846 .notifier_call = i7core_mce_check_error,
1847};
1848
Nils Carlson535e9c72011-08-08 06:21:26 -03001849struct memdev_dmi_entry {
1850 u8 type;
1851 u8 length;
1852 u16 handle;
1853 u16 phys_mem_array_handle;
1854 u16 mem_err_info_handle;
1855 u16 total_width;
1856 u16 data_width;
1857 u16 size;
1858 u8 form;
1859 u8 device_set;
1860 u8 device_locator;
1861 u8 bank_locator;
1862 u8 memory_type;
1863 u16 type_detail;
1864 u16 speed;
1865 u8 manufacturer;
1866 u8 serial_number;
1867 u8 asset_tag;
1868 u8 part_number;
1869 u8 attributes;
1870 u32 extended_size;
1871 u16 conf_mem_clk_speed;
1872} __attribute__((__packed__));
1873
1874
1875/*
1876 * Decode the DRAM Clock Frequency, be paranoid, make sure that all
1877 * memory devices show the same speed, and if they don't then consider
1878 * all speeds to be invalid.
1879 */
1880static void decode_dclk(const struct dmi_header *dh, void *_dclk_freq)
1881{
1882 int *dclk_freq = _dclk_freq;
1883 u16 dmi_mem_clk_speed;
1884
1885 if (*dclk_freq == -1)
1886 return;
1887
1888 if (dh->type == DMI_ENTRY_MEM_DEVICE) {
1889 struct memdev_dmi_entry *memdev_dmi_entry =
1890 (struct memdev_dmi_entry *)dh;
1891 unsigned long conf_mem_clk_speed_offset =
1892 (unsigned long)&memdev_dmi_entry->conf_mem_clk_speed -
1893 (unsigned long)&memdev_dmi_entry->type;
1894 unsigned long speed_offset =
1895 (unsigned long)&memdev_dmi_entry->speed -
1896 (unsigned long)&memdev_dmi_entry->type;
1897
1898 /* Check that a DIMM is present */
1899 if (memdev_dmi_entry->size == 0)
1900 return;
1901
1902 /*
1903 * Pick the configured speed if it's available, otherwise
1904 * pick the DIMM speed, or we don't have a speed.
1905 */
1906 if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) {
1907 dmi_mem_clk_speed =
1908 memdev_dmi_entry->conf_mem_clk_speed;
1909 } else if (memdev_dmi_entry->length > speed_offset) {
1910 dmi_mem_clk_speed = memdev_dmi_entry->speed;
1911 } else {
1912 *dclk_freq = -1;
1913 return;
1914 }
1915
1916 if (*dclk_freq == 0) {
1917 /* First pass, speed was 0 */
1918 if (dmi_mem_clk_speed > 0) {
1919 /* Set speed if a valid speed is read */
1920 *dclk_freq = dmi_mem_clk_speed;
1921 } else {
1922 /* Otherwise we don't have a valid speed */
1923 *dclk_freq = -1;
1924 }
1925 } else if (*dclk_freq > 0 &&
1926 *dclk_freq != dmi_mem_clk_speed) {
1927 /*
1928 * If we have a speed, check that all DIMMS are the same
1929 * speed, otherwise set the speed as invalid.
1930 */
1931 *dclk_freq = -1;
1932 }
1933 }
1934}
1935
1936/*
1937 * The default DCLK frequency is used as a fallback if we
1938 * fail to find anything reliable in the DMI. The value
1939 * is taken straight from the datasheet.
1940 */
1941#define DEFAULT_DCLK_FREQ 800
1942
1943static int get_dclk_freq(void)
1944{
1945 int dclk_freq = 0;
1946
1947 dmi_walk(decode_dclk, (void *)&dclk_freq);
1948
1949 if (dclk_freq < 1)
1950 return DEFAULT_DCLK_FREQ;
1951
1952 return dclk_freq;
1953}
1954
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03001955/*
1956 * set_sdram_scrub_rate This routine sets byte/sec bandwidth scrub rate
1957 * to hardware according to SCRUBINTERVAL formula
1958 * found in datasheet.
1959 */
1960static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
1961{
1962 struct i7core_pvt *pvt = mci->pvt_info;
1963 struct pci_dev *pdev;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03001964 u32 dw_scrub;
1965 u32 dw_ssr;
1966
1967 /* Get data from the MC register, function 2 */
1968 pdev = pvt->pci_mcr[2];
1969 if (!pdev)
1970 return -ENODEV;
1971
1972 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &dw_scrub);
1973
1974 if (new_bw == 0) {
1975 /* Prepare to disable petrol scrub */
1976 dw_scrub &= ~STARTSCRUB;
1977 /* Stop the patrol scrub engine */
Nils Carlson535e9c72011-08-08 06:21:26 -03001978 write_and_test(pdev, MC_SCRUB_CONTROL,
1979 dw_scrub & ~SCRUBINTERVAL_MASK);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03001980
1981 /* Get current status of scrub rate and set bit to disable */
1982 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
1983 dw_ssr &= ~SSR_MODE_MASK;
1984 dw_ssr |= SSR_MODE_DISABLE;
1985 } else {
Nils Carlson535e9c72011-08-08 06:21:26 -03001986 const int cache_line_size = 64;
1987 const u32 freq_dclk_mhz = pvt->dclk_freq;
1988 unsigned long long scrub_interval;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03001989 /*
1990 * Translate the desired scrub rate to a register value and
Nils Carlson535e9c72011-08-08 06:21:26 -03001991 * program the corresponding register value.
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03001992 */
Nils Carlson535e9c72011-08-08 06:21:26 -03001993 scrub_interval = (unsigned long long)freq_dclk_mhz *
Sedat Dilek4fad8092011-09-21 23:44:52 -03001994 cache_line_size * 1000000;
1995 do_div(scrub_interval, new_bw);
Nils Carlson535e9c72011-08-08 06:21:26 -03001996
1997 if (!scrub_interval || scrub_interval > SCRUBINTERVAL_MASK)
1998 return -EINVAL;
1999
2000 dw_scrub = SCRUBINTERVAL_MASK & scrub_interval;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002001
2002 /* Start the patrol scrub engine */
2003 pci_write_config_dword(pdev, MC_SCRUB_CONTROL,
2004 STARTSCRUB | dw_scrub);
2005
2006 /* Get current status of scrub rate and set bit to enable */
2007 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
2008 dw_ssr &= ~SSR_MODE_MASK;
2009 dw_ssr |= SSR_MODE_ENABLE;
2010 }
2011 /* Disable or enable scrubbing */
2012 pci_write_config_dword(pdev, MC_SSRCONTROL, dw_ssr);
2013
2014 return new_bw;
2015}
2016
2017/*
2018 * get_sdram_scrub_rate This routine convert current scrub rate value
2019 * into byte/sec bandwidth accourding to
2020 * SCRUBINTERVAL formula found in datasheet.
2021 */
2022static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
2023{
2024 struct i7core_pvt *pvt = mci->pvt_info;
2025 struct pci_dev *pdev;
2026 const u32 cache_line_size = 64;
Nils Carlson535e9c72011-08-08 06:21:26 -03002027 const u32 freq_dclk_mhz = pvt->dclk_freq;
2028 unsigned long long scrub_rate;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002029 u32 scrubval;
2030
2031 /* Get data from the MC register, function 2 */
2032 pdev = pvt->pci_mcr[2];
2033 if (!pdev)
2034 return -ENODEV;
2035
2036 /* Get current scrub control data */
2037 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &scrubval);
2038
2039 /* Mask highest 8-bits to 0 */
Nils Carlson535e9c72011-08-08 06:21:26 -03002040 scrubval &= SCRUBINTERVAL_MASK;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002041 if (!scrubval)
2042 return 0;
2043
2044 /* Calculate scrub rate value into byte/sec bandwidth */
Nils Carlson535e9c72011-08-08 06:21:26 -03002045 scrub_rate = (unsigned long long)freq_dclk_mhz *
Sedat Dilek4fad8092011-09-21 23:44:52 -03002046 1000000 * cache_line_size;
2047 do_div(scrub_rate, scrubval);
Nils Carlson535e9c72011-08-08 06:21:26 -03002048 return (int)scrub_rate;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002049}
2050
2051static void enable_sdram_scrub_setting(struct mem_ctl_info *mci)
2052{
2053 struct i7core_pvt *pvt = mci->pvt_info;
2054 u32 pci_lock;
2055
2056 /* Unlock writes to pci registers */
2057 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2058 pci_lock &= ~0x3;
2059 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2060 pci_lock | MC_CFG_UNLOCK);
2061
2062 mci->set_sdram_scrub_rate = set_sdram_scrub_rate;
2063 mci->get_sdram_scrub_rate = get_sdram_scrub_rate;
2064}
2065
2066static void disable_sdram_scrub_setting(struct mem_ctl_info *mci)
2067{
2068 struct i7core_pvt *pvt = mci->pvt_info;
2069 u32 pci_lock;
2070
2071 /* Lock writes to pci registers */
2072 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2073 pci_lock &= ~0x3;
2074 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2075 pci_lock | MC_CFG_LOCK);
2076}
2077
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002078static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
2079{
2080 pvt->i7core_pci = edac_pci_create_generic_ctl(
2081 &pvt->i7core_dev->pdev[0]->dev,
2082 EDAC_MOD_STR);
2083 if (unlikely(!pvt->i7core_pci))
Mauro Carvalho Chehabf9902f22010-08-21 09:42:05 -03002084 i7core_printk(KERN_WARNING,
2085 "Unable to setup PCI error report via EDAC\n");
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002086}
2087
2088static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
2089{
2090 if (likely(pvt->i7core_pci))
2091 edac_pci_release_generic_ctl(pvt->i7core_pci);
2092 else
2093 i7core_printk(KERN_ERR,
2094 "Couldn't find mem_ctl_info for socket %d\n",
2095 pvt->i7core_dev->socket);
2096 pvt->i7core_pci = NULL;
2097}
2098
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002099static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
2100{
2101 struct mem_ctl_info *mci = i7core_dev->mci;
2102 struct i7core_pvt *pvt;
2103
2104 if (unlikely(!mci || !mci->pvt_info)) {
2105 debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
2106 __func__, &i7core_dev->pdev[0]->dev);
2107
2108 i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
2109 return;
2110 }
2111
2112 pvt = mci->pvt_info;
2113
2114 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
2115 __func__, mci, &i7core_dev->pdev[0]->dev);
2116
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002117 /* Disable scrubrate setting */
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03002118 if (pvt->enable_scrub)
2119 disable_sdram_scrub_setting(mci);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002120
Borislav Petkov3653ada2011-12-04 15:12:09 +01002121 mce_unregister_decode_chain(&i7_mce_dec);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002122
2123 /* Disable EDAC polling */
2124 i7core_pci_ctl_release(pvt);
2125
2126 /* Remove MC sysfs nodes */
2127 edac_mc_del_mc(mci->dev);
2128
2129 debugf1("%s: free mci struct\n", mci->ctl_name);
2130 kfree(mci->ctl_name);
2131 edac_mc_free(mci);
2132 i7core_dev->mci = NULL;
2133}
2134
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002135static int i7core_register_mci(struct i7core_dev *i7core_dev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002136{
2137 struct mem_ctl_info *mci;
2138 struct i7core_pvt *pvt;
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03002139 int rc;
2140 struct edac_mc_layer layers[2];
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002141
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002142 /* allocate a new MC control structure */
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03002143
2144 layers[0].type = EDAC_MC_LAYER_CHANNEL;
2145 layers[0].size = NUM_CHANS;
2146 layers[0].is_virt_csrow = false;
2147 layers[1].type = EDAC_MC_LAYER_SLOT;
2148 layers[1].size = MAX_DIMMS;
2149 layers[1].is_virt_csrow = true;
2150 mci = new_edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers,
2151 sizeof(*pvt));
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002152 if (unlikely(!mci))
2153 return -ENOMEM;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002154
Mauro Carvalho Chehab3cfd0142010-08-10 23:23:46 -03002155 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
2156 __func__, mci, &i7core_dev->pdev[0]->dev);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002157
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002158 pvt = mci->pvt_info;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002159 memset(pvt, 0, sizeof(*pvt));
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -03002160
Mauro Carvalho Chehab6d37d242010-08-20 12:48:26 -03002161 /* Associates i7core_dev and mci for future usage */
2162 pvt->i7core_dev = i7core_dev;
2163 i7core_dev->mci = mci;
2164
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03002165 /*
2166 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
2167 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
2168 * memory channels
2169 */
2170 mci->mtype_cap = MEM_FLAG_DDR3;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002171 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2172 mci->edac_cap = EDAC_FLAG_NONE;
2173 mci->mod_name = "i7core_edac.c";
2174 mci->mod_ver = I7CORE_REVISION;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002175 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
2176 i7core_dev->socket);
2177 mci->dev_name = pci_name(i7core_dev->pdev[0]);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002178 mci->ctl_page_to_phys = NULL;
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03002179
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002180 /* Store pci devices at mci for faster access */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002181 rc = mci_bind_devs(mci, i7core_dev);
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03002182 if (unlikely(rc < 0))
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002183 goto fail0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002184
Hidetoshi Seto59398132010-08-20 04:28:25 -03002185 if (pvt->is_registered)
2186 mci->mc_driver_sysfs_attributes = i7core_sysfs_rdimm_attrs;
2187 else
2188 mci->mc_driver_sysfs_attributes = i7core_sysfs_udimm_attrs;
2189
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002190 /* Get dimm basic config */
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -03002191 get_dimm_config(mci);
Hidetoshi Seto59398132010-08-20 04:28:25 -03002192 /* record ptr to the generic device */
2193 mci->dev = &i7core_dev->pdev[0]->dev;
2194 /* Set the function pointer to an actual operation function */
2195 mci->edac_check = i7core_check_error;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002196
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002197 /* Enable scrubrate setting */
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03002198 if (pvt->enable_scrub)
2199 enable_sdram_scrub_setting(mci);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002200
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002201 /* add this new MC control structure to EDAC's list of MCs */
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002202 if (unlikely(edac_mc_add_mc(mci))) {
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002203 debugf0("MC: " __FILE__
2204 ": %s(): failed edac_mc_add_mc()\n", __func__);
2205 /* FIXME: perhaps some code should go here that disables error
2206 * reporting if we just enabled it
2207 */
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002208
2209 rc = -EINVAL;
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002210 goto fail0;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002211 }
2212
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03002213 /* Default error mask is any memory */
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002214 pvt->inject.channel = 0;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03002215 pvt->inject.dimm = -1;
2216 pvt->inject.rank = -1;
2217 pvt->inject.bank = -1;
2218 pvt->inject.page = -1;
2219 pvt->inject.col = -1;
2220
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002221 /* allocating generic PCI control info */
2222 i7core_pci_ctl_create(pvt);
2223
Nils Carlson535e9c72011-08-08 06:21:26 -03002224 /* DCLK for scrub rate setting */
2225 pvt->dclk_freq = get_dclk_freq();
2226
Borislav Petkov3653ada2011-12-04 15:12:09 +01002227 mce_register_decode_chain(&i7_mce_dec);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002228
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002229 return 0;
2230
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002231fail0:
2232 kfree(mci->ctl_name);
2233 edac_mc_free(mci);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002234 i7core_dev->mci = NULL;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002235 return rc;
2236}
2237
2238/*
2239 * i7core_probe Probe for ONE instance of device to see if it is
2240 * present.
2241 * return:
2242 * 0 for FOUND a device
2243 * < 0 for error code
2244 */
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002245
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002246static int __devinit i7core_probe(struct pci_dev *pdev,
2247 const struct pci_device_id *id)
2248{
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002249 int rc, count = 0;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002250 struct i7core_dev *i7core_dev;
2251
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002252 /* get the pci devices we want to reserve for our use */
2253 mutex_lock(&i7core_edac_lock);
2254
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002255 /*
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03002256 * All memory controllers are allocated at the first pass.
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002257 */
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002258 if (unlikely(probed >= 1)) {
2259 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehab76a7bd82010-10-24 11:36:19 -02002260 return -ENODEV;
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002261 }
2262 probed++;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03002263
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002264 rc = i7core_get_all_devices();
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002265 if (unlikely(rc < 0))
2266 goto fail0;
2267
2268 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002269 count++;
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002270 rc = i7core_register_mci(i7core_dev);
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03002271 if (unlikely(rc < 0))
2272 goto fail1;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03002273 }
2274
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002275 /*
2276 * Nehalem-EX uses a different memory controller. However, as the
2277 * memory controller is not visible on some Nehalem/Nehalem-EP, we
2278 * need to indirectly probe via a X58 PCI device. The same devices
2279 * are found on (some) Nehalem-EX. So, on those machines, the
2280 * probe routine needs to return -ENODEV, as the actual Memory
2281 * Controller registers won't be detected.
2282 */
2283 if (!count) {
2284 rc = -ENODEV;
2285 goto fail1;
2286 }
2287
2288 i7core_printk(KERN_INFO,
2289 "Driver loaded, %d memory controller(s) found.\n",
2290 count);
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03002291
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002292 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002293 return 0;
2294
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002295fail1:
Mauro Carvalho Chehab88ef5ea2010-08-20 15:39:38 -03002296 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2297 i7core_unregister_mci(i7core_dev);
2298
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03002299 i7core_put_all_devices();
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002300fail0:
2301 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002302 return rc;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002303}
2304
2305/*
2306 * i7core_remove destructor for one instance of device
2307 *
2308 */
2309static void __devexit i7core_remove(struct pci_dev *pdev)
2310{
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002311 struct i7core_dev *i7core_dev;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002312
2313 debugf0(__FILE__ ": %s()\n", __func__);
2314
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002315 /*
2316 * we have a trouble here: pdev value for removal will be wrong, since
2317 * it will point to the X58 register used to detect that the machine
2318 * is a Nehalem or upper design. However, due to the way several PCI
2319 * devices are grouped together to provide MC functionality, we need
2320 * to use a different method for releasing the devices
2321 */
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03002322
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002323 mutex_lock(&i7core_edac_lock);
Hidetoshi Seto71fe0172010-08-20 04:29:47 -03002324
2325 if (unlikely(!probed)) {
2326 mutex_unlock(&i7core_edac_lock);
2327 return;
2328 }
2329
Mauro Carvalho Chehab88ef5ea2010-08-20 15:39:38 -03002330 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2331 i7core_unregister_mci(i7core_dev);
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002332
2333 /* Release PCI resources */
2334 i7core_put_all_devices();
2335
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002336 probed--;
2337
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002338 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002339}
2340
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002341MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
2342
2343/*
2344 * i7core_driver pci_driver structure for this module
2345 *
2346 */
2347static struct pci_driver i7core_driver = {
2348 .name = "i7core_edac",
2349 .probe = i7core_probe,
2350 .remove = __devexit_p(i7core_remove),
2351 .id_table = i7core_pci_tbl,
2352};
2353
2354/*
2355 * i7core_init Module entry function
2356 * Try to initialize this module for its devices
2357 */
2358static int __init i7core_init(void)
2359{
2360 int pci_rc;
2361
2362 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2363
2364 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2365 opstate_init();
2366
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -03002367 if (use_pci_fixup)
2368 i7core_xeon_pci_fixup(pci_dev_table);
Keith Manntheybc2d7242009-09-03 00:05:05 -03002369
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002370 pci_rc = pci_register_driver(&i7core_driver);
2371
Mauro Carvalho Chehab3ef288a2009-09-02 23:43:33 -03002372 if (pci_rc >= 0)
2373 return 0;
2374
2375 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
2376 pci_rc);
2377
2378 return pci_rc;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002379}
2380
2381/*
2382 * i7core_exit() Module exit function
2383 * Unregister the driver
2384 */
2385static void __exit i7core_exit(void)
2386{
2387 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2388 pci_unregister_driver(&i7core_driver);
2389}
2390
2391module_init(i7core_init);
2392module_exit(i7core_exit);
2393
2394MODULE_LICENSE("GPL");
2395MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2396MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2397MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
2398 I7CORE_REVISION);
2399
2400module_param(edac_op_state, int, 0444);
2401MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");