Blame - drivers/gpu/drm/radeon/rv770d.h - kernel/msm-4.19

Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

/*

*

* Permission is hereby granted, free of charge, to any person obtaining a

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* copy of this software and associated documentation files (the "Software"),

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* to deal in the Software without restriction, including without limitation

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* the rights to use, copy, modify, merge, publish, distribute, sublicense,

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* and/or sell copies of the Software, and to permit persons to whom the

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* Software is furnished to do so, subject to the following conditions:

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*

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* The above copyright notice and this permission notice shall be included in

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* all copies or substantial portions of the Software.

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*

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

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* OTHER DEALINGS IN THE SOFTWARE.

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*

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* Authors: Dave Airlie

* Alex Deucher

* Jerome Glisse

*/

#ifndef RV770_H

#define RV770_H

#define R7XX_MAX_SH_GPRS 256

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#define R7XX_MAX_TEMP_GPRS 16

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#define R7XX_MAX_SH_THREADS 256

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#define R7XX_MAX_SH_STACK_ENTRIES 4096

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#define R7XX_MAX_BACKENDS 8

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#define R7XX_MAX_BACKENDS_MASK 0xff

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#define R7XX_MAX_SIMDS 16

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#define R7XX_MAX_SIMDS_MASK 0xffff

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#define R7XX_MAX_PIPES 8

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#define R7XX_MAX_PIPES_MASK 0xff

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2013-04-08 12:41:35 +0200

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/* discrete uvd clocks */

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#define CG_UPLL_FUNC_CNTL 0x718

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# define UPLL_RESET_MASK 0x00000001

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# define UPLL_SLEEP_MASK 0x00000002

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# define UPLL_BYPASS_EN_MASK 0x00000004

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# define UPLL_CTLREQ_MASK 0x00000008

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# define UPLL_REF_DIV(x) ((x) << 16)

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2013-04-29 10:20:23 +0200

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# define UPLL_REF_DIV_MASK 0x003F0000

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# define UPLL_CTLACK_MASK 0x40000000

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# define UPLL_CTLACK2_MASK 0x80000000

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#define CG_UPLL_FUNC_CNTL_2 0x71c

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# define UPLL_SW_HILEN(x) ((x) << 0)

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# define UPLL_SW_LOLEN(x) ((x) << 4)

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# define UPLL_SW_HILEN2(x) ((x) << 8)

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# define UPLL_SW_LOLEN2(x) ((x) << 12)

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# define UPLL_SW_MASK 0x0000FFFF

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# define VCLK_SRC_SEL(x) ((x) << 20)

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# define VCLK_SRC_SEL_MASK 0x01F00000

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# define DCLK_SRC_SEL(x) ((x) << 25)

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# define DCLK_SRC_SEL_MASK 0x3E000000

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#define CG_UPLL_FUNC_CNTL_3 0x720

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# define UPLL_FB_DIV(x) ((x) << 0)

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# define UPLL_FB_DIV_MASK 0x01FFFFFF

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Alex Deucher

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2013-06-26 00:11:19 -0400

[diff] [blame]

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/* pm registers */

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#define SMC_SRAM_ADDR 0x200

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#define SMC_SRAM_AUTO_INC_DIS (1 << 16)

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#define SMC_SRAM_DATA 0x204

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#define SMC_IO 0x208

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#define SMC_RST_N (1 << 0)

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#define SMC_STOP_MODE (1 << 2)

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#define SMC_CLK_EN (1 << 11)

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#define SMC_MSG 0x20c

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#define HOST_SMC_MSG(x) ((x) << 0)

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#define HOST_SMC_MSG_MASK (0xff << 0)

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#define HOST_SMC_MSG_SHIFT 0

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#define HOST_SMC_RESP(x) ((x) << 8)

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#define HOST_SMC_RESP_MASK (0xff << 8)

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#define HOST_SMC_RESP_SHIFT 8

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#define SMC_HOST_MSG(x) ((x) << 16)

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#define SMC_HOST_MSG_MASK (0xff << 16)

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#define SMC_HOST_MSG_SHIFT 16

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#define SMC_HOST_RESP(x) ((x) << 24)

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#define SMC_HOST_RESP_MASK (0xff << 24)

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#define SMC_HOST_RESP_SHIFT 24

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#define SMC_ISR_FFD8_FFDB 0x218

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#define CG_SPLL_FUNC_CNTL 0x600

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#define SPLL_RESET (1 << 0)

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#define SPLL_SLEEP (1 << 1)

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#define SPLL_DIVEN (1 << 2)

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#define SPLL_BYPASS_EN (1 << 3)

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#define SPLL_REF_DIV(x) ((x) << 4)

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#define SPLL_REF_DIV_MASK (0x3f << 4)

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#define SPLL_HILEN(x) ((x) << 12)

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#define SPLL_HILEN_MASK (0xf << 12)

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#define SPLL_LOLEN(x) ((x) << 16)

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#define SPLL_LOLEN_MASK (0xf << 16)

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#define CG_SPLL_FUNC_CNTL_2 0x604

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#define SCLK_MUX_SEL(x) ((x) << 0)

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#define SCLK_MUX_SEL_MASK (0x1ff << 0)

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#define CG_SPLL_FUNC_CNTL_3 0x608

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#define SPLL_FB_DIV(x) ((x) << 0)

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#define SPLL_FB_DIV_MASK (0x3ffffff << 0)

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#define SPLL_DITHEN (1 << 28)

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#define SPLL_CNTL_MODE 0x610

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#define SPLL_DIV_SYNC (1 << 5)

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#define MPLL_AD_FUNC_CNTL 0x624

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#define CLKF(x) ((x) << 0)

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#define CLKF_MASK (0x7f << 0)

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#define CLKR(x) ((x) << 7)

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#define CLKR_MASK (0x1f << 7)

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#define CLKFRAC(x) ((x) << 12)

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#define CLKFRAC_MASK (0x1f << 12)

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#define YCLK_POST_DIV(x) ((x) << 17)

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#define YCLK_POST_DIV_MASK (3 << 17)

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#define IBIAS(x) ((x) << 20)

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#define IBIAS_MASK (0x3ff << 20)

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#define RESET (1 << 30)

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#define PDNB (1 << 31)

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#define MPLL_AD_FUNC_CNTL_2 0x628

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#define BYPASS (1 << 19)

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#define BIAS_GEN_PDNB (1 << 24)

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#define RESET_EN (1 << 25)

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#define VCO_MODE (1 << 29)

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#define MPLL_DQ_FUNC_CNTL 0x62c

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#define MPLL_DQ_FUNC_CNTL_2 0x630

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#define GENERAL_PWRMGT 0x63c

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# define GLOBAL_PWRMGT_EN (1 << 0)

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# define STATIC_PM_EN (1 << 1)

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# define THERMAL_PROTECTION_DIS (1 << 2)

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# define THERMAL_PROTECTION_TYPE (1 << 3)

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# define ENABLE_GEN2PCIE (1 << 4)

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# define ENABLE_GEN2XSP (1 << 5)

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# define SW_SMIO_INDEX(x) ((x) << 6)

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# define SW_SMIO_INDEX_MASK (3 << 6)

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# define SW_SMIO_INDEX_SHIFT 6

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# define LOW_VOLT_D2_ACPI (1 << 8)

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# define LOW_VOLT_D3_ACPI (1 << 9)

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# define VOLT_PWRMGT_EN (1 << 10)

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# define BACKBIAS_PAD_EN (1 << 18)

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# define BACKBIAS_VALUE (1 << 19)

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# define DYN_SPREAD_SPECTRUM_EN (1 << 23)

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# define AC_DC_SW (1 << 24)

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#define CG_TPC 0x640

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#define SCLK_PWRMGT_CNTL 0x644

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# define SCLK_PWRMGT_OFF (1 << 0)

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# define SCLK_LOW_D1 (1 << 1)

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# define FIR_RESET (1 << 4)

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# define FIR_FORCE_TREND_SEL (1 << 5)

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# define FIR_TREND_MODE (1 << 6)

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# define DYN_GFX_CLK_OFF_EN (1 << 7)

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# define GFX_CLK_FORCE_ON (1 << 8)

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# define GFX_CLK_REQUEST_OFF (1 << 9)

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# define GFX_CLK_FORCE_OFF (1 << 10)

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# define GFX_CLK_OFF_ACPI_D1 (1 << 11)

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# define GFX_CLK_OFF_ACPI_D2 (1 << 12)

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# define GFX_CLK_OFF_ACPI_D3 (1 << 13)

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#define MCLK_PWRMGT_CNTL 0x648

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# define DLL_SPEED(x) ((x) << 0)

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# define DLL_SPEED_MASK (0x1f << 0)

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# define MPLL_PWRMGT_OFF (1 << 5)

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# define DLL_READY (1 << 6)

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# define MC_INT_CNTL (1 << 7)

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# define MRDCKA0_SLEEP (1 << 8)

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# define MRDCKA1_SLEEP (1 << 9)

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# define MRDCKB0_SLEEP (1 << 10)

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# define MRDCKB1_SLEEP (1 << 11)

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# define MRDCKC0_SLEEP (1 << 12)

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# define MRDCKC1_SLEEP (1 << 13)

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# define MRDCKD0_SLEEP (1 << 14)

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# define MRDCKD1_SLEEP (1 << 15)

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# define MRDCKA0_RESET (1 << 16)

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# define MRDCKA1_RESET (1 << 17)

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# define MRDCKB0_RESET (1 << 18)

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# define MRDCKB1_RESET (1 << 19)

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# define MRDCKC0_RESET (1 << 20)

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# define MRDCKC1_RESET (1 << 21)

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# define MRDCKD0_RESET (1 << 22)

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# define MRDCKD1_RESET (1 << 23)

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# define DLL_READY_READ (1 << 24)

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# define USE_DISPLAY_GAP (1 << 25)

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# define USE_DISPLAY_URGENT_NORMAL (1 << 26)

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# define MPLL_TURNOFF_D2 (1 << 28)

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#define DLL_CNTL 0x64c

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# define MRDCKA0_BYPASS (1 << 24)

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# define MRDCKA1_BYPASS (1 << 25)

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# define MRDCKB0_BYPASS (1 << 26)

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# define MRDCKB1_BYPASS (1 << 27)

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# define MRDCKC0_BYPASS (1 << 28)

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# define MRDCKC1_BYPASS (1 << 29)

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# define MRDCKD0_BYPASS (1 << 30)

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# define MRDCKD1_BYPASS (1 << 31)

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#define MPLL_TIME 0x654

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# define MPLL_LOCK_TIME(x) ((x) << 0)

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# define MPLL_LOCK_TIME_MASK (0xffff << 0)

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# define MPLL_RESET_TIME(x) ((x) << 16)

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# define MPLL_RESET_TIME_MASK (0xffff << 16)

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#define CG_CLKPIN_CNTL 0x660

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# define MUX_TCLK_TO_XCLK (1 << 8)

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# define XTALIN_DIVIDE (1 << 9)

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#define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c

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# define CURRENT_PROFILE_INDEX_MASK (0xf << 4)

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# define CURRENT_PROFILE_INDEX_SHIFT 4

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Alex Deucher

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[diff] [blame]

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#define S0_VID_LOWER_SMIO_CNTL 0x678

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#define S1_VID_LOWER_SMIO_CNTL 0x67c

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#define S2_VID_LOWER_SMIO_CNTL 0x680

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#define S3_VID_LOWER_SMIO_CNTL 0x684

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#define CG_FTV 0x690

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#define CG_FFCT_0 0x694

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# define UTC_0(x) ((x) << 0)

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# define UTC_0_MASK (0x3ff << 0)

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# define DTC_0(x) ((x) << 10)

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# define DTC_0_MASK (0x3ff << 10)

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#define CG_BSP 0x6d0

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# define BSP(x) ((x) << 0)

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# define BSP_MASK (0xffff << 0)

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# define BSU(x) ((x) << 16)

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# define BSU_MASK (0xf << 16)

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#define CG_AT 0x6d4

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# define CG_R(x) ((x) << 0)

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# define CG_R_MASK (0xffff << 0)

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# define CG_L(x) ((x) << 16)

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# define CG_L_MASK (0xffff << 16)

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#define CG_GIT 0x6d8

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# define CG_GICST(x) ((x) << 0)

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# define CG_GICST_MASK (0xffff << 0)

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# define CG_GIPOT(x) ((x) << 16)

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# define CG_GIPOT_MASK (0xffff << 16)

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#define CG_SSP 0x6e8

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# define SST(x) ((x) << 0)

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# define SST_MASK (0xffff << 0)

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# define SSTU(x) ((x) << 16)

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# define SSTU_MASK (0xf << 16)

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#define CG_DISPLAY_GAP_CNTL 0x714

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# define DISP1_GAP(x) ((x) << 0)

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# define DISP1_GAP_MASK (3 << 0)

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# define DISP2_GAP(x) ((x) << 2)

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# define DISP2_GAP_MASK (3 << 2)

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# define VBI_TIMER_COUNT(x) ((x) << 4)

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# define VBI_TIMER_COUNT_MASK (0x3fff << 4)

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# define VBI_TIMER_UNIT(x) ((x) << 20)

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# define VBI_TIMER_UNIT_MASK (7 << 20)

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# define DISP1_GAP_MCHG(x) ((x) << 24)

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# define DISP1_GAP_MCHG_MASK (3 << 24)

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# define DISP2_GAP_MCHG(x) ((x) << 26)

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# define DISP2_GAP_MCHG_MASK (3 << 26)

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#define CG_SPLL_SPREAD_SPECTRUM 0x790

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#define SSEN (1 << 0)

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#define CLKS(x) ((x) << 4)

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#define CLKS_MASK (0xfff << 4)

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#define CG_SPLL_SPREAD_SPECTRUM_2 0x794

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#define CLKV(x) ((x) << 0)

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#define CLKV_MASK (0x3ffffff << 0)

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#define CG_MPLL_SPREAD_SPECTRUM 0x798

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#define CG_UPLL_SPREAD_SPECTRUM 0x79c

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# define SSEN_MASK 0x00000001

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#define CG_CGTT_LOCAL_0 0x7d0

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#define CG_CGTT_LOCAL_1 0x7d4

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#define BIOS_SCRATCH_4 0x1734

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#define MC_SEQ_MISC0 0x2a00

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#define MC_SEQ_MISC0_GDDR5_SHIFT 28

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#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000

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#define MC_SEQ_MISC0_GDDR5_VALUE 5

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#define MC_ARB_SQM_RATIO 0x2770

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#define STATE0(x) ((x) << 0)

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#define STATE0_MASK (0xff << 0)

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#define STATE1(x) ((x) << 8)

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#define STATE1_MASK (0xff << 8)

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#define STATE2(x) ((x) << 16)

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#define STATE2_MASK (0xff << 16)

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#define STATE3(x) ((x) << 24)

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#define STATE3_MASK (0xff << 24)

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#define MC_ARB_RFSH_RATE 0x27b0

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#define POWERMODE0(x) ((x) << 0)

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#define POWERMODE0_MASK (0xff << 0)

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#define POWERMODE1(x) ((x) << 8)

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#define POWERMODE1_MASK (0xff << 8)

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#define POWERMODE2(x) ((x) << 16)

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#define POWERMODE2_MASK (0xff << 16)

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#define POWERMODE3(x) ((x) << 24)

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#define POWERMODE3_MASK (0xff << 24)

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#define CGTS_SM_CTRL_REG 0x9150

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3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

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/* Registers */

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#define CB_COLOR0_BASE 0x28040

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#define CB_COLOR1_BASE 0x28044

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#define CB_COLOR2_BASE 0x28048

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#define CB_COLOR3_BASE 0x2804C

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#define CB_COLOR4_BASE 0x28050

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#define CB_COLOR5_BASE 0x28054

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#define CB_COLOR6_BASE 0x28058

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#define CB_COLOR7_BASE 0x2805C

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#define CB_COLOR7_FRAG 0x280FC

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#define CC_GC_SHADER_PIPE_CONFIG 0x8950

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#define CC_RB_BACKEND_DISABLE 0x98F4

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#define BACKEND_DISABLE(x) ((x) << 16)

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#define CC_SYS_RB_BACKEND_DISABLE 0x3F88

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#define CGTS_SYS_TCC_DISABLE 0x3F90

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#define CGTS_TCC_DISABLE 0x9148

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#define CGTS_USER_SYS_TCC_DISABLE 0x3F94

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#define CGTS_USER_TCC_DISABLE 0x914C

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#define CONFIG_MEMSIZE 0x5428

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#define CP_ME_CNTL 0x86D8

Alex Deucher

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2013-06-26 00:11:19 -0400

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#define CP_ME_HALT (1 << 28)

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#define CP_PFP_HALT (1 << 26)

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3ce0a23

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#define CP_ME_RAM_DATA 0xC160

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#define CP_ME_RAM_RADDR 0xC158

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#define CP_ME_RAM_WADDR 0xC15C

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#define CP_MEQ_THRESHOLDS 0x8764

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#define STQ_SPLIT(x) ((x) << 0)

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#define CP_PERFMON_CNTL 0x87FC

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#define CP_PFP_UCODE_ADDR 0xC150

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#define CP_PFP_UCODE_DATA 0xC154

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#define CP_QUEUE_THRESHOLDS 0x8760

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#define ROQ_IB1_START(x) ((x) << 0)

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#define ROQ_IB2_START(x) ((x) << 8)

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#define CP_RB_CNTL 0xC104

Cédric Cano

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2011-02-11 19:45:38 -0500

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#define RB_BUFSZ(x) ((x) << 0)

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#define RB_BLKSZ(x) ((x) << 8)

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#define RB_NO_UPDATE (1 << 27)

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#define RB_RPTR_WR_ENA (1 << 31)

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#define BUF_SWAP_32BIT (2 << 16)

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#define CP_RB_RPTR 0x8700

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#define CP_RB_RPTR_ADDR 0xC10C

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#define CP_RB_RPTR_ADDR_HI 0xC110

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#define CP_RB_RPTR_WR 0xC108

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#define CP_RB_WPTR 0xC114

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#define CP_RB_WPTR_ADDR 0xC118

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#define CP_RB_WPTR_ADDR_HI 0xC11C

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#define CP_RB_WPTR_DELAY 0x8704

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#define CP_SEM_WAIT_TIMER 0x85BC

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#define DB_DEBUG3 0x98B0

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#define DB_CLK_OFF_DELAY(x) ((x) << 11)

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#define DB_DEBUG4 0x9B8C

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#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)

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#define DCP_TILING_CONFIG 0x6CA0

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#define PIPE_TILING(x) ((x) << 1)

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#define BANK_TILING(x) ((x) << 4)

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#define GROUP_SIZE(x) ((x) << 6)

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#define ROW_TILING(x) ((x) << 8)

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#define BANK_SWAPS(x) ((x) << 11)

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#define SAMPLE_SPLIT(x) ((x) << 14)

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#define BACKEND_MAP(x) ((x) << 16)

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#define GB_TILING_CONFIG 0x98F0

Alex Deucher

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2012-05-31 19:00:25 -0400

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#define PIPE_TILING__SHIFT 1

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#define PIPE_TILING__MASK 0x0000000e

Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

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Alex Deucher

4d75658

2012-09-27 15:08:35 -0400

[diff] [blame]

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#define DMA_TILING_CONFIG 0x3ec8

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#define DMA_TILING_CONFIG2 0xd0b8

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Christian König

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2013-04-08 12:41:37 +0200

[diff] [blame]

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/* RV730 only */

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#define UVD_UDEC_TILING_CONFIG 0xef40

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#define UVD_UDEC_DB_TILING_CONFIG 0xef44

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#define UVD_UDEC_DBW_TILING_CONFIG 0xef48

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Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

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#define GC_USER_SHADER_PIPE_CONFIG 0x8954

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#define INACTIVE_QD_PIPES(x) ((x) << 8)

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#define INACTIVE_QD_PIPES_MASK 0x0000FF00

Alex Deucher

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2012-05-31 19:00:25 -0400

[diff] [blame]

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#define INACTIVE_QD_PIPES_SHIFT 8

Jerome Glisse

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#define INACTIVE_SIMDS(x) ((x) << 16)

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#define INACTIVE_SIMDS_MASK 0x00FF0000

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#define GRBM_CNTL 0x8000

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#define GRBM_READ_TIMEOUT(x) ((x) << 0)

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#define GRBM_SOFT_RESET 0x8020

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#define SOFT_RESET_CP (1<<0)

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#define GRBM_STATUS 0x8010

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#define CMDFIFO_AVAIL_MASK 0x0000000F

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#define GUI_ACTIVE (1<<31)

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#define GRBM_STATUS2 0x8014

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Alex Deucher

66229b2

2013-06-26 00:11:19 -0400

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#define CG_THERMAL_CTRL 0x72C

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#define DPM_EVENT_SRC(x) ((x) << 0)

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#define DPM_EVENT_SRC_MASK (7 << 0)

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#define DIG_THERM_DPM(x) ((x) << 14)

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#define DIG_THERM_DPM_MASK 0x003FC000

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#define DIG_THERM_DPM_SHIFT 14

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#define CG_THERMAL_INT 0x734

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#define DIG_THERM_INTH(x) ((x) << 8)

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#define DIG_THERM_INTH_MASK 0x0000FF00

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#define DIG_THERM_INTH_SHIFT 8

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#define DIG_THERM_INTL(x) ((x) << 16)

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#define DIG_THERM_INTL_MASK 0x00FF0000

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#define DIG_THERM_INTL_SHIFT 16

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#define THERM_INT_MASK_HIGH (1 << 24)

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#define THERM_INT_MASK_LOW (1 << 25)

Alex Deucher

454d2e2

2013-02-14 10:04:02 -0500

[diff] [blame]

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Alex Deucher

21a8122

2010-07-02 12:58:16 -0400

[diff] [blame]

417

#define CG_MULT_THERMAL_STATUS 0x740

418

#define ASIC_T(x) ((x) << 16)

419

#define ASIC_T_MASK 0x3FF0000

420

#define ASIC_T_SHIFT 16

421

Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

422

#define HDP_HOST_PATH_CNTL 0x2C00

423

#define HDP_NONSURFACE_BASE 0x2C04

424

#define HDP_NONSURFACE_INFO 0x2C08

425

#define HDP_NONSURFACE_SIZE 0x2C0C

426

#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0

427

#define HDP_TILING_CONFIG 0x2F3C

Alex Deucher

812d046

2010-07-26 18:51:53 -0400

[diff] [blame]

428

#define HDP_DEBUG1 0x2F34

Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

429

Alex Deucher

5885b7a

2009-10-19 17:23:33 -0400

[diff] [blame]

430

#define MC_SHARED_CHMAP 0x2004

431

#define NOOFCHAN_SHIFT 12

432

#define NOOFCHAN_MASK 0x00003000

Alex Deucher

9535ab7

2010-11-22 17:56:18 -0500

[diff] [blame]

433

#define MC_SHARED_CHREMAP 0x2008

Alex Deucher

5885b7a

2009-10-19 17:23:33 -0400

[diff] [blame]

434

Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

435

#define MC_ARB_RAMCFG 0x2760

436

#define NOOFBANK_SHIFT 0

437

#define NOOFBANK_MASK 0x00000003

438

#define NOOFRANK_SHIFT 2

439

#define NOOFRANK_MASK 0x00000004

440

#define NOOFROWS_SHIFT 3

441

#define NOOFROWS_MASK 0x00000038

442

#define NOOFCOLS_SHIFT 6

443

#define NOOFCOLS_MASK 0x000000C0

444

#define CHANSIZE_SHIFT 8

445

#define CHANSIZE_MASK 0x00000100

446

#define BURSTLENGTH_SHIFT 9

447

#define BURSTLENGTH_MASK 0x00000200

Alex Deucher

5885b7a

2009-10-19 17:23:33 -0400

[diff] [blame]

448

#define CHANSIZE_OVERRIDE (1 << 11)

Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

449

#define MC_VM_AGP_TOP 0x2028

450

#define MC_VM_AGP_BOT 0x202C

451

#define MC_VM_AGP_BASE 0x2030

452

#define MC_VM_FB_LOCATION 0x2024

453

#define MC_VM_MB_L1_TLB0_CNTL 0x2234

454

#define MC_VM_MB_L1_TLB1_CNTL 0x2238

455

#define MC_VM_MB_L1_TLB2_CNTL 0x223C

456

#define MC_VM_MB_L1_TLB3_CNTL 0x2240

457

#define ENABLE_L1_TLB (1 << 0)

458

#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)

459

#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)

460

#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)

461

#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)

462

#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)

463

#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)

464

#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)

465

#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)

466

#define MC_VM_MD_L1_TLB0_CNTL 0x2654

467

#define MC_VM_MD_L1_TLB1_CNTL 0x2658

468

#define MC_VM_MD_L1_TLB2_CNTL 0x265C

Alex Deucher

0b8c30b

2012-05-31 18:54:43 -0400

[diff] [blame]

469

#define MC_VM_MD_L1_TLB3_CNTL 0x2698

Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

470

#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C

471

#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038

472

#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034

473

474

#define PA_CL_ENHANCE 0x8A14

475

#define CLIP_VTX_REORDER_ENA (1 << 0)

476

#define NUM_CLIP_SEQ(x) ((x) << 1)

477

#define PA_SC_AA_CONFIG 0x28C04

478

#define PA_SC_CLIPRECT_RULE 0x2820C

479

#define PA_SC_EDGERULE 0x28230

480

#define PA_SC_FIFO_SIZE 0x8BCC

481

#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)

482

#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)

483

#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24

484

#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)

485

#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16)

486

#define PA_SC_LINE_STIPPLE 0x28A0C

487

#define PA_SC_LINE_STIPPLE_STATE 0x8B10

488

#define PA_SC_MODE_CNTL 0x28A4C

489

#define PA_SC_MULTI_CHIP_CNTL 0x8B20

490

#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)

491

492

#define SCRATCH_REG0 0x8500

493

#define SCRATCH_REG1 0x8504

494

#define SCRATCH_REG2 0x8508

495

#define SCRATCH_REG3 0x850C

496

#define SCRATCH_REG4 0x8510

497

#define SCRATCH_REG5 0x8514

498

#define SCRATCH_REG6 0x8518

499

#define SCRATCH_REG7 0x851C

500

#define SCRATCH_UMSK 0x8540

501

#define SCRATCH_ADDR 0x8544

502

Alex Deucher

b866d13

2012-06-14 22:06:36 +0200

[diff] [blame]

503

#define SMX_SAR_CTL0 0xA008

Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

504

#define SMX_DC_CTL0 0xA020

505

#define USE_HASH_FUNCTION (1 << 0)

506

#define CACHE_DEPTH(x) ((x) << 1)

507

#define FLUSH_ALL_ON_EVENT (1 << 10)

508

#define STALL_ON_EVENT (1 << 11)

509

#define SMX_EVENT_CTL 0xA02C

510

#define ES_FLUSH_CTL(x) ((x) << 0)

511

#define GS_FLUSH_CTL(x) ((x) << 3)

512

#define ACK_FLUSH_CTL(x) ((x) << 6)

513

#define SYNC_FLUSH_CTL (1 << 8)

514

515

#define SPI_CONFIG_CNTL 0x9100

516

#define GPR_WRITE_PRIORITY(x) ((x) << 0)

517

#define DISABLE_INTERP_1 (1 << 5)

518

#define SPI_CONFIG_CNTL_1 0x913C

519

#define VTX_DONE_DELAY(x) ((x) << 0)

520

#define INTERP_ONE_PRIM_PER_ROW (1 << 4)

521

#define SPI_INPUT_Z 0x286D8

522

#define SPI_PS_IN_CONTROL_0 0x286CC

523

#define NUM_INTERP(x) ((x)<<0)

524

#define POSITION_ENA (1<<8)

525

#define POSITION_CENTROID (1<<9)

526

#define POSITION_ADDR(x) ((x)<<10)

527

#define PARAM_GEN(x) ((x)<<15)

528

#define PARAM_GEN_ADDR(x) ((x)<<19)

529

#define BARYC_SAMPLE_CNTL(x) ((x)<<26)

530

#define PERSP_GRADIENT_ENA (1<<28)

531

#define LINEAR_GRADIENT_ENA (1<<29)

532

#define POSITION_SAMPLE (1<<30)

533

#define BARYC_AT_SAMPLE_ENA (1<<31)

534

535

#define SQ_CONFIG 0x8C00

536

#define VC_ENABLE (1 << 0)

537

#define EXPORT_SRC_C (1 << 1)

538

#define DX9_CONSTS (1 << 2)

539

#define ALU_INST_PREFER_VECTOR (1 << 3)

540

#define DX10_CLAMP (1 << 4)

541

#define CLAUSE_SEQ_PRIO(x) ((x) << 8)

542

#define PS_PRIO(x) ((x) << 24)

543

#define VS_PRIO(x) ((x) << 26)

544

#define GS_PRIO(x) ((x) << 28)

545

#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0

546

#define SIMDA_RING0(x) ((x)<<0)

547

#define SIMDA_RING1(x) ((x)<<8)

548

#define SIMDB_RING0(x) ((x)<<16)

549

#define SIMDB_RING1(x) ((x)<<24)

550

#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4

551

#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8

552

#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC

553

#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0

554

#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4

555

#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8

556

#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC

557

#define ES_PRIO(x) ((x) << 30)

558

#define SQ_GPR_RESOURCE_MGMT_1 0x8C04

559

#define NUM_PS_GPRS(x) ((x) << 0)

560

#define NUM_VS_GPRS(x) ((x) << 16)

561

#define DYN_GPR_ENABLE (1 << 27)

562

#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)

563

#define SQ_GPR_RESOURCE_MGMT_2 0x8C08

564

#define NUM_GS_GPRS(x) ((x) << 0)

565

#define NUM_ES_GPRS(x) ((x) << 16)

566

#define SQ_MS_FIFO_SIZES 0x8CF0

567

#define CACHE_FIFO_SIZE(x) ((x) << 0)

568

#define FETCH_FIFO_HIWATER(x) ((x) << 8)

569

#define DONE_FIFO_HIWATER(x) ((x) << 16)

570

#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)

571

#define SQ_STACK_RESOURCE_MGMT_1 0x8C10

572

#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)

573

#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)

574

#define SQ_STACK_RESOURCE_MGMT_2 0x8C14

575

#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)

576

#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)

577

#define SQ_THREAD_RESOURCE_MGMT 0x8C0C

578

#define NUM_PS_THREADS(x) ((x) << 0)

579

#define NUM_VS_THREADS(x) ((x) << 8)

580

#define NUM_GS_THREADS(x) ((x) << 16)

581

#define NUM_ES_THREADS(x) ((x) << 24)

582

583

#define SX_DEBUG_1 0x9058

584

#define ENABLE_NEW_SMX_ADDRESS (1 << 16)

585

#define SX_EXPORT_BUFFER_SIZES 0x900C

586

#define COLOR_BUFFER_SIZE(x) ((x) << 0)

587

#define POSITION_BUFFER_SIZE(x) ((x) << 8)

588

#define SMX_BUFFER_SIZE(x) ((x) << 16)

589

#define SX_MISC 0x28350

590

591

#define TA_CNTL_AUX 0x9508

592

#define DISABLE_CUBE_WRAP (1 << 0)

593

#define DISABLE_CUBE_ANISO (1 << 1)

594

#define SYNC_GRADIENT (1 << 24)

595

#define SYNC_WALKER (1 << 25)

596

#define SYNC_ALIGNER (1 << 26)

597

#define BILINEAR_PRECISION_6_BIT (0 << 31)

598

#define BILINEAR_PRECISION_8_BIT (1 << 31)

599

600

#define TCP_CNTL 0x9610

Alex Deucher

9535ab7

2010-11-22 17:56:18 -0500

[diff] [blame]

601

#define TCP_CHAN_STEER 0x9614

Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

602

Alex Deucher

b866d13

2012-06-14 22:06:36 +0200

[diff] [blame]

603

#define VC_ENHANCE 0x9714

604

Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

605

#define VGT_CACHE_INVALIDATION 0x88C4

606

#define CACHE_INVALIDATION(x) ((x)<<0)

#define VC_ONLY 0

#define TC_ONLY 1

#define VC_AND_TC 2

#define AUTO_INVLD_EN(x) ((x) << 6)

#define NO_AUTO 0

#define ES_AUTO 1

#define GS_AUTO 2

#define ES_AND_GS_AUTO 3

615

#define VGT_ES_PER_GS 0x88CC

616

#define VGT_GS_PER_ES 0x88C8

617

#define VGT_GS_PER_VS 0x88E8

618

#define VGT_GS_VERTEX_REUSE 0x88D4

619

#define VGT_NUM_INSTANCES 0x8974

620

#define VGT_OUT_DEALLOC_CNTL 0x28C5C

621

#define DEALLOC_DIST_MASK 0x0000007F

622

#define VGT_STRMOUT_EN 0x28AB0

623

#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58

624

#define VTX_REUSE_DEPTH_MASK 0x000000FF

625

626

#define VM_CONTEXT0_CNTL 0x1410

627

#define ENABLE_CONTEXT (1 << 0)

628

#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)

629

#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)

630

#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C

631

#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C

632

#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C

633

#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518

634

#define VM_L2_CNTL 0x1400

635

#define ENABLE_L2_CACHE (1 << 0)

636

#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)

637

#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)

638

#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)

639

#define VM_L2_CNTL2 0x1404

640

#define INVALIDATE_ALL_L1_TLBS (1 << 0)

641

#define INVALIDATE_L2_CACHE (1 << 1)

642

#define VM_L2_CNTL3 0x1408

643

#define BANK_SELECT(x) ((x) << 0)

644

#define CACHE_UPDATE_MODE(x) ((x) << 6)

645

#define VM_L2_STATUS 0x140C

646

#define L2_BUSY (1 << 0)

647

648

#define WAIT_UNTIL 0x8040

649

Alex Deucher

4d75658

2012-09-27 15:08:35 -0400

[diff] [blame]

650

/* async DMA */

651

#define DMA_RB_RPTR 0xd008

652

#define DMA_RB_WPTR 0xd00c

653

654

/* async DMA packets */

655

#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \

656

(((t) & 0x1) << 23) | \

657

(((s) & 0x1) << 22) | \

658

(((n) & 0xFFFF) << 0))

659

/* async DMA Packet types */

660

#define DMA_PACKET_WRITE 0x2

661

#define DMA_PACKET_COPY 0x3

662

#define DMA_PACKET_INDIRECT_BUFFER 0x4

663

#define DMA_PACKET_SEMAPHORE 0x5

664

#define DMA_PACKET_FENCE 0x6

665

#define DMA_PACKET_TRAP 0x7

666

#define DMA_PACKET_CONSTANT_FILL 0xd

667

#define DMA_PACKET_NOP 0xf

668

669

Alex Deucher

bcc1c2a

2010-01-12 17:54:34 -0500

[diff] [blame]

670

#define SRBM_STATUS 0x0E50

671

Alex Deucher

3a2a67a

2012-03-28 13:19:06 -0400

[diff] [blame]

672

/* DCE 3.2 HDMI */

673

#define HDMI_CONTROL 0x7400

674

# define HDMI_KEEPOUT_MODE (1 << 0)

675

# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */

676

# define HDMI_ERROR_ACK (1 << 8)

677

# define HDMI_ERROR_MASK (1 << 9)

678

#define HDMI_STATUS 0x7404

679

# define HDMI_ACTIVE_AVMUTE (1 << 0)

680

# define HDMI_AUDIO_PACKET_ERROR (1 << 16)

681

# define HDMI_VBI_PACKET_ERROR (1 << 20)

682

#define HDMI_AUDIO_PACKET_CONTROL 0x7408

683

# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4)

684

# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)

685

#define HDMI_ACR_PACKET_CONTROL 0x740c

686

# define HDMI_ACR_SEND (1 << 0)

687

# define HDMI_ACR_CONT (1 << 1)

688

# define HDMI_ACR_SELECT(x) (((x) & 3) << 4)

689

# define HDMI_ACR_HW 0

690

# define HDMI_ACR_32 1

691

# define HDMI_ACR_44 2

692

# define HDMI_ACR_48 3

693

# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */

694

# define HDMI_ACR_AUTO_SEND (1 << 12)

695

#define HDMI_VBI_PACKET_CONTROL 0x7410

696

# define HDMI_NULL_SEND (1 << 0)

697

# define HDMI_GC_SEND (1 << 4)

698

# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */

699

#define HDMI_INFOFRAME_CONTROL0 0x7414

700

# define HDMI_AVI_INFO_SEND (1 << 0)

701

# define HDMI_AVI_INFO_CONT (1 << 1)

702

# define HDMI_AUDIO_INFO_SEND (1 << 4)

703

# define HDMI_AUDIO_INFO_CONT (1 << 5)

704

# define HDMI_MPEG_INFO_SEND (1 << 8)

705

# define HDMI_MPEG_INFO_CONT (1 << 9)

706

#define HDMI_INFOFRAME_CONTROL1 0x7418

707

# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)

708

# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)

709

# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)

710

#define HDMI_GENERIC_PACKET_CONTROL 0x741c

711

# define HDMI_GENERIC0_SEND (1 << 0)

712

# define HDMI_GENERIC0_CONT (1 << 1)

713

# define HDMI_GENERIC1_SEND (1 << 4)

714

# define HDMI_GENERIC1_CONT (1 << 5)

715

# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16)

716

# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24)

717

#define HDMI_GC 0x7428

718

# define HDMI_GC_AVMUTE (1 << 0)

719

#define AFMT_AUDIO_PACKET_CONTROL2 0x742c

720

# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0)

721

# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1)

722

# define AFMT_60958_CS_SOURCE (1 << 4)

723

# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8)

724

# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16)

725

#define AFMT_AVI_INFO0 0x7454

726

# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

727

# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8)

728

# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10)

729

# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12)

730

# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13)

731

# define AFMT_AVI_INFO_Y_RGB 0

732

# define AFMT_AVI_INFO_Y_YCBCR422 1

733

# define AFMT_AVI_INFO_Y_YCBCR444 2

734

# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)

735

# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16)

736

# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20)

737

# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22)

738

# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)

739

# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24)

740

# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26)

741

# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28)

742

# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31)

743

# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)

744

#define AFMT_AVI_INFO1 0x7458

745

# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */

746

# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */

747

# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)

748

#define AFMT_AVI_INFO2 0x745c

749

# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)

750

# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)

751

#define AFMT_AVI_INFO3 0x7460

752

# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)

753

# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24)

754

#define AFMT_MPEG_INFO0 0x7464

755

# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

756

# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)

757

# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)

758

# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)

759

#define AFMT_MPEG_INFO1 0x7468

760

# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)

761

# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8)

762

# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12)

763

#define AFMT_GENERIC0_HDR 0x746c

764

#define AFMT_GENERIC0_0 0x7470

765

#define AFMT_GENERIC0_1 0x7474

766

#define AFMT_GENERIC0_2 0x7478

767

#define AFMT_GENERIC0_3 0x747c

768

#define AFMT_GENERIC0_4 0x7480

769

#define AFMT_GENERIC0_5 0x7484

770

#define AFMT_GENERIC0_6 0x7488

771

#define AFMT_GENERIC1_HDR 0x748c

772

#define AFMT_GENERIC1_0 0x7490

773

#define AFMT_GENERIC1_1 0x7494

774

#define AFMT_GENERIC1_2 0x7498

775

#define AFMT_GENERIC1_3 0x749c

776

#define AFMT_GENERIC1_4 0x74a0

777

#define AFMT_GENERIC1_5 0x74a4

778

#define AFMT_GENERIC1_6 0x74a8

779

#define HDMI_ACR_32_0 0x74ac

780

# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)

781

#define HDMI_ACR_32_1 0x74b0

782

# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0)

783

#define HDMI_ACR_44_0 0x74b4

784

# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12)

785

#define HDMI_ACR_44_1 0x74b8

786

# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0)

787

#define HDMI_ACR_48_0 0x74bc

788

# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)

789

#define HDMI_ACR_48_1 0x74c0

790

# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0)

791

#define HDMI_ACR_STATUS_0 0x74c4

792

#define HDMI_ACR_STATUS_1 0x74c8

793

#define AFMT_AUDIO_INFO0 0x74cc

794

# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)

795

# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8)

796

# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16)

797

#define AFMT_AUDIO_INFO1 0x74d0

798

# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)

799

# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)

800

# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)

801

# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)

802

#define AFMT_60958_0 0x74d4

803

# define AFMT_60958_CS_A(x) (((x) & 1) << 0)

804

# define AFMT_60958_CS_B(x) (((x) & 1) << 1)

805

# define AFMT_60958_CS_C(x) (((x) & 1) << 2)

806

# define AFMT_60958_CS_D(x) (((x) & 3) << 3)

807

# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6)

808

# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)

809

# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)

810

# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)

811

# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)

812

# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)

813

#define AFMT_60958_1 0x74d8

814

# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)

815

# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)

816

# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16)

817

# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18)

818

# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)

819

#define AFMT_AUDIO_CRC_CONTROL 0x74dc

820

# define AFMT_AUDIO_CRC_EN (1 << 0)

821

#define AFMT_RAMP_CONTROL0 0x74e0

822

# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)

823

# define AFMT_RAMP_DATA_SIGN (1 << 31)

824

#define AFMT_RAMP_CONTROL1 0x74e4

825

# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)

826

# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)

827

#define AFMT_RAMP_CONTROL2 0x74e8

828

# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)

829

#define AFMT_RAMP_CONTROL3 0x74ec

830

# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)

831

#define AFMT_60958_2 0x74f0

832

# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)

833

# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)

834

# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)

835

# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)

836

# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)

837

# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)

838

#define AFMT_STATUS 0x7600

839

# define AFMT_AUDIO_ENABLE (1 << 4)

840

# define AFMT_AZ_FORMAT_WTRIG (1 << 28)

841

# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)

842

# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)

843

#define AFMT_AUDIO_PACKET_CONTROL 0x7604

844

# define AFMT_AUDIO_SAMPLE_SEND (1 << 0)

845

# define AFMT_AUDIO_TEST_EN (1 << 12)

846

# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)

847

# define AFMT_60958_CS_UPDATE (1 << 26)

848

# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)

849

# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)

850

# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)

851

# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)

852

#define AFMT_VBI_PACKET_CONTROL 0x7608

853

# define AFMT_GENERIC0_UPDATE (1 << 2)

854

#define AFMT_INFOFRAME_CONTROL0 0x760c

855

# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */

856

# define AFMT_AUDIO_INFO_UPDATE (1 << 7)

857

# define AFMT_MPEG_INFO_UPDATE (1 << 10)

858

#define AFMT_GENERIC0_7 0x7610

859

/* second instance starts at 0x7800 */

860

#define HDMI_OFFSET0 (0x7400 - 0x7400)

861

#define HDMI_OFFSET1 (0x7800 - 0x7400)

862

Alex Deucher

fbed600

2012-12-03 11:52:49 -0500

[diff] [blame]

863

/* DCE3.2 ELD audio interface */

864

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */

865

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */

866

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */

867

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */

868

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */

869

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */

870

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */

871

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */

872

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */

873

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */

874

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */

875

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */

876

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */

877

#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */

878

# define MAX_CHANNELS(x) (((x) & 0x7) << 0)

879

/* max channels minus one. 7 = 8 channels */

880

# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)

881

# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)

882

# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */

883

/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO

* bit0 = 32 kHz

* bit1 = 44.1 kHz

* bit2 = 48 kHz

* bit3 = 88.2 kHz

* bit4 = 96 kHz

* bit5 = 176.4 kHz

* bit6 = 192 kHz

*/

#define AZ_HOT_PLUG_CONTROL 0x7300

894

# define AZ_FORCE_CODEC_WAKE (1 << 0)

895

# define PIN0_JACK_DETECTION_ENABLE (1 << 4)

896

# define PIN1_JACK_DETECTION_ENABLE (1 << 5)

897

# define PIN2_JACK_DETECTION_ENABLE (1 << 6)

898

# define PIN3_JACK_DETECTION_ENABLE (1 << 7)

899

# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8)

900

# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9)

901

# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10)

902

# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11)

903

# define CODEC_HOT_PLUG_ENABLE (1 << 12)

904

# define PIN0_AUDIO_ENABLED (1 << 24)

905

# define PIN1_AUDIO_ENABLED (1 << 25)

906

# define PIN2_AUDIO_ENABLED (1 << 26)

907

# define PIN3_AUDIO_ENABLED (1 << 27)

908

# define AUDIO_ENABLED (1 << 31)

909

910

Alex Deucher

6f34be5

2010-11-21 10:59:01 -0500

[diff] [blame]

911

#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110

912

#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914

913

#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114

914

#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118

915

#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c

916

#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c

917

Alex Deucher

66229b2

2013-06-26 00:11:19 -0400

[diff] [blame]

918

/* PCIE indirect regs */

919

#define PCIE_P_CNTL 0x40

920

# define P_PLL_PWRDN_IN_L1L23 (1 << 3)

921

# define P_PLL_BUF_PDNB (1 << 4)

922

# define P_PLL_PDNB (1 << 9)

923

# define P_ALLOW_PRX_FRONTEND_SHUTOFF (1 << 12)

924

/* PCIE PORT regs */

925

#define PCIE_LC_CNTL 0xa0

926

# define LC_L0S_INACTIVITY(x) ((x) << 8)

927

# define LC_L0S_INACTIVITY_MASK (0xf << 8)

928

# define LC_L0S_INACTIVITY_SHIFT 8

929

# define LC_L1_INACTIVITY(x) ((x) << 12)

930

# define LC_L1_INACTIVITY_MASK (0xf << 12)

931

# define LC_L1_INACTIVITY_SHIFT 12

932

# define LC_PMI_TO_L1_DIS (1 << 16)

933

# define LC_ASPM_TO_L1_DIS (1 << 24)

Alex Deucher

9e46a48

2011-01-06 18:49:35 -0500

[diff] [blame]

934

#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */

935

#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */

936

# define LC_LINK_WIDTH_SHIFT 0

937

# define LC_LINK_WIDTH_MASK 0x7

938

# define LC_LINK_WIDTH_X0 0

939

# define LC_LINK_WIDTH_X1 1

940

# define LC_LINK_WIDTH_X2 2

941

# define LC_LINK_WIDTH_X4 3

942

# define LC_LINK_WIDTH_X8 4

943

# define LC_LINK_WIDTH_X16 6

944

# define LC_LINK_WIDTH_RD_SHIFT 4

945

# define LC_LINK_WIDTH_RD_MASK 0x70

946

# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)

947

# define LC_RECONFIG_NOW (1 << 8)

948

# define LC_RENEGOTIATION_SUPPORT (1 << 9)

949

# define LC_RENEGOTIATE_EN (1 << 10)

950

# define LC_SHORT_RECONFIG_EN (1 << 11)

951

# define LC_UPCONFIGURE_SUPPORT (1 << 12)

952

# define LC_UPCONFIGURE_DIS (1 << 13)

953

#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */

954

# define LC_GEN2_EN_STRAP (1 << 0)

955

# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)

956

# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)

957

# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)

958

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)

959

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3

960

# define LC_CURRENT_DATA_RATE (1 << 11)

Alex Deucher

66229b2

2013-06-26 00:11:19 -0400

[diff] [blame]

961

# define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12)

962

# define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12)

963

# define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12

Alex Deucher

9e46a48

2011-01-06 18:49:35 -0500

[diff] [blame]

964

# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)

965

# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)

966

# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)

967

# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)

968

#define MM_CFGREGS_CNTL 0x544c

969

# define MM_WR_TO_CFG_EN (1 << 3)

970

#define LINK_CNTL2 0x88 /* F0 */

971

# define TARGET_LINK_SPEED_MASK (0xf << 0)

972

# define SELECTABLE_DEEMPHASIS (1 << 6)

973

Christian König

e409b12

2013-08-13 11:56:53 +0200

[diff] [blame]

/*

* PM4

*/

#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \

978

(((reg) >> 2) & 0xFFFF) | \

979

((n) & 0x3FFF) << 16)

980

#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \

981

(((op) & 0xFF) << 8) | \

982

((n) & 0x3FFF) << 16)

983

Christian König

f2ba57b

2013-04-08 12:41:29 +0200

[diff] [blame]

984

/* UVD */

Christian König

e409b12

2013-08-13 11:56:53 +0200

[diff] [blame]

985

#define UVD_GPCOM_VCPU_CMD 0xef0c

986

#define UVD_GPCOM_VCPU_DATA0 0xef10

987

#define UVD_GPCOM_VCPU_DATA1 0xef14

988

Christian König

f2ba57b

2013-04-08 12:41:29 +0200

[diff] [blame]

989

#define UVD_LMI_EXT40_ADDR 0xf498

990

#define UVD_VCPU_CHIP_ID 0xf4d4

991

#define UVD_VCPU_CACHE_OFFSET0 0xf4d8

992

#define UVD_VCPU_CACHE_SIZE0 0xf4dc

993

#define UVD_VCPU_CACHE_OFFSET1 0xf4e0

994

#define UVD_VCPU_CACHE_SIZE1 0xf4e4

995

#define UVD_VCPU_CACHE_OFFSET2 0xf4e8

996

#define UVD_VCPU_CACHE_SIZE2 0xf4ec

997

#define UVD_LMI_ADDR_EXT 0xf594

998

999

#define UVD_RBC_RB_RPTR 0xf690

1000

#define UVD_RBC_RB_WPTR 0xf694

1001

Christian König

e409b12

2013-08-13 11:56:53 +0200

[diff] [blame]

1002

#define UVD_CONTEXT_ID 0xf6f4

1003

Jerome Glisse

3ce0a23

2009-09-08 10:10:24 +1000

[diff] [blame]

1004

#endif