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gerrit-public.fairphone.software / kernel / msm-4.19 / 0a7f364e812285246cd617a51194a3f8bd0e8daa / . / include / drm / i915_pciids.h
blob: 940ece4934bab0e0c17f491b28da059454967621 [file] [log] [blame]
Jesse Barnesa0a18072013-07-26 13:32:51 -0700[diff] [blame]1/*
2 * Copyright 2013 Intel Corporation
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25#ifndef _I915_PCIIDS_H
26#define _I915_PCIIDS_H
27
28/*
29 * A pci_device_id struct {
30 * __u32 vendor, device;
31 * __u32 subvendor, subdevice;
32 * __u32 class, class_mask;
33 * kernel_ulong_t driver_data;
34 * };
35 * Don't use C99 here because "class" is reserved and we want to
36 * give userspace flexibility.
37 */
38#define INTEL_VGA_DEVICE(id, info) { \
39 0x8086, id, \
40 ~0, ~0, \
41 0x030000, 0xff0000, \
42 (unsigned long) info }
43
44#define INTEL_QUANTA_VGA_DEVICE(info) { \
45 0x8086, 0x16a, \
46 0x152d, 0x8990, \
47 0x030000, 0xff0000, \
48 (unsigned long) info }
49
50#define INTEL_I830_IDS(info) \
51 INTEL_VGA_DEVICE(0x3577, info)
52
53#define INTEL_I845G_IDS(info) \
54 INTEL_VGA_DEVICE(0x2562, info)
55
56#define INTEL_I85X_IDS(info) \
57 INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
58 INTEL_VGA_DEVICE(0x358e, info)
59
60#define INTEL_I865G_IDS(info) \
61 INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
62
63#define INTEL_I915G_IDS(info) \
64 INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
65 INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
66
67#define INTEL_I915GM_IDS(info) \
68 INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
69
70#define INTEL_I945G_IDS(info) \
71 INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
72
73#define INTEL_I945GM_IDS(info) \
74 INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
75 INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
76
77#define INTEL_I965G_IDS(info) \
78 INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
79 INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
80 INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
81 INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
82
83#define INTEL_G33_IDS(info) \
84 INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
85 INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
86 INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
87
88#define INTEL_I965GM_IDS(info) \
89 INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
90 INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
91
92#define INTEL_GM45_IDS(info) \
93 INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
94
95#define INTEL_G45_IDS(info) \
96 INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
97 INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
98 INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
99 INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
100 INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
101 INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
102
103#define INTEL_PINEVIEW_IDS(info) \
104 INTEL_VGA_DEVICE(0xa001, info), \
105 INTEL_VGA_DEVICE(0xa011, info)
106
107#define INTEL_IRONLAKE_D_IDS(info) \
108 INTEL_VGA_DEVICE(0x0042, info)
109
110#define INTEL_IRONLAKE_M_IDS(info) \
111 INTEL_VGA_DEVICE(0x0046, info)
112
113#define INTEL_SNB_D_IDS(info) \
114 INTEL_VGA_DEVICE(0x0102, info), \
115 INTEL_VGA_DEVICE(0x0112, info), \
116 INTEL_VGA_DEVICE(0x0122, info), \
117 INTEL_VGA_DEVICE(0x010A, info)
118
119#define INTEL_SNB_M_IDS(info) \
120 INTEL_VGA_DEVICE(0x0106, info), \
121 INTEL_VGA_DEVICE(0x0116, info), \
122 INTEL_VGA_DEVICE(0x0126, info)
123
124#define INTEL_IVB_M_IDS(info) \
125 INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
126 INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
127
128#define INTEL_IVB_D_IDS(info) \
129 INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
130 INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
131 INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
132 INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
133
134#define INTEL_IVB_Q_IDS(info) \
135 INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
136
137#define INTEL_HSW_D_IDS(info) \
138 INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
139 INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
140 INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
141 INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
142 INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
143 INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
144 INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
145 INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
146 INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
147 INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
148 INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
149 INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
150 INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
151 INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
152 INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
153 INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
154 INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
155 INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
156 INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
157 INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
158 INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
159 INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
160 INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
161 INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
162 INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
163 INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
164 INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
165 INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
166 INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
167 INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
168 INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
169 INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
170 INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
171 INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
172 INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
173 INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
174 INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
175 INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
176 INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
177 INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
178 INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
179 INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
180 INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
181 INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
182 INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \
183
184#define INTEL_HSW_M_IDS(info) \
185 INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
186 INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
187 INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
188 INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
189 INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
190 INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
191 INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
192 INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
193 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
194 INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
195 INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
196 INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
197 INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
198 INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
199 INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
200
201#define INTEL_VLV_M_IDS(info) \
202 INTEL_VGA_DEVICE(0x0f30, info), \
203 INTEL_VGA_DEVICE(0x0f31, info), \
204 INTEL_VGA_DEVICE(0x0f32, info), \
205 INTEL_VGA_DEVICE(0x0f33, info), \
206 INTEL_VGA_DEVICE(0x0157, info)
207
208#define INTEL_VLV_D_IDS(info) \
209 INTEL_VGA_DEVICE(0x0155, info)
210
Ben Widawsky4d4dead2013-11-03 16:47:33 -0800[diff] [blame]211#define _INTEL_BDW_M(gt, id, info) \
212 INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
213#define _INTEL_BDW_D(gt, id, info) \
214 INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
215
216#define _INTEL_BDW_M_IDS(gt, info) \
217 _INTEL_BDW_M(gt, 0x1602, info), /* ULT */ \
218 _INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \
219 _INTEL_BDW_M(gt, 0x160B, info), /* Iris */ \
220 _INTEL_BDW_M(gt, 0x160E, info) /* ULX */
221
222#define _INTEL_BDW_D_IDS(gt, info) \
223 _INTEL_BDW_D(gt, 0x160A, info), /* Server */ \
224 _INTEL_BDW_D(gt, 0x160D, info) /* Workstation */
225
226#define INTEL_BDW_M_IDS(info) \
227 _INTEL_BDW_M_IDS(1, info), \
228 _INTEL_BDW_M_IDS(2, info), \
229 _INTEL_BDW_M_IDS(3, info)
230
231#define INTEL_BDW_D_IDS(info) \
232 _INTEL_BDW_D_IDS(1, info), \
233 _INTEL_BDW_D_IDS(2, info), \
234 _INTEL_BDW_D_IDS(3, info)
235
Jesse Barnesa0a18072013-07-26 13:32:51 -0700[diff] [blame]236#endif /* _I915_PCIIDS_H */