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Balaji T Ke8deb282009-12-14 00:25:31 +01001/*
2 * twl6030-irq.c - TWL6030 irq support
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 *
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
8 *
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
11 *
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
14 *
15 * TWL6030 specific code and IRQ handling changes by
16 * Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
17 * Balaji T K <balajitk@ti.com>
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 */
33
34#include <linux/init.h>
Paul Gortmaker5d4a3572011-07-10 12:41:10 -040035#include <linux/export.h>
Balaji T Ke8deb282009-12-14 00:25:31 +010036#include <linux/interrupt.h>
37#include <linux/irq.h>
38#include <linux/kthread.h>
39#include <linux/i2c/twl.h>
kishore kadiyala72f2e2c2010-09-24 17:13:20 +000040#include <linux/platform_device.h>
Todd Poynorab2b9262011-10-04 11:52:29 +020041#include <linux/suspend.h>
Benoit Cousson78518ff2012-02-29 19:40:31 +010042#include <linux/of.h>
43#include <linux/irqdomain.h>
Balaji T Ke8deb282009-12-14 00:25:31 +010044
G, Manjunath Kondaiahb0b4a7c2010-10-19 11:02:48 +020045#include "twl-core.h"
46
Balaji T Ke8deb282009-12-14 00:25:31 +010047/*
48 * TWL6030 (unlike its predecessors, which had two level interrupt handling)
49 * three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
50 * It exposes status bits saying who has raised an interrupt. There are
51 * three mask registers that corresponds to these status registers, that
52 * enables/disables these interrupts.
53 *
54 * We set up IRQs starting at a platform-specified base. An interrupt map table,
55 * specifies mapping between interrupt number and the associated module.
Balaji T Ke8deb282009-12-14 00:25:31 +010056 */
Benoit Cousson78518ff2012-02-29 19:40:31 +010057#define TWL6030_NR_IRQS 20
Balaji T Ke8deb282009-12-14 00:25:31 +010058
59static int twl6030_interrupt_mapping[24] = {
60 PWR_INTR_OFFSET, /* Bit 0 PWRON */
61 PWR_INTR_OFFSET, /* Bit 1 RPWRON */
62 PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
63 RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
64 RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
65 HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
66 SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
67 SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
68
69 SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
70 BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
71 SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
72 MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
73 RSV_INTR_OFFSET, /* Bit 12 Reserved */
74 MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
75 MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
76 GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
77
78 USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
79 USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
80 USBOTG_INTR_OFFSET, /* Bit 18 ID */
Hema HK77b1d3f2010-12-10 17:55:37 +053081 USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
Balaji T Ke8deb282009-12-14 00:25:31 +010082 CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
Graeme Gregory6523b142011-05-12 14:27:56 +010083 CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
84 CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
Balaji T Ke8deb282009-12-14 00:25:31 +010085 RSV_INTR_OFFSET, /* Bit 23 Reserved */
86};
87/*----------------------------------------------------------------------*/
88
Grygorii Strashko0aa8c682013-07-25 16:15:50 +030089struct twl6030_irq {
90 unsigned int irq_base;
91 int twl_irq;
92 bool irq_wake_enabled;
93 atomic_t wakeirqs;
94 struct notifier_block pm_nb;
95 struct irq_chip irq_chip;
96 struct irq_domain *irq_domain;
97};
Balaji T Ke8deb282009-12-14 00:25:31 +010098
Grygorii Strashko0aa8c682013-07-25 16:15:50 +030099static struct twl6030_irq *twl6030_irq;
Todd Poynorab2b9262011-10-04 11:52:29 +0200100
101static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
102 unsigned long pm_event, void *unused)
103{
104 int chained_wakeups;
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300105 struct twl6030_irq *pdata = container_of(notifier, struct twl6030_irq,
106 pm_nb);
Todd Poynorab2b9262011-10-04 11:52:29 +0200107
108 switch (pm_event) {
109 case PM_SUSPEND_PREPARE:
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300110 chained_wakeups = atomic_read(&pdata->wakeirqs);
Todd Poynorab2b9262011-10-04 11:52:29 +0200111
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300112 if (chained_wakeups && !pdata->irq_wake_enabled) {
113 if (enable_irq_wake(pdata->twl_irq))
Todd Poynorab2b9262011-10-04 11:52:29 +0200114 pr_err("twl6030 IRQ wake enable failed\n");
115 else
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300116 pdata->irq_wake_enabled = true;
117 } else if (!chained_wakeups && pdata->irq_wake_enabled) {
118 disable_irq_wake(pdata->twl_irq);
119 pdata->irq_wake_enabled = false;
Todd Poynorab2b9262011-10-04 11:52:29 +0200120 }
121
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300122 disable_irq(pdata->twl_irq);
Todd Poynorab2b9262011-10-04 11:52:29 +0200123 break;
Todd Poynor782baa22011-09-26 16:44:24 -0700124
125 case PM_POST_SUSPEND:
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300126 enable_irq(pdata->twl_irq);
Todd Poynor782baa22011-09-26 16:44:24 -0700127 break;
128
Todd Poynorab2b9262011-10-04 11:52:29 +0200129 default:
130 break;
131 }
132
133 return NOTIFY_DONE;
134}
135
Balaji T Ke8deb282009-12-14 00:25:31 +0100136/*
Naga Venkata Srikanth V87343e52013-07-25 16:15:47 +0300137* Threaded irq handler for the twl6030 interrupt.
138* We query the interrupt controller in the twl6030 to determine
139* which module is generating the interrupt request and call
140* handle_nested_irq for that module.
141*/
142static irqreturn_t twl6030_irq_thread(int irq, void *data)
Balaji T Ke8deb282009-12-14 00:25:31 +0100143{
Naga Venkata Srikanth V87343e52013-07-25 16:15:47 +0300144 int i, ret;
145 union {
Balaji T Ke8deb282009-12-14 00:25:31 +0100146 u8 bytes[4];
147 u32 int_sts;
Naga Venkata Srikanth V87343e52013-07-25 16:15:47 +0300148 } sts;
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300149 struct twl6030_irq *pdata = data;
Balaji T Ke8deb282009-12-14 00:25:31 +0100150
Naga Venkata Srikanth V87343e52013-07-25 16:15:47 +0300151 /* read INT_STS_A, B and C in one shot using a burst read */
152 ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes, REG_INT_STS_A, 3);
153 if (ret) {
154 pr_warn("twl6030_irq: I2C error %d reading PIH ISR\n", ret);
155 return IRQ_HANDLED;
Balaji T Ke8deb282009-12-14 00:25:31 +0100156 }
157
Naga Venkata Srikanth V87343e52013-07-25 16:15:47 +0300158 sts.bytes[3] = 0; /* Only 24 bits are valid*/
Balaji T Ke8deb282009-12-14 00:25:31 +0100159
Naga Venkata Srikanth V87343e52013-07-25 16:15:47 +0300160 /*
161 * Since VBUS status bit is not reliable for VBUS disconnect
162 * use CHARGER VBUS detection status bit instead.
163 */
164 if (sts.bytes[2] & 0x10)
165 sts.bytes[2] |= 0x08;
166
167 for (i = 0; sts.int_sts; sts.int_sts >>= 1, i++)
168 if (sts.int_sts & 0x1) {
Grygorii Strashkob32408f2013-07-25 16:15:49 +0300169 int module_irq =
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300170 irq_find_mapping(pdata->irq_domain,
Grygorii Strashkob32408f2013-07-25 16:15:49 +0300171 twl6030_interrupt_mapping[i]);
172 if (module_irq)
173 handle_nested_irq(module_irq);
174 else
175 pr_err("twl6030_irq: Unmapped PIH ISR %u detected\n",
176 i);
Naga Venkata Srikanth V87343e52013-07-25 16:15:47 +0300177 pr_debug("twl6030_irq: PIH ISR %u, virq%u\n",
178 i, module_irq);
179 }
180
181 /*
182 * NOTE:
183 * Simulation confirms that documentation is wrong w.r.t the
184 * interrupt status clear operation. A single *byte* write to
185 * any one of STS_A to STS_C register results in all three
186 * STS registers being reset. Since it does not matter which
187 * value is written, all three registers are cleared on a
188 * single byte write, so we just use 0x0 to clear.
189 */
190 ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
191 if (ret)
192 pr_warn("twl6030_irq: I2C error in clearing PIH ISR\n");
193
Balaji T Ke8deb282009-12-14 00:25:31 +0100194 return IRQ_HANDLED;
195}
196
197/*----------------------------------------------------------------------*/
198
Nishanth Menonb8b8d792012-02-22 20:03:59 -0600199static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
Santosh Shilimkar49dcd072011-09-06 21:29:30 +0530200{
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300201 struct twl6030_irq *pdata = irq_get_chip_data(d->irq);
202
Todd Poynorab2b9262011-10-04 11:52:29 +0200203 if (on)
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300204 atomic_inc(&pdata->wakeirqs);
Todd Poynorab2b9262011-10-04 11:52:29 +0200205 else
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300206 atomic_dec(&pdata->wakeirqs);
Santosh Shilimkar49dcd072011-09-06 21:29:30 +0530207
Todd Poynorab2b9262011-10-04 11:52:29 +0200208 return 0;
Santosh Shilimkar49dcd072011-09-06 21:29:30 +0530209}
210
Balaji T Ke8deb282009-12-14 00:25:31 +0100211int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
212{
213 int ret;
214 u8 unmask_value;
215 ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
216 REG_INT_STS_A + offset);
217 unmask_value &= (~(bit_mask));
218 ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
219 REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
220 return ret;
221}
222EXPORT_SYMBOL(twl6030_interrupt_unmask);
223
224int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
225{
226 int ret;
227 u8 mask_value;
228 ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
229 REG_INT_STS_A + offset);
230 mask_value |= (bit_mask);
231 ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
232 REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
233 return ret;
234}
235EXPORT_SYMBOL(twl6030_interrupt_mask);
236
kishore kadiyala72f2e2c2010-09-24 17:13:20 +0000237int twl6030_mmc_card_detect_config(void)
238{
239 int ret;
240 u8 reg_val = 0;
241
242 /* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
243 twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
244 REG_INT_MSK_LINE_B);
245 twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
246 REG_INT_MSK_STS_B);
247 /*
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300248 * Initially Configuring MMC_CTRL for receiving interrupts &
kishore kadiyala72f2e2c2010-09-24 17:13:20 +0000249 * Card status on TWL6030 for MMC1
250 */
251 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL);
252 if (ret < 0) {
253 pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
254 return ret;
255 }
256 reg_val &= ~VMMC_AUTO_OFF;
257 reg_val |= SW_FC;
258 ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
259 if (ret < 0) {
260 pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
261 return ret;
262 }
263
264 /* Configuring PullUp-PullDown register */
265 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val,
266 TWL6030_CFG_INPUT_PUPD3);
267 if (ret < 0) {
268 pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
269 ret);
270 return ret;
271 }
272 reg_val &= ~(MMC_PU | MMC_PD);
273 ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
274 TWL6030_CFG_INPUT_PUPD3);
275 if (ret < 0) {
276 pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
277 ret);
278 return ret;
279 }
Benoit Coussonbdd61bc2012-03-02 16:15:22 +0100280
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300281 return irq_find_mapping(twl6030_irq->irq_domain,
282 MMCDETECT_INTR_OFFSET);
kishore kadiyala72f2e2c2010-09-24 17:13:20 +0000283}
284EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
285
286int twl6030_mmc_card_detect(struct device *dev, int slot)
287{
288 int ret = -EIO;
289 u8 read_reg = 0;
290 struct platform_device *pdev = to_platform_device(dev);
291
292 if (pdev->id) {
293 /* TWL6030 provide's Card detect support for
294 * only MMC1 controller.
295 */
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300296 pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
kishore kadiyala72f2e2c2010-09-24 17:13:20 +0000297 return ret;
298 }
299 /*
300 * BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
301 * 0 - Card not present ,1 - Card present
302 */
303 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
304 TWL6030_MMCCTRL);
305 if (ret >= 0)
306 ret = read_reg & STS_MMC;
307 return ret;
308}
309EXPORT_SYMBOL(twl6030_mmc_card_detect);
310
Grygorii Strashkob32408f2013-07-25 16:15:49 +0300311static int twl6030_irq_map(struct irq_domain *d, unsigned int virq,
312 irq_hw_number_t hwirq)
313{
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300314 struct twl6030_irq *pdata = d->host_data;
315
316 irq_set_chip_data(virq, pdata);
317 irq_set_chip_and_handler(virq, &pdata->irq_chip, handle_simple_irq);
Grygorii Strashkob32408f2013-07-25 16:15:49 +0300318 irq_set_nested_thread(virq, true);
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300319 irq_set_parent(virq, pdata->twl_irq);
Grygorii Strashkob32408f2013-07-25 16:15:49 +0300320
321#ifdef CONFIG_ARM
322 /*
323 * ARM requires an extra step to clear IRQ_NOREQUEST, which it
324 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
325 */
326 set_irq_flags(virq, IRQF_VALID);
327#else
328 /* same effect on other architectures */
329 irq_set_noprobe(virq);
330#endif
331
332 return 0;
333}
334
335static void twl6030_irq_unmap(struct irq_domain *d, unsigned int virq)
336{
337#ifdef CONFIG_ARM
338 set_irq_flags(virq, 0);
339#endif
340 irq_set_chip_and_handler(virq, NULL, NULL);
341 irq_set_chip_data(virq, NULL);
342}
343
344static struct irq_domain_ops twl6030_irq_domain_ops = {
345 .map = twl6030_irq_map,
346 .unmap = twl6030_irq_unmap,
347 .xlate = irq_domain_xlate_onetwocell,
348};
349
Benoit Cousson78518ff2012-02-29 19:40:31 +0100350int twl6030_init_irq(struct device *dev, int irq_num)
Balaji T Ke8deb282009-12-14 00:25:31 +0100351{
Benoit Cousson78518ff2012-02-29 19:40:31 +0100352 struct device_node *node = dev->of_node;
Grygorii Strashkob32408f2013-07-25 16:15:49 +0300353 int nr_irqs;
Grygorii Strashkoa820e562013-07-25 16:15:48 +0300354 int status;
Peter Ujfalusi14591d82012-11-13 09:28:45 +0100355 u8 mask[3];
Benoit Cousson78518ff2012-02-29 19:40:31 +0100356
357 nr_irqs = TWL6030_NR_IRQS;
358
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300359 twl6030_irq = devm_kzalloc(dev, sizeof(*twl6030_irq), GFP_KERNEL);
360 if (!twl6030_irq) {
361 dev_err(dev, "twl6030_irq: Memory allocation failed\n");
362 return -ENOMEM;
363 }
364
Peter Ujfalusi14591d82012-11-13 09:28:45 +0100365 mask[0] = 0xFF;
Balaji T Ke8deb282009-12-14 00:25:31 +0100366 mask[1] = 0xFF;
367 mask[2] = 0xFF;
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100368
369 /* mask all int lines */
Grygorii Strashkoa820e562013-07-25 16:15:48 +0300370 status = twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100371 /* mask all int sts */
Grygorii Strashkoa820e562013-07-25 16:15:48 +0300372 status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100373 /* clear INT_STS_A,B,C */
Grygorii Strashkoa820e562013-07-25 16:15:48 +0300374 status |= twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
375
376 if (status < 0) {
377 dev_err(dev, "I2C err writing TWL_MODULE_PIH: %d\n", status);
378 return status;
379 }
Balaji T Ke8deb282009-12-14 00:25:31 +0100380
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100381 /*
382 * install an irq handler for each of the modules;
Balaji T Ke8deb282009-12-14 00:25:31 +0100383 * clone dummy irq_chip since PIH can't *do* anything
384 */
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300385 twl6030_irq->irq_chip = dummy_irq_chip;
386 twl6030_irq->irq_chip.name = "twl6030";
387 twl6030_irq->irq_chip.irq_set_type = NULL;
388 twl6030_irq->irq_chip.irq_set_wake = twl6030_irq_set_wake;
Balaji T Ke8deb282009-12-14 00:25:31 +0100389
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300390 twl6030_irq->pm_nb.notifier_call = twl6030_irq_pm_notifier;
391 atomic_set(&twl6030_irq->wakeirqs, 0);
392
393 twl6030_irq->irq_domain =
394 irq_domain_add_linear(node, nr_irqs,
395 &twl6030_irq_domain_ops, twl6030_irq);
396 if (!twl6030_irq->irq_domain) {
Grygorii Strashkob32408f2013-07-25 16:15:49 +0300397 dev_err(dev, "Can't add irq_domain\n");
398 return -ENOMEM;
Balaji T Ke8deb282009-12-14 00:25:31 +0100399 }
400
Grygorii Strashkob32408f2013-07-25 16:15:49 +0300401 dev_info(dev, "PIH (irq %d) nested IRQs\n", irq_num);
Balaji T Ke8deb282009-12-14 00:25:31 +0100402
403 /* install an irq handler to demultiplex the TWL6030 interrupt */
Naga Venkata Srikanth V87343e52013-07-25 16:15:47 +0300404 status = request_threaded_irq(irq_num, NULL, twl6030_irq_thread,
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300405 IRQF_ONESHOT, "TWL6030-PIH", twl6030_irq);
Balaji T Ke8deb282009-12-14 00:25:31 +0100406 if (status < 0) {
Benoit Coussonec1a07b2012-03-02 11:11:26 +0100407 dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
Balaji T Ke8deb282009-12-14 00:25:31 +0100408 goto fail_irq;
409 }
Axel Lin862de702011-08-11 15:21:00 +0800410
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300411 twl6030_irq->twl_irq = irq_num;
412 register_pm_notifier(&twl6030_irq->pm_nb);
Grygorii Strashkob32408f2013-07-25 16:15:49 +0300413 return 0;
Balaji T Ke8deb282009-12-14 00:25:31 +0100414
Axel Lin862de702011-08-11 15:21:00 +0800415fail_irq:
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300416 irq_domain_remove(twl6030_irq->irq_domain);
Balaji T Ke8deb282009-12-14 00:25:31 +0100417 return status;
418}
419
420int twl6030_exit_irq(void)
421{
Grygorii Strashko0aa8c682013-07-25 16:15:50 +0300422 if (twl6030_irq && twl6030_irq->twl_irq) {
423 unregister_pm_notifier(&twl6030_irq->pm_nb);
424 free_irq(twl6030_irq->twl_irq, NULL);
Grygorii Strashkob32408f2013-07-25 16:15:49 +0300425 /*
426 * TODO: IRQ domain and allocated nested IRQ descriptors
427 * should be freed somehow here. Now It can't be done, because
428 * child devices will not be deleted during removing of
429 * TWL Core driver and they will still contain allocated
430 * virt IRQs in their Resources tables.
431 * The same prevents us from using devm_request_threaded_irq()
432 * in this module.
433 */
Balaji T Ke8deb282009-12-14 00:25:31 +0100434 }
Balaji T Ke8deb282009-12-14 00:25:31 +0100435 return 0;
436}
437