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Ingo Molnarcdd6c482009-09-21 12:02:48 +02001#ifndef _ASM_X86_PERF_EVENT_H
2#define _ASM_X86_PERF_EVENT_H
Thomas Gleixner003a46c2007-10-15 13:57:47 +02003
Ingo Molnareb2b8612008-12-17 09:09:13 +01004/*
Ingo Molnarcdd6c482009-09-21 12:02:48 +02005 * Performance event hw details:
Ingo Molnareb2b8612008-12-17 09:09:13 +01006 */
7
Robert Richter15c7ad52012-06-20 20:46:33 +02008#define INTEL_PMC_MAX_GENERIC 32
9#define INTEL_PMC_MAX_FIXED 3
10#define INTEL_PMC_IDX_FIXED 32
Ingo Molnareb2b8612008-12-17 09:09:13 +010011
Ingo Molnar862a1a52008-12-17 13:09:20 +010012#define X86_PMC_IDX_MAX 64
13
Ingo Molnar241771e2008-12-03 10:39:53 +010014#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
15#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
Thomas Gleixner003a46c2007-10-15 13:57:47 +020016
Ingo Molnar241771e2008-12-03 10:39:53 +010017#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
18#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
Thomas Gleixner003a46c2007-10-15 13:57:47 +020019
Robert Richtera098f442010-03-30 11:28:21 +020020#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
21#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
22#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
23#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
24#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
Gleb Natapova7b9d2c2012-02-26 16:55:40 +020025#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
Robert Richtera098f442010-03-30 11:28:21 +020026#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
27#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
28#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
29#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
30#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
Thomas Gleixner003a46c2007-10-15 13:57:47 +020031
Andi Kleen3a632cb2013-06-17 17:36:48 -070032#define HSW_IN_TX (1ULL << 32)
33#define HSW_IN_TX_CHECKPOINTED (1ULL << 33)
34
Jacob Shine2595142013-02-06 11:26:29 -060035#define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36)
Jacob Shin9f190102013-02-06 11:26:26 -060036#define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
37#define AMD64_EVENTSEL_HOSTONLY (1ULL << 41)
Joerg Roedel011af852011-10-05 14:01:17 +020038
Jacob Shine2595142013-02-06 11:26:29 -060039#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37
40#define AMD64_EVENTSEL_INT_CORE_SEL_MASK \
41 (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
42
Robert Richtera098f442010-03-30 11:28:21 +020043#define AMD64_EVENTSEL_EVENT \
44 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
45#define INTEL_ARCH_EVENT_MASK \
46 (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
Stephane Eranian1da53e02010-01-18 10:58:01 +020047
Robert Richtera098f442010-03-30 11:28:21 +020048#define X86_RAW_EVENT_MASK \
49 (ARCH_PERFMON_EVENTSEL_EVENT | \
50 ARCH_PERFMON_EVENTSEL_UMASK | \
51 ARCH_PERFMON_EVENTSEL_EDGE | \
52 ARCH_PERFMON_EVENTSEL_INV | \
53 ARCH_PERFMON_EVENTSEL_CMASK)
Andi Kleen86a04462014-08-11 21:27:10 +020054#define X86_ALL_EVENT_FLAGS \
55 (ARCH_PERFMON_EVENTSEL_EDGE | \
56 ARCH_PERFMON_EVENTSEL_INV | \
57 ARCH_PERFMON_EVENTSEL_CMASK | \
58 ARCH_PERFMON_EVENTSEL_ANY | \
59 ARCH_PERFMON_EVENTSEL_PIN_CONTROL | \
60 HSW_IN_TX | \
61 HSW_IN_TX_CHECKPOINTED)
Robert Richtera098f442010-03-30 11:28:21 +020062#define AMD64_RAW_EVENT_MASK \
63 (X86_RAW_EVENT_MASK | \
64 AMD64_EVENTSEL_EVENT)
Jacob Shine2595142013-02-06 11:26:29 -060065#define AMD64_RAW_EVENT_MASK_NB \
66 (AMD64_EVENTSEL_EVENT | \
67 ARCH_PERFMON_EVENTSEL_UMASK)
Robert Richteree5789d2011-09-21 11:30:17 +020068#define AMD64_NUM_COUNTERS 4
Robert Richterb1dc3c42012-06-20 20:46:35 +020069#define AMD64_NUM_COUNTERS_CORE 6
Jacob Shine2595142013-02-06 11:26:29 -060070#define AMD64_NUM_COUNTERS_NB 4
Stephane Eranian04a705df2009-10-06 16:42:08 +020071
Robert Richteree5789d2011-09-21 11:30:17 +020072#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
Ingo Molnar241771e2008-12-03 10:39:53 +010073#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
Robert Richteree5789d2011-09-21 11:30:17 +020074#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
Thomas Gleixner003a46c2007-10-15 13:57:47 +020075#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
Ingo Molnar241771e2008-12-03 10:39:53 +010076 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
77
Robert Richteree5789d2011-09-21 11:30:17 +020078#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
Gleb Natapovffb871b2011-11-10 14:57:26 +020079#define ARCH_PERFMON_EVENTS_COUNT 7
Thomas Gleixner003a46c2007-10-15 13:57:47 +020080
Ingo Molnareb2b8612008-12-17 09:09:13 +010081/*
82 * Intel "Architectural Performance Monitoring" CPUID
83 * detection/enumeration details:
84 */
Thomas Gleixner003a46c2007-10-15 13:57:47 +020085union cpuid10_eax {
86 struct {
87 unsigned int version_id:8;
Robert Richter948b1bb2010-03-29 18:36:50 +020088 unsigned int num_counters:8;
Thomas Gleixner003a46c2007-10-15 13:57:47 +020089 unsigned int bit_width:8;
90 unsigned int mask_length:8;
91 } split;
92 unsigned int full;
93};
94
Gleb Natapovffb871b2011-11-10 14:57:26 +020095union cpuid10_ebx {
96 struct {
97 unsigned int no_unhalted_core_cycles:1;
98 unsigned int no_instructions_retired:1;
99 unsigned int no_unhalted_reference_cycles:1;
100 unsigned int no_llc_reference:1;
101 unsigned int no_llc_misses:1;
102 unsigned int no_branch_instruction_retired:1;
103 unsigned int no_branch_misses_retired:1;
104 } split;
105 unsigned int full;
106};
107
Ingo Molnar703e9372008-12-17 10:51:15 +0100108union cpuid10_edx {
109 struct {
Livio Soarese768aee2010-06-03 15:00:31 -0400110 unsigned int num_counters_fixed:5;
111 unsigned int bit_width_fixed:8;
112 unsigned int reserved:19;
Ingo Molnar703e9372008-12-17 10:51:15 +0100113 } split;
114 unsigned int full;
115};
116
Gleb Natapovb3d94682011-11-10 14:57:27 +0200117struct x86_pmu_capability {
118 int version;
119 int num_counters_gp;
120 int num_counters_fixed;
121 int bit_width_gp;
122 int bit_width_fixed;
123 unsigned int events_mask;
124 int events_mask_len;
125};
Ingo Molnar703e9372008-12-17 10:51:15 +0100126
127/*
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200128 * Fixed-purpose performance events:
Ingo Molnar703e9372008-12-17 10:51:15 +0100129 */
130
Ingo Molnar862a1a52008-12-17 13:09:20 +0100131/*
132 * All 3 fixed-mode PMCs are configured via this single MSR:
133 */
Stephane Eraniancd09c0c2011-12-11 00:28:51 +0100134#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
Ingo Molnar862a1a52008-12-17 13:09:20 +0100135
136/*
137 * The counts are available in three separate MSRs:
138 */
139
Ingo Molnar703e9372008-12-17 10:51:15 +0100140/* Instr_Retired.Any: */
Stephane Eraniancd09c0c2011-12-11 00:28:51 +0100141#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
Robert Richter15c7ad52012-06-20 20:46:33 +0200142#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
Ingo Molnar703e9372008-12-17 10:51:15 +0100143
144/* CPU_CLK_Unhalted.Core: */
Stephane Eraniancd09c0c2011-12-11 00:28:51 +0100145#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
Robert Richter15c7ad52012-06-20 20:46:33 +0200146#define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)
Ingo Molnar703e9372008-12-17 10:51:15 +0100147
148/* CPU_CLK_Unhalted.Ref: */
Stephane Eraniancd09c0c2011-12-11 00:28:51 +0100149#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
Robert Richter15c7ad52012-06-20 20:46:33 +0200150#define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
151#define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
Ingo Molnar703e9372008-12-17 10:51:15 +0100152
Markus Metzger30dd5682009-07-21 15:56:48 +0200153/*
154 * We model BTS tracing as another fixed-mode PMC.
155 *
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200156 * We choose a value in the middle of the fixed event range, since lower
157 * values are used by actual fixed events and higher values are used
Markus Metzger30dd5682009-07-21 15:56:48 +0200158 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
159 */
Robert Richter15c7ad52012-06-20 20:46:33 +0200160#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
Markus Metzger30dd5682009-07-21 15:56:48 +0200161
Robert Richteree5789d2011-09-21 11:30:17 +0200162/*
163 * IBS cpuid feature detection
164 */
165
166#define IBS_CPUID_FEATURES 0x8000001b
167
168/*
169 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
170 * bit 0 is used to indicate the existence of IBS.
171 */
172#define IBS_CAPS_AVAIL (1U<<0)
173#define IBS_CAPS_FETCHSAM (1U<<1)
174#define IBS_CAPS_OPSAM (1U<<2)
175#define IBS_CAPS_RDWROPCNT (1U<<3)
176#define IBS_CAPS_OPCNT (1U<<4)
177#define IBS_CAPS_BRNTRGT (1U<<5)
178#define IBS_CAPS_OPCNTEXT (1U<<6)
Robert Richterd47e8232012-04-02 20:19:11 +0200179#define IBS_CAPS_RIPINVALIDCHK (1U<<7)
Robert Richteree5789d2011-09-21 11:30:17 +0200180
181#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
182 | IBS_CAPS_FETCHSAM \
183 | IBS_CAPS_OPSAM)
184
185/*
186 * IBS APIC setup
187 */
188#define IBSCTL 0x1cc
189#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
190#define IBSCTL_LVT_OFFSET_MASK 0x0F
191
Robert Richterd47e8232012-04-02 20:19:11 +0200192/* ibs fetch bits/masks */
Robert Richterb47fad32010-09-22 17:45:39 +0200193#define IBS_FETCH_RAND_EN (1ULL<<57)
194#define IBS_FETCH_VAL (1ULL<<49)
195#define IBS_FETCH_ENABLE (1ULL<<48)
196#define IBS_FETCH_CNT 0xFFFF0000ULL
197#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
Robert Richter1d6040f2010-02-25 19:40:46 +0100198
Robert Richterd47e8232012-04-02 20:19:11 +0200199/* ibs op bits/masks */
Robert Richterdb98c5f2011-12-15 17:56:39 +0100200/* lower 4 bits of the current count are ignored: */
201#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)
Robert Richterb47fad32010-09-22 17:45:39 +0200202#define IBS_OP_CNT_CTL (1ULL<<19)
203#define IBS_OP_VAL (1ULL<<18)
204#define IBS_OP_ENABLE (1ULL<<17)
205#define IBS_OP_MAX_CNT 0x0000FFFFULL
206#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
Robert Richterd47e8232012-04-02 20:19:11 +0200207#define IBS_RIP_INVALID (1ULL<<38)
Markus Metzger30dd5682009-07-21 15:56:48 +0200208
Robert Richter978da302012-05-11 11:44:59 +0200209#ifdef CONFIG_X86_LOCAL_APIC
Robert Richterb7169162011-09-21 11:30:18 +0200210extern u32 get_ibs_caps(void);
Robert Richter978da302012-05-11 11:44:59 +0200211#else
212static inline u32 get_ibs_caps(void) { return 0; }
213#endif
Robert Richterb7169162011-09-21 11:30:18 +0200214
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200215#ifdef CONFIG_PERF_EVENTS
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200216extern void perf_events_lapic_init(void);
Peter Zijlstra194002b2009-06-22 16:35:24 +0200217
Peter Zijlstraef21f682010-03-03 13:12:23 +0100218/*
Peter Zijlstrad07bdfd2012-07-10 09:42:15 +0200219 * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
220 * unused and ABI specified to be 0, so nobody should care what we do with
221 * them.
222 *
223 * EXACT - the IP points to the exact instruction that triggered the
224 * event (HW bugs exempt).
225 * VM - original X86_VM_MASK; see set_linear_ip().
Peter Zijlstraef21f682010-03-03 13:12:23 +0100226 */
227#define PERF_EFLAGS_EXACT (1UL << 3)
Peter Zijlstrad07bdfd2012-07-10 09:42:15 +0200228#define PERF_EFLAGS_VM (1UL << 5)
Peter Zijlstraef21f682010-03-03 13:12:23 +0100229
Zhang, Yanmin39447b32010-04-19 13:32:41 +0800230struct pt_regs;
231extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
232extern unsigned long perf_misc_flags(struct pt_regs *regs);
233#define perf_misc_flags(regs) perf_misc_flags(regs)
Peter Zijlstraef21f682010-03-03 13:12:23 +0100234
Frederic Weisbeckerb0f82b82010-05-20 07:47:21 +0200235#include <asm/stacktrace.h>
236
237/*
238 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
239 * and the comment with PERF_EFLAGS_EXACT.
240 */
241#define perf_arch_fetch_caller_regs(regs, __ip) { \
242 (regs)->ip = (__ip); \
243 (regs)->bp = caller_frame_pointer(); \
244 (regs)->cs = __KERNEL_CS; \
245 regs->flags = 0; \
Frederic Weisbecker9e462942011-07-02 15:00:52 +0200246 asm volatile( \
247 _ASM_MOV "%%"_ASM_SP ", %0\n" \
248 : "=m" ((regs)->sp) \
249 :: "memory" \
250 ); \
Frederic Weisbeckerb0f82b82010-05-20 07:47:21 +0200251}
252
Gleb Natapov144d31e2011-10-05 14:01:21 +0200253struct perf_guest_switch_msr {
254 unsigned msr;
255 u64 host, guest;
256};
257
258extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
Gleb Natapovb3d94682011-11-10 14:57:27 +0200259extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
Peter Zijlstrac93dc842012-06-08 14:50:50 +0200260extern void perf_check_microcode(void);
Ingo Molnar241771e2008-12-03 10:39:53 +0100261#else
Jovi Zhang35d56ca92012-07-17 10:14:41 +0800262static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
Gleb Natapov144d31e2011-10-05 14:01:21 +0200263{
264 *nr = 0;
265 return NULL;
266}
267
Gleb Natapovb3d94682011-11-10 14:57:27 +0200268static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
269{
270 memset(cap, 0, sizeof(*cap));
271}
272
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200273static inline void perf_events_lapic_init(void) { }
Peter Zijlstrac93dc842012-06-08 14:50:50 +0200274static inline void perf_check_microcode(void) { }
Ingo Molnar241771e2008-12-03 10:39:53 +0100275#endif
276
Joerg Roedel1018faa2012-02-29 14:57:32 +0100277#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
278 extern void amd_pmu_enable_virt(void);
279 extern void amd_pmu_disable_virt(void);
280#else
281 static inline void amd_pmu_enable_virt(void) { }
282 static inline void amd_pmu_disable_virt(void) { }
283#endif
284
Frederic Weisbecker91d77532012-08-07 15:20:38 +0200285#define arch_perf_out_copy_user copy_from_user_nmi
286
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200287#endif /* _ASM_X86_PERF_EVENT_H */