Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 1 | /* |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 2 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * Interrupt architecture for the GIC: |
| 9 | * |
| 10 | * o There is one Interrupt Distributor, which receives interrupts |
| 11 | * from system devices and sends them to the Interrupt Controllers. |
| 12 | * |
| 13 | * o There is one CPU Interface per CPU, which sends interrupts sent |
| 14 | * by the Distributor, and interrupts generated locally, to the |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 15 | * associated CPU. The base address of the CPU interface is usually |
| 16 | * aliased so that the same address points to different chips depending |
| 17 | * on the CPU it is accessed from. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 18 | * |
| 19 | * Note that IRQs 0-31 are special - they are local to each CPU. |
| 20 | * As such, the enable set/clear, pending set/clear and active bit |
| 21 | * registers are banked per-cpu for these sources. |
| 22 | */ |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/kernel.h> |
Rob Herring | f37a53c | 2011-10-21 17:14:27 -0500 | [diff] [blame] | 25 | #include <linux/err.h> |
Arnd Bergmann | 7e1efcf | 2011-11-01 00:28:37 +0100 | [diff] [blame] | 26 | #include <linux/module.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 27 | #include <linux/list.h> |
| 28 | #include <linux/smp.h> |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 29 | #include <linux/cpu.h> |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 30 | #include <linux/cpu_pm.h> |
Catalin Marinas | dcb86e8 | 2005-08-31 21:45:14 +0100 | [diff] [blame] | 31 | #include <linux/cpumask.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 32 | #include <linux/io.h> |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 33 | #include <linux/of.h> |
| 34 | #include <linux/of_address.h> |
| 35 | #include <linux/of_irq.h> |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 36 | #include <linux/acpi.h> |
Rob Herring | 4294f8b | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 37 | #include <linux/irqdomain.h> |
Marc Zyngier | 292b293 | 2011-07-20 16:24:14 +0100 | [diff] [blame] | 38 | #include <linux/interrupt.h> |
| 39 | #include <linux/percpu.h> |
| 40 | #include <linux/slab.h> |
Joel Porquet | 41a83e0 | 2015-07-07 17:11:46 -0400 | [diff] [blame] | 41 | #include <linux/irqchip.h> |
Catalin Marinas | de88cbb | 2013-01-18 15:31:37 +0000 | [diff] [blame] | 42 | #include <linux/irqchip/chained_irq.h> |
Rob Herring | 520f7bd | 2012-12-27 13:10:24 -0600 | [diff] [blame] | 43 | #include <linux/irqchip/arm-gic.h> |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 44 | #include <linux/irqchip/arm-gic-acpi.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 45 | |
Tomasz Figa | 29e697b | 2014-07-17 17:23:44 +0200 | [diff] [blame] | 46 | #include <asm/cputype.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 47 | #include <asm/irq.h> |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 48 | #include <asm/exception.h> |
Will Deacon | eb50439 | 2012-01-20 12:01:12 +0100 | [diff] [blame] | 49 | #include <asm/smp_plat.h> |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 50 | #include <asm/virt.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 51 | |
Marc Zyngier | d51d0af | 2014-06-30 16:01:30 +0100 | [diff] [blame] | 52 | #include "irq-gic-common.h" |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 53 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 54 | union gic_base { |
| 55 | void __iomem *common_base; |
Stephen Boyd | 6859358 | 2014-03-04 17:02:01 -0800 | [diff] [blame] | 56 | void __percpu * __iomem *percpu_base; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 57 | }; |
| 58 | |
| 59 | struct gic_chip_data { |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 60 | union gic_base dist_base; |
| 61 | union gic_base cpu_base; |
| 62 | #ifdef CONFIG_CPU_PM |
| 63 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; |
| 64 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; |
| 65 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; |
| 66 | u32 __percpu *saved_ppi_enable; |
| 67 | u32 __percpu *saved_ppi_conf; |
| 68 | #endif |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 69 | struct irq_domain *domain; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 70 | unsigned int gic_irqs; |
| 71 | #ifdef CONFIG_GIC_NON_BANKED |
| 72 | void __iomem *(*get_base)(union gic_base *); |
| 73 | #endif |
| 74 | }; |
| 75 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 76 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 77 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 78 | /* |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 79 | * The GIC mapping of CPU interfaces does not necessarily match |
| 80 | * the logical CPU numbering. Let's use a mapping as returned |
| 81 | * by the GIC itself. |
| 82 | */ |
| 83 | #define NR_GIC_CPU_IF 8 |
| 84 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; |
| 85 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 86 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
| 87 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 88 | #ifndef MAX_GIC_NR |
| 89 | #define MAX_GIC_NR 1 |
| 90 | #endif |
| 91 | |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 92 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 93 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 94 | #ifdef CONFIG_GIC_NON_BANKED |
| 95 | static void __iomem *gic_get_percpu_base(union gic_base *base) |
| 96 | { |
Christoph Lameter | 513d1a2 | 2014-09-02 10:00:07 -0500 | [diff] [blame] | 97 | return raw_cpu_read(*base->percpu_base); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | static void __iomem *gic_get_common_base(union gic_base *base) |
| 101 | { |
| 102 | return base->common_base; |
| 103 | } |
| 104 | |
| 105 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) |
| 106 | { |
| 107 | return data->get_base(&data->dist_base); |
| 108 | } |
| 109 | |
| 110 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) |
| 111 | { |
| 112 | return data->get_base(&data->cpu_base); |
| 113 | } |
| 114 | |
| 115 | static inline void gic_set_base_accessor(struct gic_chip_data *data, |
| 116 | void __iomem *(*f)(union gic_base *)) |
| 117 | { |
| 118 | data->get_base = f; |
| 119 | } |
| 120 | #else |
| 121 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) |
| 122 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) |
Sachin Kamat | 46f101d | 2013-03-13 15:05:15 +0530 | [diff] [blame] | 123 | #define gic_set_base_accessor(d, f) |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 124 | #endif |
| 125 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 126 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 127 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 128 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 129 | return gic_data_dist_base(gic_data); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 130 | } |
| 131 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 132 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 133 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 134 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 135 | return gic_data_cpu_base(gic_data); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 136 | } |
| 137 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 138 | static inline unsigned int gic_irq(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 139 | { |
Rob Herring | 4294f8b | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 140 | return d->hwirq; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 141 | } |
| 142 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 143 | /* |
| 144 | * Routines to acknowledge, disable and enable interrupts |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 145 | */ |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 146 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 147 | { |
Rob Herring | 4294f8b | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 148 | u32 mask = 1 << (gic_irq(d) % 32); |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 149 | writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); |
| 150 | } |
| 151 | |
| 152 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
| 153 | { |
| 154 | u32 mask = 1 << (gic_irq(d) % 32); |
| 155 | return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); |
| 156 | } |
| 157 | |
| 158 | static void gic_mask_irq(struct irq_data *d) |
| 159 | { |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 160 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 161 | } |
| 162 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 163 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
| 164 | { |
| 165 | gic_mask_irq(d); |
| 166 | } |
| 167 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 168 | static void gic_unmask_irq(struct irq_data *d) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 169 | { |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 170 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 171 | } |
| 172 | |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 173 | static void gic_eoi_irq(struct irq_data *d) |
| 174 | { |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 175 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 176 | } |
| 177 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 178 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
| 179 | { |
| 180 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); |
| 181 | } |
| 182 | |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 183 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
| 184 | enum irqchip_irq_state which, bool val) |
| 185 | { |
| 186 | u32 reg; |
| 187 | |
| 188 | switch (which) { |
| 189 | case IRQCHIP_STATE_PENDING: |
| 190 | reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; |
| 191 | break; |
| 192 | |
| 193 | case IRQCHIP_STATE_ACTIVE: |
| 194 | reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; |
| 195 | break; |
| 196 | |
| 197 | case IRQCHIP_STATE_MASKED: |
| 198 | reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; |
| 199 | break; |
| 200 | |
| 201 | default: |
| 202 | return -EINVAL; |
| 203 | } |
| 204 | |
| 205 | gic_poke_irq(d, reg); |
| 206 | return 0; |
| 207 | } |
| 208 | |
| 209 | static int gic_irq_get_irqchip_state(struct irq_data *d, |
| 210 | enum irqchip_irq_state which, bool *val) |
| 211 | { |
| 212 | switch (which) { |
| 213 | case IRQCHIP_STATE_PENDING: |
| 214 | *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); |
| 215 | break; |
| 216 | |
| 217 | case IRQCHIP_STATE_ACTIVE: |
| 218 | *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); |
| 219 | break; |
| 220 | |
| 221 | case IRQCHIP_STATE_MASKED: |
| 222 | *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); |
| 223 | break; |
| 224 | |
| 225 | default: |
| 226 | return -EINVAL; |
| 227 | } |
| 228 | |
| 229 | return 0; |
| 230 | } |
| 231 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 232 | static int gic_set_type(struct irq_data *d, unsigned int type) |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 233 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 234 | void __iomem *base = gic_dist_base(d); |
| 235 | unsigned int gicirq = gic_irq(d); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 236 | |
| 237 | /* Interrupt configuration for SGIs can't be changed */ |
| 238 | if (gicirq < 16) |
| 239 | return -EINVAL; |
| 240 | |
Liviu Dudau | fb7e7de | 2015-01-20 16:52:59 +0000 | [diff] [blame] | 241 | /* SPIs have restrictions on the supported types */ |
| 242 | if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && |
| 243 | type != IRQ_TYPE_EDGE_RISING) |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 244 | return -EINVAL; |
| 245 | |
Marc Zyngier | 1dcc73d | 2015-04-22 18:20:04 +0100 | [diff] [blame] | 246 | return gic_configure_irq(gicirq, type, base, NULL); |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 247 | } |
| 248 | |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 249 | #ifdef CONFIG_SMP |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 250 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
| 251 | bool force) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 252 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 253 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
Thomas Gleixner | ffde1de | 2014-04-16 14:36:44 +0000 | [diff] [blame] | 254 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 255 | u32 val, mask, bit; |
Marc Zyngier | cf61387 | 2015-03-06 16:37:44 +0000 | [diff] [blame] | 256 | unsigned long flags; |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 257 | |
Thomas Gleixner | ffde1de | 2014-04-16 14:36:44 +0000 | [diff] [blame] | 258 | if (!force) |
| 259 | cpu = cpumask_any_and(mask_val, cpu_online_mask); |
| 260 | else |
| 261 | cpu = cpumask_first(mask_val); |
| 262 | |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 263 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 264 | return -EINVAL; |
| 265 | |
Marc Zyngier | cf61387 | 2015-03-06 16:37:44 +0000 | [diff] [blame] | 266 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 267 | mask = 0xff << shift; |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 268 | bit = gic_cpu_map[cpu] << shift; |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 269 | val = readl_relaxed(reg) & ~mask; |
| 270 | writel_relaxed(val | bit, reg); |
Marc Zyngier | cf61387 | 2015-03-06 16:37:44 +0000 | [diff] [blame] | 271 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 272 | |
Russell King | 5dfc54e | 2011-07-21 15:00:57 +0100 | [diff] [blame] | 273 | return IRQ_SET_MASK_OK; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 274 | } |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 275 | #endif |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 276 | |
Stephen Boyd | 8783dd3 | 2014-03-04 16:40:30 -0800 | [diff] [blame] | 277 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 278 | { |
| 279 | u32 irqstat, irqnr; |
| 280 | struct gic_chip_data *gic = &gic_data[0]; |
| 281 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
| 282 | |
| 283 | do { |
| 284 | irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); |
Haojian Zhuang | b8802f7 | 2014-05-11 16:05:58 +0800 | [diff] [blame] | 285 | irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 286 | |
| 287 | if (likely(irqnr > 15 && irqnr < 1021)) { |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 288 | if (static_key_true(&supports_deactivate)) |
| 289 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); |
Marc Zyngier | 60031b4 | 2014-08-26 11:03:20 +0100 | [diff] [blame] | 290 | handle_domain_irq(gic->domain, irqnr, regs); |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 291 | continue; |
| 292 | } |
| 293 | if (irqnr < 16) { |
| 294 | writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 295 | if (static_key_true(&supports_deactivate)) |
| 296 | writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 297 | #ifdef CONFIG_SMP |
| 298 | handle_IPI(irqnr, regs); |
| 299 | #endif |
| 300 | continue; |
| 301 | } |
| 302 | break; |
| 303 | } while (1); |
| 304 | } |
| 305 | |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 306 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 307 | { |
Jiang Liu | 5b29264 | 2015-06-04 12:13:20 +0800 | [diff] [blame] | 308 | struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); |
| 309 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 310 | unsigned int cascade_irq, gic_irq; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 311 | unsigned long status; |
| 312 | |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 313 | chained_irq_enter(chip, desc); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 314 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 315 | raw_spin_lock(&irq_controller_lock); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 316 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 317 | raw_spin_unlock(&irq_controller_lock); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 318 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 319 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
| 320 | if (gic_irq == GICC_INT_SPURIOUS) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 321 | goto out; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 322 | |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 323 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
| 324 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) |
Catalin Marinas | aec0095 | 2013-01-14 17:53:39 +0000 | [diff] [blame] | 325 | handle_bad_irq(cascade_irq, desc); |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 326 | else |
| 327 | generic_handle_irq(cascade_irq); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 328 | |
| 329 | out: |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 330 | chained_irq_exit(chip, desc); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 331 | } |
| 332 | |
David Brownell | 38c677c | 2006-08-01 22:26:25 +0100 | [diff] [blame] | 333 | static struct irq_chip gic_chip = { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 334 | .name = "GIC", |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 335 | .irq_mask = gic_mask_irq, |
| 336 | .irq_unmask = gic_unmask_irq, |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 337 | .irq_eoi = gic_eoi_irq, |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 338 | .irq_set_type = gic_set_type, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 339 | #ifdef CONFIG_SMP |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 340 | .irq_set_affinity = gic_set_affinity, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 341 | #endif |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 342 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
| 343 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, |
Sudeep Holla | aec89ef | 2015-07-15 15:38:28 +0100 | [diff] [blame] | 344 | .flags = IRQCHIP_SET_TYPE_MASKED | |
| 345 | IRQCHIP_SKIP_SET_WAKE | |
| 346 | IRQCHIP_MASK_ON_SUSPEND, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 347 | }; |
| 348 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 349 | static struct irq_chip gic_eoimode1_chip = { |
| 350 | .name = "GICv2", |
| 351 | .irq_mask = gic_eoimode1_mask_irq, |
| 352 | .irq_unmask = gic_unmask_irq, |
| 353 | .irq_eoi = gic_eoimode1_eoi_irq, |
| 354 | .irq_set_type = gic_set_type, |
| 355 | #ifdef CONFIG_SMP |
| 356 | .irq_set_affinity = gic_set_affinity, |
| 357 | #endif |
| 358 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
| 359 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, |
| 360 | .flags = IRQCHIP_SET_TYPE_MASKED | |
| 361 | IRQCHIP_SKIP_SET_WAKE | |
| 362 | IRQCHIP_MASK_ON_SUSPEND, |
| 363 | }; |
| 364 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 365 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
| 366 | { |
| 367 | if (gic_nr >= MAX_GIC_NR) |
| 368 | BUG(); |
Thomas Gleixner | 4d83fcf | 2015-06-21 21:10:53 +0200 | [diff] [blame] | 369 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, |
| 370 | &gic_data[gic_nr]); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 371 | } |
| 372 | |
Russell King | 2bb3135 | 2013-01-30 23:49:57 +0000 | [diff] [blame] | 373 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
| 374 | { |
| 375 | void __iomem *base = gic_data_dist_base(gic); |
| 376 | u32 mask, i; |
| 377 | |
| 378 | for (i = mask = 0; i < 32; i += 4) { |
| 379 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); |
| 380 | mask |= mask >> 16; |
| 381 | mask |= mask >> 8; |
| 382 | if (mask) |
| 383 | break; |
| 384 | } |
| 385 | |
Stephen Boyd | 6e3aca4 | 2015-03-11 23:21:31 -0700 | [diff] [blame] | 386 | if (!mask && num_possible_cpus() > 1) |
Russell King | 2bb3135 | 2013-01-30 23:49:57 +0000 | [diff] [blame] | 387 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); |
| 388 | |
| 389 | return mask; |
| 390 | } |
| 391 | |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 392 | static void gic_cpu_if_up(struct gic_chip_data *gic) |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 393 | { |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 394 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 395 | u32 bypass = 0; |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 396 | u32 mode = 0; |
| 397 | |
| 398 | if (static_key_true(&supports_deactivate)) |
| 399 | mode = GIC_CPU_CTRL_EOImodeNS; |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 400 | |
| 401 | /* |
| 402 | * Preserve bypass disable bits to be written back later |
| 403 | */ |
| 404 | bypass = readl(cpu_base + GIC_CPU_CTRL); |
| 405 | bypass &= GICC_DIS_BYPASS_MASK; |
| 406 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 407 | writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 408 | } |
| 409 | |
| 410 | |
Rob Herring | 4294f8b | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 411 | static void __init gic_dist_init(struct gic_chip_data *gic) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 412 | { |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 413 | unsigned int i; |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 414 | u32 cpumask; |
Rob Herring | 4294f8b | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 415 | unsigned int gic_irqs = gic->gic_irqs; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 416 | void __iomem *base = gic_data_dist_base(gic); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 417 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 418 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 419 | |
| 420 | /* |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 421 | * Set all global interrupts to this CPU only. |
| 422 | */ |
Russell King | 2bb3135 | 2013-01-30 23:49:57 +0000 | [diff] [blame] | 423 | cpumask = gic_get_cpumask(gic); |
| 424 | cpumask |= cpumask << 8; |
| 425 | cpumask |= cpumask << 16; |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 426 | for (i = 32; i < gic_irqs; i += 4) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 427 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 428 | |
Marc Zyngier | d51d0af | 2014-06-30 16:01:30 +0100 | [diff] [blame] | 429 | gic_dist_config(base, gic_irqs, NULL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 430 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 431 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 432 | } |
| 433 | |
Paul Gortmaker | 8c37bb3 | 2013-06-19 11:32:08 -0400 | [diff] [blame] | 434 | static void gic_cpu_init(struct gic_chip_data *gic) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 435 | { |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 436 | void __iomem *dist_base = gic_data_dist_base(gic); |
| 437 | void __iomem *base = gic_data_cpu_base(gic); |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 438 | unsigned int cpu_mask, cpu = smp_processor_id(); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 439 | int i; |
| 440 | |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 441 | /* |
Jon Hunter | 567e5a0 | 2015-07-31 09:44:11 +0100 | [diff] [blame] | 442 | * Setting up the CPU map is only relevant for the primary GIC |
| 443 | * because any nested/secondary GICs do not directly interface |
| 444 | * with the CPU(s). |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 445 | */ |
Jon Hunter | 567e5a0 | 2015-07-31 09:44:11 +0100 | [diff] [blame] | 446 | if (gic == &gic_data[0]) { |
| 447 | /* |
| 448 | * Get what the GIC says our CPU mask is. |
| 449 | */ |
| 450 | BUG_ON(cpu >= NR_GIC_CPU_IF); |
| 451 | cpu_mask = gic_get_cpumask(gic); |
| 452 | gic_cpu_map[cpu] = cpu_mask; |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 453 | |
Jon Hunter | 567e5a0 | 2015-07-31 09:44:11 +0100 | [diff] [blame] | 454 | /* |
| 455 | * Clear our mask from the other map entries in case they're |
| 456 | * still undefined. |
| 457 | */ |
| 458 | for (i = 0; i < NR_GIC_CPU_IF; i++) |
| 459 | if (i != cpu) |
| 460 | gic_cpu_map[i] &= ~cpu_mask; |
| 461 | } |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 462 | |
Marc Zyngier | d51d0af | 2014-06-30 16:01:30 +0100 | [diff] [blame] | 463 | gic_cpu_config(dist_base, NULL); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 464 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 465 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 466 | gic_cpu_if_up(gic); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 467 | } |
| 468 | |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 469 | int gic_cpu_if_down(unsigned int gic_nr) |
Nicolas Pitre | 10d9eb8 | 2013-03-19 23:59:04 -0400 | [diff] [blame] | 470 | { |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 471 | void __iomem *cpu_base; |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 472 | u32 val = 0; |
| 473 | |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 474 | if (gic_nr >= MAX_GIC_NR) |
| 475 | return -EINVAL; |
| 476 | |
| 477 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 478 | val = readl(cpu_base + GIC_CPU_CTRL); |
| 479 | val &= ~GICC_ENABLE; |
| 480 | writel_relaxed(val, cpu_base + GIC_CPU_CTRL); |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 481 | |
| 482 | return 0; |
Nicolas Pitre | 10d9eb8 | 2013-03-19 23:59:04 -0400 | [diff] [blame] | 483 | } |
| 484 | |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 485 | #ifdef CONFIG_CPU_PM |
| 486 | /* |
| 487 | * Saves the GIC distributor registers during suspend or idle. Must be called |
| 488 | * with interrupts disabled but before powering down the GIC. After calling |
| 489 | * this function, no interrupts will be delivered by the GIC, and another |
| 490 | * platform-specific wakeup source must be enabled. |
| 491 | */ |
| 492 | static void gic_dist_save(unsigned int gic_nr) |
| 493 | { |
| 494 | unsigned int gic_irqs; |
| 495 | void __iomem *dist_base; |
| 496 | int i; |
| 497 | |
| 498 | if (gic_nr >= MAX_GIC_NR) |
| 499 | BUG(); |
| 500 | |
| 501 | gic_irqs = gic_data[gic_nr].gic_irqs; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 502 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 503 | |
| 504 | if (!dist_base) |
| 505 | return; |
| 506 | |
| 507 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) |
| 508 | gic_data[gic_nr].saved_spi_conf[i] = |
| 509 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); |
| 510 | |
| 511 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
| 512 | gic_data[gic_nr].saved_spi_target[i] = |
| 513 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); |
| 514 | |
| 515 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) |
| 516 | gic_data[gic_nr].saved_spi_enable[i] = |
| 517 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 518 | } |
| 519 | |
| 520 | /* |
| 521 | * Restores the GIC distributor registers during resume or when coming out of |
| 522 | * idle. Must be called before enabling interrupts. If a level interrupt |
| 523 | * that occured while the GIC was suspended is still present, it will be |
| 524 | * handled normally, but any edge interrupts that occured will not be seen by |
| 525 | * the GIC and need to be handled by the platform-specific wakeup source. |
| 526 | */ |
| 527 | static void gic_dist_restore(unsigned int gic_nr) |
| 528 | { |
| 529 | unsigned int gic_irqs; |
| 530 | unsigned int i; |
| 531 | void __iomem *dist_base; |
| 532 | |
| 533 | if (gic_nr >= MAX_GIC_NR) |
| 534 | BUG(); |
| 535 | |
| 536 | gic_irqs = gic_data[gic_nr].gic_irqs; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 537 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 538 | |
| 539 | if (!dist_base) |
| 540 | return; |
| 541 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 542 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 543 | |
| 544 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) |
| 545 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], |
| 546 | dist_base + GIC_DIST_CONFIG + i * 4); |
| 547 | |
| 548 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 549 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 550 | dist_base + GIC_DIST_PRI + i * 4); |
| 551 | |
| 552 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
| 553 | writel_relaxed(gic_data[gic_nr].saved_spi_target[i], |
| 554 | dist_base + GIC_DIST_TARGET + i * 4); |
| 555 | |
| 556 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) |
| 557 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], |
| 558 | dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 559 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 560 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 561 | } |
| 562 | |
| 563 | static void gic_cpu_save(unsigned int gic_nr) |
| 564 | { |
| 565 | int i; |
| 566 | u32 *ptr; |
| 567 | void __iomem *dist_base; |
| 568 | void __iomem *cpu_base; |
| 569 | |
| 570 | if (gic_nr >= MAX_GIC_NR) |
| 571 | BUG(); |
| 572 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 573 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
| 574 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 575 | |
| 576 | if (!dist_base || !cpu_base) |
| 577 | return; |
| 578 | |
Christoph Lameter | 532d0d0 | 2014-08-17 12:30:39 -0500 | [diff] [blame] | 579 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 580 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
| 581 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 582 | |
Christoph Lameter | 532d0d0 | 2014-08-17 12:30:39 -0500 | [diff] [blame] | 583 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 584 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
| 585 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); |
| 586 | |
| 587 | } |
| 588 | |
| 589 | static void gic_cpu_restore(unsigned int gic_nr) |
| 590 | { |
| 591 | int i; |
| 592 | u32 *ptr; |
| 593 | void __iomem *dist_base; |
| 594 | void __iomem *cpu_base; |
| 595 | |
| 596 | if (gic_nr >= MAX_GIC_NR) |
| 597 | BUG(); |
| 598 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 599 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
| 600 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 601 | |
| 602 | if (!dist_base || !cpu_base) |
| 603 | return; |
| 604 | |
Christoph Lameter | 532d0d0 | 2014-08-17 12:30:39 -0500 | [diff] [blame] | 605 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 606 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
| 607 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 608 | |
Christoph Lameter | 532d0d0 | 2014-08-17 12:30:39 -0500 | [diff] [blame] | 609 | ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 610 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
| 611 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); |
| 612 | |
| 613 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 614 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
| 615 | dist_base + GIC_DIST_PRI + i * 4); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 616 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 617 | writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 618 | gic_cpu_if_up(&gic_data[gic_nr]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 619 | } |
| 620 | |
| 621 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) |
| 622 | { |
| 623 | int i; |
| 624 | |
| 625 | for (i = 0; i < MAX_GIC_NR; i++) { |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 626 | #ifdef CONFIG_GIC_NON_BANKED |
| 627 | /* Skip over unused GICs */ |
| 628 | if (!gic_data[i].get_base) |
| 629 | continue; |
| 630 | #endif |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 631 | switch (cmd) { |
| 632 | case CPU_PM_ENTER: |
| 633 | gic_cpu_save(i); |
| 634 | break; |
| 635 | case CPU_PM_ENTER_FAILED: |
| 636 | case CPU_PM_EXIT: |
| 637 | gic_cpu_restore(i); |
| 638 | break; |
| 639 | case CPU_CLUSTER_PM_ENTER: |
| 640 | gic_dist_save(i); |
| 641 | break; |
| 642 | case CPU_CLUSTER_PM_ENTER_FAILED: |
| 643 | case CPU_CLUSTER_PM_EXIT: |
| 644 | gic_dist_restore(i); |
| 645 | break; |
| 646 | } |
| 647 | } |
| 648 | |
| 649 | return NOTIFY_OK; |
| 650 | } |
| 651 | |
| 652 | static struct notifier_block gic_notifier_block = { |
| 653 | .notifier_call = gic_notifier, |
| 654 | }; |
| 655 | |
| 656 | static void __init gic_pm_init(struct gic_chip_data *gic) |
| 657 | { |
| 658 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, |
| 659 | sizeof(u32)); |
| 660 | BUG_ON(!gic->saved_ppi_enable); |
| 661 | |
| 662 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, |
| 663 | sizeof(u32)); |
| 664 | BUG_ON(!gic->saved_ppi_conf); |
| 665 | |
Marc Zyngier | abdd7b9 | 2011-11-25 17:58:19 +0100 | [diff] [blame] | 666 | if (gic == &gic_data[0]) |
| 667 | cpu_pm_register_notifier(&gic_notifier_block); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 668 | } |
| 669 | #else |
| 670 | static void __init gic_pm_init(struct gic_chip_data *gic) |
| 671 | { |
| 672 | } |
| 673 | #endif |
| 674 | |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 675 | #ifdef CONFIG_SMP |
Stephen Boyd | 6859358 | 2014-03-04 17:02:01 -0800 | [diff] [blame] | 676 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 677 | { |
| 678 | int cpu; |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 679 | unsigned long flags, map = 0; |
| 680 | |
| 681 | raw_spin_lock_irqsave(&irq_controller_lock, flags); |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 682 | |
| 683 | /* Convert our logical CPU mask into a physical one. */ |
| 684 | for_each_cpu(cpu, mask) |
Javi Merino | 91bdf0d | 2013-02-19 13:52:22 +0000 | [diff] [blame] | 685 | map |= gic_cpu_map[cpu]; |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 686 | |
| 687 | /* |
| 688 | * Ensure that stores to Normal memory are visible to the |
Will Deacon | 8adbf57 | 2014-02-20 17:42:07 +0000 | [diff] [blame] | 689 | * other CPUs before they observe us issuing the IPI. |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 690 | */ |
Will Deacon | 8adbf57 | 2014-02-20 17:42:07 +0000 | [diff] [blame] | 691 | dmb(ishst); |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 692 | |
| 693 | /* this always happens on GIC0 */ |
| 694 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 695 | |
| 696 | raw_spin_unlock_irqrestore(&irq_controller_lock, flags); |
| 697 | } |
| 698 | #endif |
| 699 | |
| 700 | #ifdef CONFIG_BL_SWITCHER |
| 701 | /* |
Nicolas Pitre | 14d2ca6 | 2012-11-28 18:48:19 -0500 | [diff] [blame] | 702 | * gic_send_sgi - send a SGI directly to given CPU interface number |
| 703 | * |
| 704 | * cpu_id: the ID for the destination CPU interface |
| 705 | * irq: the IPI number to send a SGI for |
| 706 | */ |
| 707 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) |
| 708 | { |
| 709 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); |
| 710 | cpu_id = 1 << cpu_id; |
| 711 | /* this always happens on GIC0 */ |
| 712 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); |
| 713 | } |
| 714 | |
| 715 | /* |
Nicolas Pitre | ed96762 | 2012-07-05 21:33:26 -0400 | [diff] [blame] | 716 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU |
| 717 | * |
| 718 | * @cpu: the logical CPU number to get the GIC ID for. |
| 719 | * |
| 720 | * Return the CPU interface ID for the given logical CPU number, |
| 721 | * or -1 if the CPU number is too large or the interface ID is |
| 722 | * unknown (more than one bit set). |
| 723 | */ |
| 724 | int gic_get_cpu_id(unsigned int cpu) |
| 725 | { |
| 726 | unsigned int cpu_bit; |
| 727 | |
| 728 | if (cpu >= NR_GIC_CPU_IF) |
| 729 | return -1; |
| 730 | cpu_bit = gic_cpu_map[cpu]; |
| 731 | if (cpu_bit & (cpu_bit - 1)) |
| 732 | return -1; |
| 733 | return __ffs(cpu_bit); |
| 734 | } |
| 735 | |
| 736 | /* |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 737 | * gic_migrate_target - migrate IRQs to another CPU interface |
| 738 | * |
| 739 | * @new_cpu_id: the CPU target ID to migrate IRQs to |
| 740 | * |
| 741 | * Migrate all peripheral interrupts with a target matching the current CPU |
| 742 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping |
| 743 | * is also updated. Targets to other CPU interfaces are unchanged. |
| 744 | * This must be called with IRQs locally disabled. |
| 745 | */ |
| 746 | void gic_migrate_target(unsigned int new_cpu_id) |
| 747 | { |
| 748 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; |
| 749 | void __iomem *dist_base; |
| 750 | int i, ror_val, cpu = smp_processor_id(); |
| 751 | u32 val, cur_target_mask, active_mask; |
| 752 | |
| 753 | if (gic_nr >= MAX_GIC_NR) |
| 754 | BUG(); |
| 755 | |
| 756 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
| 757 | if (!dist_base) |
| 758 | return; |
| 759 | gic_irqs = gic_data[gic_nr].gic_irqs; |
| 760 | |
| 761 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); |
| 762 | cur_target_mask = 0x01010101 << cur_cpu_id; |
| 763 | ror_val = (cur_cpu_id - new_cpu_id) & 31; |
| 764 | |
| 765 | raw_spin_lock(&irq_controller_lock); |
| 766 | |
| 767 | /* Update the target interface for this logical CPU */ |
| 768 | gic_cpu_map[cpu] = 1 << new_cpu_id; |
| 769 | |
| 770 | /* |
| 771 | * Find all the peripheral interrupts targetting the current |
| 772 | * CPU interface and migrate them to the new CPU interface. |
| 773 | * We skip DIST_TARGET 0 to 7 as they are read-only. |
| 774 | */ |
| 775 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { |
| 776 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); |
| 777 | active_mask = val & cur_target_mask; |
| 778 | if (active_mask) { |
| 779 | val &= ~active_mask; |
| 780 | val |= ror32(active_mask, ror_val); |
| 781 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); |
| 782 | } |
| 783 | } |
| 784 | |
| 785 | raw_spin_unlock(&irq_controller_lock); |
| 786 | |
| 787 | /* |
| 788 | * Now let's migrate and clear any potential SGIs that might be |
| 789 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET |
| 790 | * is a banked register, we can only forward the SGI using |
| 791 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux |
| 792 | * doesn't use that information anyway. |
| 793 | * |
| 794 | * For the same reason we do not adjust SGI source information |
| 795 | * for previously sent SGIs by us to other CPUs either. |
| 796 | */ |
| 797 | for (i = 0; i < 16; i += 4) { |
| 798 | int j; |
| 799 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); |
| 800 | if (!val) |
| 801 | continue; |
| 802 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); |
| 803 | for (j = i; j < i + 4; j++) { |
| 804 | if (val & 0xff) |
| 805 | writel_relaxed((1 << (new_cpu_id + 16)) | j, |
| 806 | dist_base + GIC_DIST_SOFTINT); |
| 807 | val >>= 8; |
| 808 | } |
| 809 | } |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 810 | } |
Nicolas Pitre | eeb4465 | 2012-11-28 18:17:25 -0500 | [diff] [blame] | 811 | |
| 812 | /* |
| 813 | * gic_get_sgir_physaddr - get the physical address for the SGI register |
| 814 | * |
| 815 | * REturn the physical address of the SGI register to be used |
| 816 | * by some early assembly code when the kernel is not yet available. |
| 817 | */ |
| 818 | static unsigned long gic_dist_physaddr; |
| 819 | |
| 820 | unsigned long gic_get_sgir_physaddr(void) |
| 821 | { |
| 822 | if (!gic_dist_physaddr) |
| 823 | return 0; |
| 824 | return gic_dist_physaddr + GIC_DIST_SOFTINT; |
| 825 | } |
| 826 | |
| 827 | void __init gic_init_physaddr(struct device_node *node) |
| 828 | { |
| 829 | struct resource res; |
| 830 | if (of_address_to_resource(node, 0, &res) == 0) { |
| 831 | gic_dist_physaddr = res.start; |
| 832 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); |
| 833 | } |
| 834 | } |
| 835 | |
| 836 | #else |
| 837 | #define gic_init_physaddr(node) do { } while (0) |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 838 | #endif |
| 839 | |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 840 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
| 841 | irq_hw_number_t hw) |
| 842 | { |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 843 | struct irq_chip *chip = &gic_chip; |
| 844 | |
| 845 | if (static_key_true(&supports_deactivate)) { |
| 846 | if (d->host_data == (void *)&gic_data[0]) |
| 847 | chip = &gic_eoimode1_chip; |
| 848 | } |
| 849 | |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 850 | if (hw < 32) { |
| 851 | irq_set_percpu_devid(irq); |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 852 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 853 | handle_percpu_devid_irq, NULL, NULL); |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 854 | set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); |
| 855 | } else { |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 856 | irq_domain_set_info(d, irq, hw, chip, d->host_data, |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 857 | handle_fasteoi_irq, NULL, NULL); |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 858 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
| 859 | } |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 860 | return 0; |
| 861 | } |
| 862 | |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 863 | static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) |
| 864 | { |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 865 | } |
| 866 | |
Grant Likely | 7bb69ba | 2012-02-14 14:06:48 -0700 | [diff] [blame] | 867 | static int gic_irq_domain_xlate(struct irq_domain *d, |
| 868 | struct device_node *controller, |
| 869 | const u32 *intspec, unsigned int intsize, |
| 870 | unsigned long *out_hwirq, unsigned int *out_type) |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 871 | { |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 872 | unsigned long ret = 0; |
| 873 | |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 874 | if (d->of_node != controller) |
| 875 | return -EINVAL; |
| 876 | if (intsize < 3) |
| 877 | return -EINVAL; |
| 878 | |
| 879 | /* Get the interrupt number and add 16 to skip over SGIs */ |
| 880 | *out_hwirq = intspec[1] + 16; |
| 881 | |
| 882 | /* For SPIs, we need to add 16 more to get the GIC irq ID number */ |
Marc Zyngier | a5561c3 | 2015-03-11 15:43:46 +0000 | [diff] [blame] | 883 | if (!intspec[0]) |
| 884 | *out_hwirq += 16; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 885 | |
| 886 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 887 | |
| 888 | return ret; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 889 | } |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 890 | |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 891 | #ifdef CONFIG_SMP |
Paul Gortmaker | 8c37bb3 | 2013-06-19 11:32:08 -0400 | [diff] [blame] | 892 | static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, |
| 893 | void *hcpu) |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 894 | { |
Shawn Guo | 8b6fd65 | 2013-06-12 19:30:27 +0800 | [diff] [blame] | 895 | if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 896 | gic_cpu_init(&gic_data[0]); |
| 897 | return NOTIFY_OK; |
| 898 | } |
| 899 | |
| 900 | /* |
| 901 | * Notifier for enabling the GIC CPU interface. Set an arbitrarily high |
| 902 | * priority because the GIC needs to be up before the ARM generic timers. |
| 903 | */ |
Paul Gortmaker | 8c37bb3 | 2013-06-19 11:32:08 -0400 | [diff] [blame] | 904 | static struct notifier_block gic_cpu_notifier = { |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 905 | .notifier_call = gic_secondary_init, |
| 906 | .priority = 100, |
| 907 | }; |
| 908 | #endif |
| 909 | |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 910 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
| 911 | unsigned int nr_irqs, void *arg) |
| 912 | { |
| 913 | int i, ret; |
| 914 | irq_hw_number_t hwirq; |
| 915 | unsigned int type = IRQ_TYPE_NONE; |
| 916 | struct of_phandle_args *irq_data = arg; |
| 917 | |
| 918 | ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, |
| 919 | irq_data->args_count, &hwirq, &type); |
| 920 | if (ret) |
| 921 | return ret; |
| 922 | |
| 923 | for (i = 0; i < nr_irqs; i++) |
| 924 | gic_irq_domain_map(domain, virq + i, hwirq + i); |
| 925 | |
| 926 | return 0; |
| 927 | } |
| 928 | |
| 929 | static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { |
| 930 | .xlate = gic_irq_domain_xlate, |
| 931 | .alloc = gic_irq_domain_alloc, |
| 932 | .free = irq_domain_free_irqs_top, |
| 933 | }; |
| 934 | |
Stephen Boyd | 6859358 | 2014-03-04 17:02:01 -0800 | [diff] [blame] | 935 | static const struct irq_domain_ops gic_irq_domain_ops = { |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 936 | .map = gic_irq_domain_map, |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 937 | .unmap = gic_irq_domain_unmap, |
Grant Likely | 7bb69ba | 2012-02-14 14:06:48 -0700 | [diff] [blame] | 938 | .xlate = gic_irq_domain_xlate, |
Rob Herring | 4294f8b | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 939 | }; |
| 940 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 941 | void __init gic_init_bases(unsigned int gic_nr, int irq_start, |
| 942 | void __iomem *dist_base, void __iomem *cpu_base, |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 943 | u32 percpu_offset, struct device_node *node) |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 944 | { |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 945 | irq_hw_number_t hwirq_base; |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 946 | struct gic_chip_data *gic; |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 947 | int gic_irqs, irq_base, i; |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 948 | |
| 949 | BUG_ON(gic_nr >= MAX_GIC_NR); |
| 950 | |
| 951 | gic = &gic_data[gic_nr]; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 952 | #ifdef CONFIG_GIC_NON_BANKED |
| 953 | if (percpu_offset) { /* Frankein-GIC without banked registers... */ |
| 954 | unsigned int cpu; |
| 955 | |
| 956 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); |
| 957 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); |
| 958 | if (WARN_ON(!gic->dist_base.percpu_base || |
| 959 | !gic->cpu_base.percpu_base)) { |
| 960 | free_percpu(gic->dist_base.percpu_base); |
| 961 | free_percpu(gic->cpu_base.percpu_base); |
| 962 | return; |
| 963 | } |
| 964 | |
| 965 | for_each_possible_cpu(cpu) { |
Tomasz Figa | 29e697b | 2014-07-17 17:23:44 +0200 | [diff] [blame] | 966 | u32 mpidr = cpu_logical_map(cpu); |
| 967 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); |
| 968 | unsigned long offset = percpu_offset * core_id; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 969 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; |
| 970 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; |
| 971 | } |
| 972 | |
| 973 | gic_set_base_accessor(gic, gic_get_percpu_base); |
| 974 | } else |
| 975 | #endif |
| 976 | { /* Normal, sane GIC... */ |
| 977 | WARN(percpu_offset, |
| 978 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", |
| 979 | percpu_offset); |
| 980 | gic->dist_base.common_base = dist_base; |
| 981 | gic->cpu_base.common_base = cpu_base; |
| 982 | gic_set_base_accessor(gic, gic_get_common_base); |
| 983 | } |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 984 | |
Rob Herring | 4294f8b | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 985 | /* |
Rob Herring | 4294f8b | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 986 | * Find out how many interrupts are supported. |
| 987 | * The GIC only supports up to 1020 interrupt sources. |
| 988 | */ |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 989 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
Rob Herring | 4294f8b | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 990 | gic_irqs = (gic_irqs + 1) * 32; |
| 991 | if (gic_irqs > 1020) |
| 992 | gic_irqs = 1020; |
| 993 | gic->gic_irqs = gic_irqs; |
| 994 | |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 995 | if (node) { /* DT case */ |
Marc Zyngier | a5561c3 | 2015-03-11 15:43:46 +0000 | [diff] [blame] | 996 | gic->domain = irq_domain_add_linear(node, gic_irqs, |
| 997 | &gic_irq_domain_hierarchy_ops, |
| 998 | gic); |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 999 | } else { /* Non-DT case */ |
| 1000 | /* |
| 1001 | * For primary GICs, skip over SGIs. |
| 1002 | * For secondary GICs, skip over PPIs, too. |
| 1003 | */ |
| 1004 | if (gic_nr == 0 && (irq_start & 31) > 0) { |
| 1005 | hwirq_base = 16; |
| 1006 | if (irq_start != -1) |
| 1007 | irq_start = (irq_start & ~31) + 16; |
| 1008 | } else { |
| 1009 | hwirq_base = 32; |
| 1010 | } |
| 1011 | |
| 1012 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ |
| 1013 | |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 1014 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, |
| 1015 | numa_node_id()); |
| 1016 | if (IS_ERR_VALUE(irq_base)) { |
| 1017 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", |
| 1018 | irq_start); |
| 1019 | irq_base = irq_start; |
| 1020 | } |
| 1021 | |
| 1022 | gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, |
| 1023 | hwirq_base, &gic_irq_domain_ops, gic); |
Rob Herring | f37a53c | 2011-10-21 17:14:27 -0500 | [diff] [blame] | 1024 | } |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 1025 | |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 1026 | if (WARN_ON(!gic->domain)) |
| 1027 | return; |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 1028 | |
Mark Rutland | 08332df | 2013-11-28 14:21:40 +0000 | [diff] [blame] | 1029 | if (gic_nr == 0) { |
Jon Hunter | 567e5a0 | 2015-07-31 09:44:11 +0100 | [diff] [blame] | 1030 | /* |
| 1031 | * Initialize the CPU interface map to all CPUs. |
| 1032 | * It will be refined as each CPU probes its ID. |
| 1033 | * This is only necessary for the primary GIC. |
| 1034 | */ |
| 1035 | for (i = 0; i < NR_GIC_CPU_IF; i++) |
| 1036 | gic_cpu_map[i] = 0xff; |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 1037 | #ifdef CONFIG_SMP |
Mark Rutland | 08332df | 2013-11-28 14:21:40 +0000 | [diff] [blame] | 1038 | set_smp_cross_call(gic_raise_softirq); |
| 1039 | register_cpu_notifier(&gic_cpu_notifier); |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 1040 | #endif |
Mark Rutland | 08332df | 2013-11-28 14:21:40 +0000 | [diff] [blame] | 1041 | set_handle_irq(gic_handle_irq); |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 1042 | if (static_key_true(&supports_deactivate)) |
| 1043 | pr_info("GIC: Using split EOI/Deactivate mode\n"); |
Mark Rutland | 08332df | 2013-11-28 14:21:40 +0000 | [diff] [blame] | 1044 | } |
Rob Herring | cfed7d6 | 2012-11-03 12:59:51 -0500 | [diff] [blame] | 1045 | |
Rob Herring | 4294f8b | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 1046 | gic_dist_init(gic); |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 1047 | gic_cpu_init(gic); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 1048 | gic_pm_init(gic); |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 1049 | } |
| 1050 | |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1051 | #ifdef CONFIG_OF |
Sachin Kamat | 46f101d | 2013-03-13 15:05:15 +0530 | [diff] [blame] | 1052 | static int gic_cnt __initdata; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1053 | |
Stephen Boyd | 6859358 | 2014-03-04 17:02:01 -0800 | [diff] [blame] | 1054 | static int __init |
| 1055 | gic_of_init(struct device_node *node, struct device_node *parent) |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1056 | { |
| 1057 | void __iomem *cpu_base; |
| 1058 | void __iomem *dist_base; |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 1059 | struct resource cpu_res; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1060 | u32 percpu_offset; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1061 | int irq; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1062 | |
| 1063 | if (WARN_ON(!node)) |
| 1064 | return -ENODEV; |
| 1065 | |
| 1066 | dist_base = of_iomap(node, 0); |
| 1067 | WARN(!dist_base, "unable to map gic dist registers\n"); |
| 1068 | |
| 1069 | cpu_base = of_iomap(node, 1); |
| 1070 | WARN(!cpu_base, "unable to map gic cpu registers\n"); |
| 1071 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 1072 | of_address_to_resource(node, 1, &cpu_res); |
| 1073 | |
| 1074 | /* |
| 1075 | * Disable split EOI/Deactivate if either HYP is not available |
| 1076 | * or the CPU interface is too small. |
| 1077 | */ |
| 1078 | if (gic_cnt == 0 && (!is_hyp_mode_available() || |
| 1079 | resource_size(&cpu_res) < SZ_8K)) |
| 1080 | static_key_slow_dec(&supports_deactivate); |
| 1081 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1082 | if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) |
| 1083 | percpu_offset = 0; |
| 1084 | |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 1085 | gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); |
Nicolas Pitre | eeb4465 | 2012-11-28 18:17:25 -0500 | [diff] [blame] | 1086 | if (!gic_cnt) |
| 1087 | gic_init_physaddr(node); |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1088 | |
| 1089 | if (parent) { |
| 1090 | irq = irq_of_parse_and_map(node, 0); |
| 1091 | gic_cascade_irq(gic_cnt, irq); |
| 1092 | } |
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 1093 | |
| 1094 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) |
| 1095 | gicv2m_of_init(node, gic_data[gic_cnt].domain); |
| 1096 | |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1097 | gic_cnt++; |
| 1098 | return 0; |
| 1099 | } |
Suravee Suthikulpanit | 144cb08 | 2014-07-15 00:03:03 +0200 | [diff] [blame] | 1100 | IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); |
Linus Walleij | fa6e2ee | 2014-10-01 09:29:22 +0200 | [diff] [blame] | 1101 | IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); |
| 1102 | IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 1103 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
| 1104 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); |
Matthias Brugger | a97e8027 | 2014-07-03 13:58:52 +0200 | [diff] [blame] | 1105 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 1106 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
| 1107 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); |
| 1108 | |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1109 | #endif |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1110 | |
| 1111 | #ifdef CONFIG_ACPI |
| 1112 | static phys_addr_t dist_phy_base, cpu_phy_base __initdata; |
| 1113 | |
| 1114 | static int __init |
| 1115 | gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, |
| 1116 | const unsigned long end) |
| 1117 | { |
| 1118 | struct acpi_madt_generic_interrupt *processor; |
| 1119 | phys_addr_t gic_cpu_base; |
| 1120 | static int cpu_base_assigned; |
| 1121 | |
| 1122 | processor = (struct acpi_madt_generic_interrupt *)header; |
| 1123 | |
Al Stone | 99e3e3a | 2015-07-06 17:16:48 -0600 | [diff] [blame] | 1124 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1125 | return -EINVAL; |
| 1126 | |
| 1127 | /* |
| 1128 | * There is no support for non-banked GICv1/2 register in ACPI spec. |
| 1129 | * All CPU interface addresses have to be the same. |
| 1130 | */ |
| 1131 | gic_cpu_base = processor->base_address; |
| 1132 | if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) |
| 1133 | return -EINVAL; |
| 1134 | |
| 1135 | cpu_phy_base = gic_cpu_base; |
| 1136 | cpu_base_assigned = 1; |
| 1137 | return 0; |
| 1138 | } |
| 1139 | |
| 1140 | static int __init |
| 1141 | gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, |
| 1142 | const unsigned long end) |
| 1143 | { |
| 1144 | struct acpi_madt_generic_distributor *dist; |
| 1145 | |
| 1146 | dist = (struct acpi_madt_generic_distributor *)header; |
| 1147 | |
| 1148 | if (BAD_MADT_ENTRY(dist, end)) |
| 1149 | return -EINVAL; |
| 1150 | |
| 1151 | dist_phy_base = dist->base_address; |
| 1152 | return 0; |
| 1153 | } |
| 1154 | |
| 1155 | int __init |
| 1156 | gic_v2_acpi_init(struct acpi_table_header *table) |
| 1157 | { |
| 1158 | void __iomem *cpu_base, *dist_base; |
| 1159 | int count; |
| 1160 | |
| 1161 | /* Collect CPU base addresses */ |
| 1162 | count = acpi_parse_entries(ACPI_SIG_MADT, |
| 1163 | sizeof(struct acpi_table_madt), |
| 1164 | gic_acpi_parse_madt_cpu, table, |
| 1165 | ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); |
| 1166 | if (count <= 0) { |
| 1167 | pr_err("No valid GICC entries exist\n"); |
| 1168 | return -EINVAL; |
| 1169 | } |
| 1170 | |
| 1171 | /* |
| 1172 | * Find distributor base address. We expect one distributor entry since |
| 1173 | * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade. |
| 1174 | */ |
| 1175 | count = acpi_parse_entries(ACPI_SIG_MADT, |
| 1176 | sizeof(struct acpi_table_madt), |
| 1177 | gic_acpi_parse_madt_distributor, table, |
| 1178 | ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); |
| 1179 | if (count <= 0) { |
| 1180 | pr_err("No valid GICD entries exist\n"); |
| 1181 | return -EINVAL; |
| 1182 | } else if (count > 1) { |
| 1183 | pr_err("More than one GICD entry detected\n"); |
| 1184 | return -EINVAL; |
| 1185 | } |
| 1186 | |
| 1187 | cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); |
| 1188 | if (!cpu_base) { |
| 1189 | pr_err("Unable to map GICC registers\n"); |
| 1190 | return -ENOMEM; |
| 1191 | } |
| 1192 | |
| 1193 | dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE); |
| 1194 | if (!dist_base) { |
| 1195 | pr_err("Unable to map GICD registers\n"); |
| 1196 | iounmap(cpu_base); |
| 1197 | return -ENOMEM; |
| 1198 | } |
| 1199 | |
| 1200 | /* |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame^] | 1201 | * Disable split EOI/Deactivate if HYP is not available. ACPI |
| 1202 | * guarantees that we'll always have a GICv2, so the CPU |
| 1203 | * interface will always be the right size. |
| 1204 | */ |
| 1205 | if (!is_hyp_mode_available()) |
| 1206 | static_key_slow_dec(&supports_deactivate); |
| 1207 | |
| 1208 | /* |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1209 | * Initialize zero GIC instance (no multi-GIC support). Also, set GIC |
| 1210 | * as default IRQ domain to allow for GSI registration and GSI to IRQ |
| 1211 | * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()). |
| 1212 | */ |
| 1213 | gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); |
| 1214 | irq_set_default_host(gic_data[0].domain); |
Lorenzo Pieralisi | d8f4f16 | 2015-03-24 17:58:51 +0000 | [diff] [blame] | 1215 | |
| 1216 | acpi_irq_model = ACPI_IRQ_MODEL_GIC; |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1217 | return 0; |
| 1218 | } |
| 1219 | #endif |