| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/ppc/platforms/mcpn765.h |
| 3 | * |
| 4 | * Definitions for Motorola MCG MCPN765 cPCI Board. |
| 5 | * |
| 6 | * Author: Mark A. Greer |
| 7 | * mgreer@mvista.com |
| 8 | * |
| 9 | * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under |
| 10 | * the terms of the GNU General Public License version 2. This program |
| 11 | * is licensed "as is" without any warranty of any kind, whether express |
| 12 | * or implied. |
| 13 | */ |
| 14 | |
| 15 | /* |
| 16 | * From Processor to PCI: |
| 17 | * PCI Mem Space: 0x80000000 - 0xc0000000 -> 0x80000000 - 0xc0000000 (1 GB) |
| 18 | * PCI I/O Space: 0xfd800000 - 0xfe000000 -> 0x00000000 - 0x00800000 (8 MB) |
| 19 | * Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area |
| 20 | * MPIC in PCI Mem Space: 0xfe800000 - 0xfe830000 (not all used by MPIC) |
| 21 | * |
| 22 | * From PCI to Processor: |
| 23 | * System Memory: 0x00000000 -> 0x00000000 |
| 24 | */ |
| 25 | |
| 26 | #ifndef __PPC_PLATFORMS_MCPN765_H |
| 27 | #define __PPC_PLATFORMS_MCPN765_H |
| 28 | #include <linux/config.h> |
| 29 | |
| 30 | /* PCI Memory space mapping info */ |
| 31 | #define MCPN765_PCI_MEM_SIZE 0x40000000U |
| 32 | #define MCPN765_PROC_PCI_MEM_START 0x80000000U |
| 33 | #define MCPN765_PROC_PCI_MEM_END (MCPN765_PROC_PCI_MEM_START + \ |
| 34 | MCPN765_PCI_MEM_SIZE - 1) |
| 35 | #define MCPN765_PCI_MEM_START 0x80000000U |
| 36 | #define MCPN765_PCI_MEM_END (MCPN765_PCI_MEM_START + \ |
| 37 | MCPN765_PCI_MEM_SIZE - 1) |
| 38 | |
| 39 | /* PCI I/O space mapping info */ |
| 40 | #define MCPN765_PCI_IO_SIZE 0x00800000U |
| 41 | #define MCPN765_PROC_PCI_IO_START 0xfd800000U |
| 42 | #define MCPN765_PROC_PCI_IO_END (MCPN765_PROC_PCI_IO_START + \ |
| 43 | MCPN765_PCI_IO_SIZE - 1) |
| 44 | #define MCPN765_PCI_IO_START 0x00000000U |
| 45 | #define MCPN765_PCI_IO_END (MCPN765_PCI_IO_START + \ |
| 46 | MCPN765_PCI_IO_SIZE - 1) |
| 47 | |
| 48 | /* System memory mapping info */ |
| 49 | #define MCPN765_PCI_DRAM_OFFSET 0x00000000U |
| 50 | #define MCPN765_PCI_PHY_MEM_OFFSET 0x00000000U |
| 51 | |
| 52 | #define MCPN765_ISA_MEM_BASE 0x00000000U |
| 53 | #define MCPN765_ISA_IO_BASE MCPN765_PROC_PCI_IO_START |
| 54 | |
| 55 | /* Define base addresses for important sets of registers */ |
| 56 | #define MCPN765_HAWK_MPIC_BASE 0xfe800000U |
| 57 | #define MCPN765_HAWK_SMC_BASE 0xfef80000U |
| 58 | #define MCPN765_HAWK_PPC_REG_BASE 0xfeff0000U |
| 59 | |
| 60 | /* Define MCPN765 board register addresses. */ |
| 61 | #define MCPN765_BOARD_STATUS_REG 0xfef88080U |
| 62 | #define MCPN765_BOARD_MODFAIL_REG 0xfef88090U |
| 63 | #define MCPN765_BOARD_MODRST_REG 0xfef880a0U |
| 64 | #define MCPN765_BOARD_TBEN_REG 0xfef880c0U |
| 65 | #define MCPN765_BOARD_GEOGRAPHICAL_REG 0xfef880e8U |
| 66 | #define MCPN765_BOARD_EXT_FEATURE_REG 0xfef880f0U |
| 67 | #define MCPN765_BOARD_LAST_RESET_REG 0xfef880f8U |
| 68 | |
| 69 | /* Defines for UART */ |
| 70 | |
| 71 | /* Define the UART base addresses */ |
| 72 | #define MCPN765_SERIAL_1 0xfef88000 |
| 73 | #define MCPN765_SERIAL_2 0xfef88200 |
| 74 | #define MCPN765_SERIAL_3 0xfef88400 |
| 75 | #define MCPN765_SERIAL_4 0xfef88600 |
| 76 | |
| 77 | #ifdef CONFIG_SERIAL_MANY_PORTS |
| 78 | #define RS_TABLE_SIZE 64 |
| 79 | #else |
| 80 | #define RS_TABLE_SIZE 4 |
| 81 | #endif |
| 82 | |
| 83 | /* Rate for the 1.8432 Mhz clock for the onboard serial chip */ |
| 84 | #define BASE_BAUD ( 1843200 / 16 ) |
| 85 | #define UART_CLK 1843200 |
| 86 | |
| 87 | #ifdef CONFIG_SERIAL_DETECT_IRQ |
| 88 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ) |
| 89 | #else |
| 90 | #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST) |
| 91 | #endif |
| 92 | |
| 93 | /* All UART IRQ's are wire-OR'd to IRQ 17 */ |
| 94 | #define STD_SERIAL_PORT_DFNS \ |
| 95 | { 0, BASE_BAUD, MCPN765_SERIAL_1, 17, STD_COM_FLAGS, /* ttyS0 */\ |
| 96 | iomem_base: (u8 *)MCPN765_SERIAL_1, \ |
| 97 | iomem_reg_shift: 4, \ |
| 98 | io_type: SERIAL_IO_MEM }, \ |
| 99 | { 0, BASE_BAUD, MCPN765_SERIAL_2, 17, STD_COM_FLAGS, /* ttyS1 */\ |
| 100 | iomem_base: (u8 *)MCPN765_SERIAL_2, \ |
| 101 | iomem_reg_shift: 4, \ |
| 102 | io_type: SERIAL_IO_MEM }, \ |
| 103 | { 0, BASE_BAUD, MCPN765_SERIAL_3, 17, STD_COM_FLAGS, /* ttyS2 */\ |
| 104 | iomem_base: (u8 *)MCPN765_SERIAL_3, \ |
| 105 | iomem_reg_shift: 4, \ |
| 106 | io_type: SERIAL_IO_MEM }, \ |
| 107 | { 0, BASE_BAUD, MCPN765_SERIAL_4, 17, STD_COM_FLAGS, /* ttyS3 */\ |
| 108 | iomem_base: (u8 *)MCPN765_SERIAL_4, \ |
| 109 | iomem_reg_shift: 4, \ |
| 110 | io_type: SERIAL_IO_MEM }, |
| 111 | |
| 112 | #define SERIAL_PORT_DFNS \ |
| 113 | STD_SERIAL_PORT_DFNS |
| 114 | |
| 115 | /* Define the NVRAM/RTC address strobe & data registers */ |
| 116 | #define MCPN765_PHYS_NVRAM_AS0 0xfef880c8U |
| 117 | #define MCPN765_PHYS_NVRAM_AS1 0xfef880d0U |
| 118 | #define MCPN765_PHYS_NVRAM_DATA 0xfef880d8U |
| 119 | |
| 120 | extern void mcpn765_find_bridges(void); |
| 121 | |
| 122 | #endif /* __PPC_PLATFORMS_MCPN765_H */ |