Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 1 | #include <dt-bindings/clock/tegra114-car.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
Thierry Reding | 32215e7 | 2014-09-24 15:41:41 +0200 | [diff] [blame] | 3 | #include <dt-bindings/memory/tegra114-mc.h> |
Laxman Dewangan | 5fc6b0d | 2013-12-05 16:14:07 +0530 | [diff] [blame] | 4 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 5 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 6 | |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 7 | #include "skeleton.dtsi" |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 8 | |
| 9 | / { |
| 10 | compatible = "nvidia,tegra114"; |
Marc Zyngier | 870c81a | 2015-03-11 15:43:01 +0000 | [diff] [blame] | 11 | interrupt-parent = <&lic>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 12 | |
Mikko Perttunen | 65344b9 | 2013-12-19 16:59:28 +0100 | [diff] [blame] | 13 | host1x@50000000 { |
| 14 | compatible = "nvidia,tegra114-host1x", "simple-bus"; |
| 15 | reg = <0x50000000 0x00028000>; |
| 16 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
| 17 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ |
| 18 | clocks = <&tegra_car TEGRA114_CLK_HOST1X>; |
| 19 | resets = <&tegra_car 28>; |
| 20 | reset-names = "host1x"; |
| 21 | |
| 22 | #address-cells = <1>; |
| 23 | #size-cells = <1>; |
| 24 | |
| 25 | ranges = <0x54000000 0x54000000 0x01000000>; |
| 26 | |
Thierry Reding | 5648b26 | 2013-12-19 16:59:30 +0100 | [diff] [blame] | 27 | gr2d@54140000 { |
| 28 | compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d"; |
| 29 | reg = <0x54140000 0x00040000>; |
| 30 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| 31 | clocks = <&tegra_car TEGRA114_CLK_GR2D>; |
| 32 | resets = <&tegra_car 21>; |
| 33 | reset-names = "2d"; |
| 34 | }; |
| 35 | |
Thierry Reding | 032f11f | 2013-12-19 16:59:31 +0100 | [diff] [blame] | 36 | gr3d@54180000 { |
| 37 | compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d"; |
| 38 | reg = <0x54180000 0x00040000>; |
| 39 | clocks = <&tegra_car TEGRA114_CLK_GR3D>; |
| 40 | resets = <&tegra_car 24>; |
| 41 | reset-names = "3d"; |
| 42 | }; |
| 43 | |
Mikko Perttunen | 65344b9 | 2013-12-19 16:59:28 +0100 | [diff] [blame] | 44 | dc@54200000 { |
| 45 | compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; |
| 46 | reg = <0x54200000 0x00040000>; |
| 47 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 48 | clocks = <&tegra_car TEGRA114_CLK_DISP1>, |
| 49 | <&tegra_car TEGRA114_CLK_PLL_P>; |
| 50 | clock-names = "dc", "parent"; |
| 51 | resets = <&tegra_car 27>; |
| 52 | reset-names = "dc"; |
| 53 | |
Thierry Reding | 32215e7 | 2014-09-24 15:41:41 +0200 | [diff] [blame] | 54 | iommus = <&mc TEGRA_SWGROUP_DC>; |
| 55 | |
Thierry Reding | 688b56b | 2014-02-18 23:03:31 +0100 | [diff] [blame] | 56 | nvidia,head = <0>; |
| 57 | |
Mikko Perttunen | 65344b9 | 2013-12-19 16:59:28 +0100 | [diff] [blame] | 58 | rgb { |
| 59 | status = "disabled"; |
| 60 | }; |
| 61 | }; |
| 62 | |
| 63 | dc@54240000 { |
| 64 | compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; |
| 65 | reg = <0x54240000 0x00040000>; |
| 66 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 67 | clocks = <&tegra_car TEGRA114_CLK_DISP2>, |
| 68 | <&tegra_car TEGRA114_CLK_PLL_P>; |
| 69 | clock-names = "dc", "parent"; |
| 70 | resets = <&tegra_car 26>; |
| 71 | reset-names = "dc"; |
| 72 | |
Thierry Reding | 32215e7 | 2014-09-24 15:41:41 +0200 | [diff] [blame] | 73 | iommus = <&mc TEGRA_SWGROUP_DCB>; |
| 74 | |
Thierry Reding | 688b56b | 2014-02-18 23:03:31 +0100 | [diff] [blame] | 75 | nvidia,head = <1>; |
| 76 | |
Mikko Perttunen | 65344b9 | 2013-12-19 16:59:28 +0100 | [diff] [blame] | 77 | rgb { |
| 78 | status = "disabled"; |
| 79 | }; |
| 80 | }; |
| 81 | |
| 82 | hdmi@54280000 { |
| 83 | compatible = "nvidia,tegra114-hdmi"; |
| 84 | reg = <0x54280000 0x00040000>; |
| 85 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 86 | clocks = <&tegra_car TEGRA114_CLK_HDMI>, |
| 87 | <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; |
| 88 | clock-names = "hdmi", "parent"; |
| 89 | resets = <&tegra_car 51>; |
| 90 | reset-names = "hdmi"; |
| 91 | status = "disabled"; |
| 92 | }; |
Thierry Reding | 7e4ba90 | 2013-12-19 16:59:29 +0100 | [diff] [blame] | 93 | |
| 94 | dsi@54300000 { |
| 95 | compatible = "nvidia,tegra114-dsi"; |
| 96 | reg = <0x54300000 0x00040000>; |
| 97 | clocks = <&tegra_car TEGRA114_CLK_DSIA>, |
| 98 | <&tegra_car TEGRA114_CLK_DSIALP>, |
| 99 | <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; |
| 100 | clock-names = "dsi", "lp", "parent"; |
| 101 | resets = <&tegra_car 48>; |
| 102 | reset-names = "dsi"; |
| 103 | nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ |
| 104 | status = "disabled"; |
| 105 | |
| 106 | #address-cells = <1>; |
| 107 | #size-cells = <0>; |
| 108 | }; |
| 109 | |
| 110 | dsi@54400000 { |
| 111 | compatible = "nvidia,tegra114-dsi"; |
| 112 | reg = <0x54400000 0x00040000>; |
| 113 | clocks = <&tegra_car TEGRA114_CLK_DSIB>, |
| 114 | <&tegra_car TEGRA114_CLK_DSIBLP>, |
| 115 | <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; |
| 116 | clock-names = "dsi", "lp", "parent"; |
| 117 | resets = <&tegra_car 82>; |
| 118 | reset-names = "dsi"; |
| 119 | nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ |
| 120 | status = "disabled"; |
| 121 | |
| 122 | #address-cells = <1>; |
| 123 | #size-cells = <0>; |
| 124 | }; |
Mikko Perttunen | 65344b9 | 2013-12-19 16:59:28 +0100 | [diff] [blame] | 125 | }; |
| 126 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 127 | gic: interrupt-controller@50041000 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 128 | compatible = "arm,cortex-a15-gic"; |
| 129 | #interrupt-cells = <3>; |
| 130 | interrupt-controller; |
| 131 | reg = <0x50041000 0x1000>, |
| 132 | <0x50042000 0x1000>, |
| 133 | <0x50044000 0x2000>, |
| 134 | <0x50046000 0x2000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 135 | interrupts = <GIC_PPI 9 |
| 136 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Marc Zyngier | 870c81a | 2015-03-11 15:43:01 +0000 | [diff] [blame] | 137 | interrupt-parent = <&gic>; |
| 138 | }; |
| 139 | |
| 140 | lic: interrupt-controller@60004000 { |
| 141 | compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; |
| 142 | reg = <0x60004000 0x100>, |
| 143 | <0x60004100 0x50>, |
| 144 | <0x60004200 0x50>, |
| 145 | <0x60004300 0x50>, |
| 146 | <0x60004400 0x50>; |
| 147 | interrupt-controller; |
| 148 | #interrupt-cells = <3>; |
| 149 | interrupt-parent = <&gic>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 150 | }; |
| 151 | |
| 152 | timer@60005000 { |
| 153 | compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; |
| 154 | reg = <0x60005000 0x400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 155 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 156 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 157 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 158 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 159 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 160 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 161 | clocks = <&tegra_car TEGRA114_CLK_TIMER>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 162 | }; |
| 163 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 164 | tegra_car: clock@60006000 { |
Peter De Schrijver | 672d889 | 2013-04-03 17:40:48 +0300 | [diff] [blame] | 165 | compatible = "nvidia,tegra114-car"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 166 | reg = <0x60006000 0x1000>; |
| 167 | #clock-cells = <1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 168 | #reset-cells = <1>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 169 | }; |
| 170 | |
Thierry Reding | b102313 | 2014-08-26 08:14:03 +0200 | [diff] [blame] | 171 | flow-controller@60007000 { |
| 172 | compatible = "nvidia,tegra114-flowctrl"; |
| 173 | reg = <0x60007000 0x1000>; |
| 174 | }; |
| 175 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 176 | apbdma: dma@6000a000 { |
Laxman Dewangan | c5d9da4 | 2013-03-14 01:19:50 +0530 | [diff] [blame] | 177 | compatible = "nvidia,tegra114-apbdma"; |
| 178 | reg = <0x6000a000 0x1400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 179 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 180 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 181 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 182 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 183 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 184 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 185 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 186 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 187 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 188 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 189 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 190 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 191 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 192 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 193 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 194 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 195 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| 196 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| 197 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| 198 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 199 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| 200 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| 201 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| 202 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 203 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| 204 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| 205 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| 206 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| 207 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| 208 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| 209 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 210 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 211 | clocks = <&tegra_car TEGRA114_CLK_APBDMA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 212 | resets = <&tegra_car 34>; |
| 213 | reset-names = "dma"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 214 | #dma-cells = <1>; |
Laxman Dewangan | c5d9da4 | 2013-03-14 01:19:50 +0530 | [diff] [blame] | 215 | }; |
| 216 | |
Nicolas Chauvet | 0d5ccb3 | 2015-08-08 15:58:12 +0200 | [diff] [blame^] | 217 | ahb: ahb@6000c000 { |
Hiroshi Doyu | 0dfe42e | 2013-01-15 10:17:27 +0200 | [diff] [blame] | 218 | compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; |
Nicolas Chauvet | 0d5ccb3 | 2015-08-08 15:58:12 +0200 | [diff] [blame^] | 219 | reg = <0x6000c000 0x150>; |
Hiroshi Doyu | 0dfe42e | 2013-01-15 10:17:27 +0200 | [diff] [blame] | 220 | }; |
| 221 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 222 | gpio: gpio@6000d000 { |
Laxman Dewangan | b16f918 | 2013-01-29 18:26:18 +0530 | [diff] [blame] | 223 | compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; |
| 224 | reg = <0x6000d000 0x1000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 225 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 226 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 227 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 228 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 229 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 230 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 231 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| 232 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | b16f918 | 2013-01-29 18:26:18 +0530 | [diff] [blame] | 233 | #gpio-cells = <2>; |
| 234 | gpio-controller; |
| 235 | #interrupt-cells = <2>; |
| 236 | interrupt-controller; |
| 237 | }; |
| 238 | |
Peter De Schrijver | 155dfc7 | 2014-06-12 18:36:38 +0300 | [diff] [blame] | 239 | apbmisc@70000800 { |
| 240 | compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; |
| 241 | reg = <0x70000800 0x64 /* Chip revision */ |
| 242 | 0x70000008 0x04>; /* Strapping options */ |
| 243 | }; |
| 244 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 245 | pinmux: pinmux@70000868 { |
Laxman Dewangan | 031b77a | 2013-01-29 18:26:20 +0530 | [diff] [blame] | 246 | compatible = "nvidia,tegra114-pinmux"; |
| 247 | reg = <0x70000868 0x148 /* Pad control registers */ |
| 248 | 0x70003000 0x40c>; /* Mux registers */ |
| 249 | }; |
| 250 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 251 | /* |
| 252 | * There are two serial driver i.e. 8250 based simple serial |
| 253 | * driver and APB DMA based serial driver for higher baudrate |
| 254 | * and performace. To enable the 8250 based driver, the compatible |
| 255 | * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable |
| 256 | * the APB DMA based serial driver, the comptible is |
| 257 | * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". |
| 258 | */ |
| 259 | uarta: serial@70006000 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 260 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 261 | reg = <0x70006000 0x40>; |
| 262 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 263 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 264 | clocks = <&tegra_car TEGRA114_CLK_UARTA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 265 | resets = <&tegra_car 6>; |
| 266 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 267 | dmas = <&apbdma 8>, <&apbdma 8>; |
| 268 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 269 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 270 | }; |
| 271 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 272 | uartb: serial@70006040 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 273 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 274 | reg = <0x70006040 0x40>; |
| 275 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 276 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 277 | clocks = <&tegra_car TEGRA114_CLK_UARTB>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 278 | resets = <&tegra_car 7>; |
| 279 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 280 | dmas = <&apbdma 9>, <&apbdma 9>; |
| 281 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 282 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 283 | }; |
| 284 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 285 | uartc: serial@70006200 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 286 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 287 | reg = <0x70006200 0x100>; |
| 288 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 289 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 290 | clocks = <&tegra_car TEGRA114_CLK_UARTC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 291 | resets = <&tegra_car 55>; |
| 292 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 293 | dmas = <&apbdma 10>, <&apbdma 10>; |
| 294 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 295 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 296 | }; |
| 297 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 298 | uartd: serial@70006300 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 299 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 300 | reg = <0x70006300 0x100>; |
| 301 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 302 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 303 | clocks = <&tegra_car TEGRA114_CLK_UARTD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 304 | resets = <&tegra_car 65>; |
| 305 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 306 | dmas = <&apbdma 19>, <&apbdma 19>; |
| 307 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 308 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 309 | }; |
| 310 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 311 | pwm: pwm@7000a000 { |
Andrew Chew | 6c716db | 2013-03-12 16:40:50 -0700 | [diff] [blame] | 312 | compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; |
| 313 | reg = <0x7000a000 0x100>; |
| 314 | #pwm-cells = <2>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 315 | clocks = <&tegra_car TEGRA114_CLK_PWM>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 316 | resets = <&tegra_car 17>; |
| 317 | reset-names = "pwm"; |
Andrew Chew | 6c716db | 2013-03-12 16:40:50 -0700 | [diff] [blame] | 318 | status = "disabled"; |
| 319 | }; |
| 320 | |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 321 | i2c@7000c000 { |
| 322 | compatible = "nvidia,tegra114-i2c"; |
| 323 | reg = <0x7000c000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 324 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 325 | #address-cells = <1>; |
| 326 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 327 | clocks = <&tegra_car TEGRA114_CLK_I2C1>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 328 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 329 | resets = <&tegra_car 12>; |
| 330 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 331 | dmas = <&apbdma 21>, <&apbdma 21>; |
| 332 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 333 | status = "disabled"; |
| 334 | }; |
| 335 | |
| 336 | i2c@7000c400 { |
| 337 | compatible = "nvidia,tegra114-i2c"; |
| 338 | reg = <0x7000c400 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 339 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 340 | #address-cells = <1>; |
| 341 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 342 | clocks = <&tegra_car TEGRA114_CLK_I2C2>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 343 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 344 | resets = <&tegra_car 54>; |
| 345 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 346 | dmas = <&apbdma 22>, <&apbdma 22>; |
| 347 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 348 | status = "disabled"; |
| 349 | }; |
| 350 | |
| 351 | i2c@7000c500 { |
| 352 | compatible = "nvidia,tegra114-i2c"; |
| 353 | reg = <0x7000c500 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 354 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 355 | #address-cells = <1>; |
| 356 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 357 | clocks = <&tegra_car TEGRA114_CLK_I2C3>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 358 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 359 | resets = <&tegra_car 67>; |
| 360 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 361 | dmas = <&apbdma 23>, <&apbdma 23>; |
| 362 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 363 | status = "disabled"; |
| 364 | }; |
| 365 | |
| 366 | i2c@7000c700 { |
| 367 | compatible = "nvidia,tegra114-i2c"; |
| 368 | reg = <0x7000c700 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 369 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 370 | #address-cells = <1>; |
| 371 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 372 | clocks = <&tegra_car TEGRA114_CLK_I2C4>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 373 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 374 | resets = <&tegra_car 103>; |
| 375 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 376 | dmas = <&apbdma 26>, <&apbdma 26>; |
| 377 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 378 | status = "disabled"; |
| 379 | }; |
| 380 | |
| 381 | i2c@7000d000 { |
| 382 | compatible = "nvidia,tegra114-i2c"; |
| 383 | reg = <0x7000d000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 384 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 385 | #address-cells = <1>; |
| 386 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 387 | clocks = <&tegra_car TEGRA114_CLK_I2C5>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 388 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 389 | resets = <&tegra_car 47>; |
| 390 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 391 | dmas = <&apbdma 24>, <&apbdma 24>; |
| 392 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 393 | status = "disabled"; |
| 394 | }; |
| 395 | |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 396 | spi@7000d400 { |
| 397 | compatible = "nvidia,tegra114-spi"; |
| 398 | reg = <0x7000d400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 399 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 400 | #address-cells = <1>; |
| 401 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 402 | clocks = <&tegra_car TEGRA114_CLK_SBC1>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 403 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 404 | resets = <&tegra_car 41>; |
| 405 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 406 | dmas = <&apbdma 15>, <&apbdma 15>; |
| 407 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 408 | status = "disabled"; |
| 409 | }; |
| 410 | |
| 411 | spi@7000d600 { |
| 412 | compatible = "nvidia,tegra114-spi"; |
| 413 | reg = <0x7000d600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 414 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 415 | #address-cells = <1>; |
| 416 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 417 | clocks = <&tegra_car TEGRA114_CLK_SBC2>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 418 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 419 | resets = <&tegra_car 44>; |
| 420 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 421 | dmas = <&apbdma 16>, <&apbdma 16>; |
| 422 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 423 | status = "disabled"; |
| 424 | }; |
| 425 | |
| 426 | spi@7000d800 { |
| 427 | compatible = "nvidia,tegra114-spi"; |
| 428 | reg = <0x7000d800 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 429 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 430 | #address-cells = <1>; |
| 431 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 432 | clocks = <&tegra_car TEGRA114_CLK_SBC3>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 433 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 434 | resets = <&tegra_car 46>; |
| 435 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 436 | dmas = <&apbdma 17>, <&apbdma 17>; |
| 437 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 438 | status = "disabled"; |
| 439 | }; |
| 440 | |
| 441 | spi@7000da00 { |
| 442 | compatible = "nvidia,tegra114-spi"; |
| 443 | reg = <0x7000da00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 444 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 445 | #address-cells = <1>; |
| 446 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 447 | clocks = <&tegra_car TEGRA114_CLK_SBC4>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 448 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 449 | resets = <&tegra_car 68>; |
| 450 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 451 | dmas = <&apbdma 18>, <&apbdma 18>; |
| 452 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 453 | status = "disabled"; |
| 454 | }; |
| 455 | |
| 456 | spi@7000dc00 { |
| 457 | compatible = "nvidia,tegra114-spi"; |
| 458 | reg = <0x7000dc00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 459 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 460 | #address-cells = <1>; |
| 461 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 462 | clocks = <&tegra_car TEGRA114_CLK_SBC5>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 463 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 464 | resets = <&tegra_car 104>; |
| 465 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 466 | dmas = <&apbdma 27>, <&apbdma 27>; |
| 467 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 468 | status = "disabled"; |
| 469 | }; |
| 470 | |
| 471 | spi@7000de00 { |
| 472 | compatible = "nvidia,tegra114-spi"; |
| 473 | reg = <0x7000de00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 474 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 475 | #address-cells = <1>; |
| 476 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 477 | clocks = <&tegra_car TEGRA114_CLK_SBC6>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 478 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 479 | resets = <&tegra_car 105>; |
| 480 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 481 | dmas = <&apbdma 28>, <&apbdma 28>; |
| 482 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 483 | status = "disabled"; |
| 484 | }; |
| 485 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 486 | rtc@7000e000 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 487 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; |
| 488 | reg = <0x7000e000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 489 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 490 | clocks = <&tegra_car TEGRA114_CLK_RTC>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 491 | }; |
| 492 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 493 | kbc@7000e200 { |
Laxman Dewangan | cd467b7 | 2013-03-14 01:19:53 +0530 | [diff] [blame] | 494 | compatible = "nvidia,tegra114-kbc"; |
| 495 | reg = <0x7000e200 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 496 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 497 | clocks = <&tegra_car TEGRA114_CLK_KBC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 498 | resets = <&tegra_car 36>; |
| 499 | reset-names = "kbc"; |
Laxman Dewangan | cd467b7 | 2013-03-14 01:19:53 +0530 | [diff] [blame] | 500 | status = "disabled"; |
| 501 | }; |
| 502 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 503 | pmc@7000e400 { |
Joseph Lo | 2b84e53 | 2013-02-26 16:27:43 +0000 | [diff] [blame] | 504 | compatible = "nvidia,tegra114-pmc"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 505 | reg = <0x7000e400 0x400>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 506 | clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 507 | clock-names = "pclk", "clk32k_in"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 508 | }; |
| 509 | |
Peter De Schrijver | 155dfc7 | 2014-06-12 18:36:38 +0300 | [diff] [blame] | 510 | fuse@7000f800 { |
| 511 | compatible = "nvidia,tegra114-efuse"; |
| 512 | reg = <0x7000f800 0x400>; |
| 513 | clocks = <&tegra_car TEGRA114_CLK_FUSE>; |
| 514 | clock-names = "fuse"; |
| 515 | resets = <&tegra_car 39>; |
| 516 | reset-names = "fuse"; |
| 517 | }; |
| 518 | |
Thierry Reding | c6f70a4 | 2014-07-18 12:11:03 +0200 | [diff] [blame] | 519 | mc: memory-controller@70019000 { |
| 520 | compatible = "nvidia,tegra114-mc"; |
| 521 | reg = <0x70019000 0x1000>; |
| 522 | clocks = <&tegra_car TEGRA114_CLK_MC>; |
| 523 | clock-names = "mc"; |
| 524 | |
| 525 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 526 | |
| 527 | #iommu-cells = <1>; |
Hiroshi Doyu | 2da1396 | 2013-01-15 10:17:28 +0200 | [diff] [blame] | 528 | }; |
| 529 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 530 | ahub@70080000 { |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 531 | compatible = "nvidia,tegra114-ahub"; |
| 532 | reg = <0x70080000 0x200>, |
| 533 | <0x70080200 0x100>, |
| 534 | <0x70081000 0x200>; |
| 535 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 536 | clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, |
Stephen Warren | 2bd541f | 2013-11-07 10:59:42 -0700 | [diff] [blame] | 537 | <&tegra_car TEGRA114_CLK_APBIF>; |
| 538 | clock-names = "d_audio", "apbif"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 539 | resets = <&tegra_car 106>, /* d_audio */ |
| 540 | <&tegra_car 107>, /* apbif */ |
| 541 | <&tegra_car 30>, /* i2s0 */ |
| 542 | <&tegra_car 11>, /* i2s1 */ |
| 543 | <&tegra_car 18>, /* i2s2 */ |
| 544 | <&tegra_car 101>, /* i2s3 */ |
| 545 | <&tegra_car 102>, /* i2s4 */ |
| 546 | <&tegra_car 108>, /* dam0 */ |
| 547 | <&tegra_car 109>, /* dam1 */ |
| 548 | <&tegra_car 110>, /* dam2 */ |
| 549 | <&tegra_car 10>, /* spdif */ |
| 550 | <&tegra_car 153>, /* amx */ |
| 551 | <&tegra_car 154>; /* adx */ |
| 552 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
| 553 | "i2s3", "i2s4", "dam0", "dam1", "dam2", |
| 554 | "spdif", "amx", "adx"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 555 | dmas = <&apbdma 1>, <&apbdma 1>, |
| 556 | <&apbdma 2>, <&apbdma 2>, |
| 557 | <&apbdma 3>, <&apbdma 3>, |
| 558 | <&apbdma 4>, <&apbdma 4>, |
| 559 | <&apbdma 6>, <&apbdma 6>, |
| 560 | <&apbdma 7>, <&apbdma 7>, |
| 561 | <&apbdma 12>, <&apbdma 12>, |
| 562 | <&apbdma 13>, <&apbdma 13>, |
| 563 | <&apbdma 14>, <&apbdma 14>, |
| 564 | <&apbdma 29>, <&apbdma 29>; |
| 565 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", |
| 566 | "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", |
| 567 | "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", |
| 568 | "rx9", "tx9"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 569 | ranges; |
| 570 | #address-cells = <1>; |
| 571 | #size-cells = <1>; |
| 572 | |
| 573 | tegra_i2s0: i2s@70080300 { |
| 574 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 575 | reg = <0x70080300 0x100>; |
| 576 | nvidia,ahub-cif-ids = <4 4>; |
| 577 | clocks = <&tegra_car TEGRA114_CLK_I2S0>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 578 | resets = <&tegra_car 30>; |
| 579 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 580 | status = "disabled"; |
| 581 | }; |
| 582 | |
| 583 | tegra_i2s1: i2s@70080400 { |
| 584 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 585 | reg = <0x70080400 0x100>; |
| 586 | nvidia,ahub-cif-ids = <5 5>; |
| 587 | clocks = <&tegra_car TEGRA114_CLK_I2S1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 588 | resets = <&tegra_car 11>; |
| 589 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 590 | status = "disabled"; |
| 591 | }; |
| 592 | |
| 593 | tegra_i2s2: i2s@70080500 { |
| 594 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 595 | reg = <0x70080500 0x100>; |
| 596 | nvidia,ahub-cif-ids = <6 6>; |
| 597 | clocks = <&tegra_car TEGRA114_CLK_I2S2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 598 | resets = <&tegra_car 18>; |
| 599 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 600 | status = "disabled"; |
| 601 | }; |
| 602 | |
| 603 | tegra_i2s3: i2s@70080600 { |
| 604 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 605 | reg = <0x70080600 0x100>; |
| 606 | nvidia,ahub-cif-ids = <7 7>; |
| 607 | clocks = <&tegra_car TEGRA114_CLK_I2S3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 608 | resets = <&tegra_car 101>; |
| 609 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 610 | status = "disabled"; |
| 611 | }; |
| 612 | |
| 613 | tegra_i2s4: i2s@70080700 { |
| 614 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 615 | reg = <0x70080700 0x100>; |
| 616 | nvidia,ahub-cif-ids = <8 8>; |
| 617 | clocks = <&tegra_car TEGRA114_CLK_I2S4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 618 | resets = <&tegra_car 102>; |
| 619 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 620 | status = "disabled"; |
| 621 | }; |
| 622 | }; |
| 623 | |
Thierry Reding | e3d04d1 | 2013-12-19 16:59:27 +0100 | [diff] [blame] | 624 | mipi: mipi@700e3000 { |
| 625 | compatible = "nvidia,tegra114-mipi"; |
| 626 | reg = <0x700e3000 0x100>; |
| 627 | clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; |
| 628 | #nvidia,mipi-calibrate-cells = <1>; |
| 629 | }; |
| 630 | |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 631 | sdhci@78000000 { |
| 632 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 633 | reg = <0x78000000 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 634 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 635 | clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 636 | resets = <&tegra_car 14>; |
| 637 | reset-names = "sdhci"; |
Thierry Reding | e2b6d77 | 2014-02-25 16:31:40 +0100 | [diff] [blame] | 638 | status = "disabled"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 639 | }; |
| 640 | |
| 641 | sdhci@78000200 { |
| 642 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 643 | reg = <0x78000200 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 644 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 645 | clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 646 | resets = <&tegra_car 9>; |
| 647 | reset-names = "sdhci"; |
Thierry Reding | e2b6d77 | 2014-02-25 16:31:40 +0100 | [diff] [blame] | 648 | status = "disabled"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 649 | }; |
| 650 | |
| 651 | sdhci@78000400 { |
| 652 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 653 | reg = <0x78000400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 654 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 655 | clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 656 | resets = <&tegra_car 69>; |
| 657 | reset-names = "sdhci"; |
Thierry Reding | e2b6d77 | 2014-02-25 16:31:40 +0100 | [diff] [blame] | 658 | status = "disabled"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 659 | }; |
| 660 | |
| 661 | sdhci@78000600 { |
| 662 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 663 | reg = <0x78000600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 664 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 665 | clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 666 | resets = <&tegra_car 15>; |
| 667 | reset-names = "sdhci"; |
Thierry Reding | e2b6d77 | 2014-02-25 16:31:40 +0100 | [diff] [blame] | 668 | status = "disabled"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 669 | }; |
| 670 | |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 671 | usb@7d000000 { |
| 672 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 673 | reg = <0x7d000000 0x4000>; |
| 674 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 675 | phy_type = "utmi"; |
| 676 | clocks = <&tegra_car TEGRA114_CLK_USBD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 677 | resets = <&tegra_car 22>; |
| 678 | reset-names = "usb"; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 679 | nvidia,phy = <&phy1>; |
| 680 | status = "disabled"; |
| 681 | }; |
| 682 | |
| 683 | phy1: usb-phy@7d000000 { |
| 684 | compatible = "nvidia,tegra30-usb-phy"; |
| 685 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; |
| 686 | phy_type = "utmi"; |
| 687 | clocks = <&tegra_car TEGRA114_CLK_USBD>, |
| 688 | <&tegra_car TEGRA114_CLK_PLL_U>, |
| 689 | <&tegra_car TEGRA114_CLK_USBD>; |
| 690 | clock-names = "reg", "pll_u", "utmi-pads"; |
Tuomas Tynkkynen | 308efde | 2014-07-04 04:09:37 +0300 | [diff] [blame] | 691 | resets = <&tegra_car 22>, <&tegra_car 22>; |
| 692 | reset-names = "usb", "utmi-pads"; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 693 | nvidia,hssync-start-delay = <0>; |
| 694 | nvidia,idle-wait-delay = <17>; |
| 695 | nvidia,elastic-limit = <16>; |
| 696 | nvidia,term-range-adj = <6>; |
| 697 | nvidia,xcvr-setup = <9>; |
| 698 | nvidia,xcvr-lsfslew = <0>; |
| 699 | nvidia,xcvr-lsrslew = <3>; |
| 700 | nvidia,hssquelch-level = <2>; |
| 701 | nvidia,hsdiscon-level = <5>; |
| 702 | nvidia,xcvr-hsslew = <12>; |
Tuomas Tynkkynen | 308efde | 2014-07-04 04:09:37 +0300 | [diff] [blame] | 703 | nvidia,has-utmi-pad-registers; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 704 | status = "disabled"; |
| 705 | }; |
| 706 | |
| 707 | usb@7d008000 { |
| 708 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 709 | reg = <0x7d008000 0x4000>; |
| 710 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 711 | phy_type = "utmi"; |
| 712 | clocks = <&tegra_car TEGRA114_CLK_USB3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 713 | resets = <&tegra_car 59>; |
| 714 | reset-names = "usb"; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 715 | nvidia,phy = <&phy3>; |
| 716 | status = "disabled"; |
| 717 | }; |
| 718 | |
| 719 | phy3: usb-phy@7d008000 { |
| 720 | compatible = "nvidia,tegra30-usb-phy"; |
| 721 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; |
| 722 | phy_type = "utmi"; |
| 723 | clocks = <&tegra_car TEGRA114_CLK_USB3>, |
| 724 | <&tegra_car TEGRA114_CLK_PLL_U>, |
| 725 | <&tegra_car TEGRA114_CLK_USBD>; |
| 726 | clock-names = "reg", "pll_u", "utmi-pads"; |
Tuomas Tynkkynen | 308efde | 2014-07-04 04:09:37 +0300 | [diff] [blame] | 727 | resets = <&tegra_car 59>, <&tegra_car 22>; |
| 728 | reset-names = "usb", "utmi-pads"; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 729 | nvidia,hssync-start-delay = <0>; |
| 730 | nvidia,idle-wait-delay = <17>; |
| 731 | nvidia,elastic-limit = <16>; |
| 732 | nvidia,term-range-adj = <6>; |
| 733 | nvidia,xcvr-setup = <9>; |
| 734 | nvidia,xcvr-lsfslew = <0>; |
| 735 | nvidia,xcvr-lsrslew = <3>; |
| 736 | nvidia,hssquelch-level = <2>; |
| 737 | nvidia,hsdiscon-level = <5>; |
| 738 | nvidia,xcvr-hsslew = <12>; |
| 739 | status = "disabled"; |
| 740 | }; |
| 741 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 742 | cpus { |
| 743 | #address-cells = <1>; |
| 744 | #size-cells = <0>; |
| 745 | |
| 746 | cpu@0 { |
| 747 | device_type = "cpu"; |
| 748 | compatible = "arm,cortex-a15"; |
| 749 | reg = <0>; |
| 750 | }; |
| 751 | |
| 752 | cpu@1 { |
| 753 | device_type = "cpu"; |
| 754 | compatible = "arm,cortex-a15"; |
| 755 | reg = <1>; |
| 756 | }; |
| 757 | |
| 758 | cpu@2 { |
| 759 | device_type = "cpu"; |
| 760 | compatible = "arm,cortex-a15"; |
| 761 | reg = <2>; |
| 762 | }; |
| 763 | |
| 764 | cpu@3 { |
| 765 | device_type = "cpu"; |
| 766 | compatible = "arm,cortex-a15"; |
| 767 | reg = <3>; |
| 768 | }; |
| 769 | }; |
| 770 | |
| 771 | timer { |
| 772 | compatible = "arm,armv7-timer"; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 773 | interrupts = |
| 774 | <GIC_PPI 13 |
| 775 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 776 | <GIC_PPI 14 |
| 777 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 778 | <GIC_PPI 11 |
| 779 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 780 | <GIC_PPI 10 |
| 781 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
Marc Zyngier | 870c81a | 2015-03-11 15:43:01 +0000 | [diff] [blame] | 782 | interrupt-parent = <&gic>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 783 | }; |
| 784 | }; |