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Zou Nan hai8187a2b2010-05-21 09:08:55 +08001#ifndef _INTEL_RINGBUFFER_H_
2#define _INTEL_RINGBUFFER_H_
3
Chris Wilson1ec14ad2010-12-04 11:30:53 +00004enum {
5 RCS = 0x0,
6 VCS,
7 BCS,
8 I915_NUM_RINGS,
9};
10
Zou Nan hai8187a2b2010-05-21 09:08:55 +080011struct intel_hw_status_page {
Chris Wilson78501ea2010-10-27 12:18:21 +010012 u32 __iomem *page_addr;
Zou Nan hai8187a2b2010-05-21 09:08:55 +080013 unsigned int gfx_addr;
Chris Wilson05394f32010-11-08 19:18:58 +000014 struct drm_i915_gem_object *obj;
Zou Nan hai8187a2b2010-05-21 09:08:55 +080015};
16
Zou Nan haicae58522010-11-09 17:17:32 +080017#define I915_RING_READ(reg) i915_safe_read(dev_priv, reg)
18
Chris Wilson9862e602011-01-04 22:22:17 +000019#define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
20#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
Zou Nan haicae58522010-11-09 17:17:32 +080021
Chris Wilson9862e602011-01-04 22:22:17 +000022#define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
23#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
Zou Nan haicae58522010-11-09 17:17:32 +080024
Chris Wilson9862e602011-01-04 22:22:17 +000025#define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base))
26#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
Zou Nan haicae58522010-11-09 17:17:32 +080027
Chris Wilson9862e602011-01-04 22:22:17 +000028#define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
29#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
Daniel Vetter870e86d2010-08-02 16:29:44 +020030
Chris Wilson9862e602011-01-04 22:22:17 +000031#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
32#define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
Chris Wilson0f468322011-01-04 17:35:21 +000033
Chris Wilson9862e602011-01-04 22:22:17 +000034#define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
35#define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
36#define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1((ring)->mmio_base))
Chris Wilson1ec14ad2010-12-04 11:30:53 +000037
Zou Nan hai8187a2b2010-05-21 09:08:55 +080038struct intel_ring_buffer {
39 const char *name;
Chris Wilson92204342010-09-18 11:02:01 +010040 enum intel_ring_id {
41 RING_RENDER = 0x1,
42 RING_BSD = 0x2,
Chris Wilson549f7362010-10-19 11:19:32 +010043 RING_BLT = 0x4,
Chris Wilson92204342010-09-18 11:02:01 +010044 } id;
Daniel Vetter333e9fe2010-08-02 16:24:01 +020045 u32 mmio_base;
Zou Nan hai8187a2b2010-05-21 09:08:55 +080046 void *virtual_start;
47 struct drm_device *dev;
Chris Wilson05394f32010-11-08 19:18:58 +000048 struct drm_i915_gem_object *obj;
Zou Nan hai8187a2b2010-05-21 09:08:55 +080049
Chris Wilson8c0a6bf2010-12-09 12:56:37 +000050 u32 actual_head;
51 u32 head;
52 u32 tail;
Chris Wilson780f0ca2010-09-23 17:45:39 +010053 int space;
Chris Wilsonc2c347a92010-10-27 15:11:53 +010054 int size;
Chris Wilson55249ba2010-12-22 14:04:47 +000055 int effective_size;
Zou Nan hai8187a2b2010-05-21 09:08:55 +080056 struct intel_hw_status_page status_page;
57
Chris Wilson01a03332011-01-04 22:22:56 +000058 u32 irq_refcount;
Chris Wilson0f468322011-01-04 17:35:21 +000059 u32 irq_mask;
Chris Wilsonb2223492010-10-27 15:27:33 +010060 u32 irq_seqno; /* last seq seem at irq time */
61 u32 waiting_seqno;
Chris Wilson1ec14ad2010-12-04 11:30:53 +000062 u32 sync_seqno[I915_NUM_RINGS-1];
Chris Wilsonb13c2b92010-12-13 16:54:50 +000063 bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
Chris Wilson1ec14ad2010-12-04 11:30:53 +000064 void (*irq_put)(struct intel_ring_buffer *ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +080065
Chris Wilson78501ea2010-10-27 12:18:21 +010066 int (*init)(struct intel_ring_buffer *ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +080067
Chris Wilson78501ea2010-10-27 12:18:21 +010068 void (*write_tail)(struct intel_ring_buffer *ring,
Chris Wilson297b0c52010-10-22 17:02:41 +010069 u32 value);
Chris Wilsonb72f3ac2011-01-04 17:34:02 +000070 int __must_check (*flush)(struct intel_ring_buffer *ring,
71 u32 invalidate_domains,
72 u32 flush_domains);
Chris Wilson3cce4692010-10-27 16:11:02 +010073 int (*add_request)(struct intel_ring_buffer *ring,
74 u32 *seqno);
Chris Wilson78501ea2010-10-27 12:18:21 +010075 u32 (*get_seqno)(struct intel_ring_buffer *ring);
76 int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
Chris Wilsonc4e7a412010-11-30 14:10:25 +000077 u32 offset, u32 length);
Zou Nan hai8d192152010-11-02 16:31:01 +080078 void (*cleanup)(struct intel_ring_buffer *ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +080079
80 /**
81 * List of objects currently involved in rendering from the
82 * ringbuffer.
83 *
84 * Includes buffers having the contents of their GPU caches
85 * flushed, not necessarily primitives. last_rendering_seqno
86 * represents when the rendering involved will be completed.
87 *
88 * A reference is held on the buffer while on this list.
89 */
90 struct list_head active_list;
91
92 /**
93 * List of breadcrumbs associated with GPU requests currently
94 * outstanding.
95 */
96 struct list_head request_list;
97
Chris Wilsona56ba562010-09-28 10:07:56 +010098 /**
Chris Wilson64193402010-10-24 12:38:05 +010099 * List of objects currently pending a GPU write flush.
100 *
101 * All elements on this list will belong to either the
102 * active_list or flushing_list, last_rendering_seqno can
103 * be used to differentiate between the two elements.
104 */
105 struct list_head gpu_write_list;
106
107 /**
Chris Wilsona56ba562010-09-28 10:07:56 +0100108 * Do we have some not yet emitted requests outstanding?
109 */
Chris Wilson5d97eb62010-11-10 20:40:02 +0000110 u32 outstanding_lazy_request;
Chris Wilsona56ba562010-09-28 10:07:56 +0100111
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800112 wait_queue_head_t irq_queue;
113 drm_local_map_t map;
Zou Nan hai8d192152010-11-02 16:31:01 +0800114
115 void *private;
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800116};
117
118static inline u32
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000119intel_ring_sync_index(struct intel_ring_buffer *ring,
120 struct intel_ring_buffer *other)
121{
122 int idx;
123
124 /*
125 * cs -> 0 = vcs, 1 = bcs
126 * vcs -> 0 = bcs, 1 = cs,
127 * bcs -> 0 = cs, 1 = vcs.
128 */
129
130 idx = (other - ring) - 1;
131 if (idx < 0)
132 idx += I915_NUM_RINGS;
133
134 return idx;
135}
136
137static inline u32
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800138intel_read_status_page(struct intel_ring_buffer *ring,
Chris Wilson78501ea2010-10-27 12:18:21 +0100139 int reg)
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800140{
Chris Wilson78501ea2010-10-27 12:18:21 +0100141 return ioread32(ring->status_page.page_addr + reg);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800142}
143
Chris Wilson78501ea2010-10-27 12:18:21 +0100144void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
Chris Wilsone1f99ce2010-10-27 12:45:26 +0100145int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
146int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
Chris Wilsone898cd22010-08-04 15:18:14 +0100147
Chris Wilson78501ea2010-10-27 12:18:21 +0100148static inline void intel_ring_emit(struct intel_ring_buffer *ring,
149 u32 data)
Chris Wilsone898cd22010-08-04 15:18:14 +0100150{
Chris Wilson78501ea2010-10-27 12:18:21 +0100151 iowrite32(data, ring->virtual_start + ring->tail);
Chris Wilsone898cd22010-08-04 15:18:14 +0100152 ring->tail += 4;
153}
154
Chris Wilson78501ea2010-10-27 12:18:21 +0100155void intel_ring_advance(struct intel_ring_buffer *ring);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800156
Chris Wilson78501ea2010-10-27 12:18:21 +0100157u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000158int intel_ring_sync(struct intel_ring_buffer *ring,
159 struct intel_ring_buffer *to,
160 u32 seqno);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800161
Xiang, Haihao5c1143b2010-09-16 10:43:11 +0800162int intel_init_render_ring_buffer(struct drm_device *dev);
163int intel_init_bsd_ring_buffer(struct drm_device *dev);
Chris Wilson549f7362010-10-19 11:19:32 +0100164int intel_init_blt_ring_buffer(struct drm_device *dev);
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800165
Chris Wilson78501ea2010-10-27 12:18:21 +0100166u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
167void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
Daniel Vetter79f321b2010-09-24 21:20:10 +0200168
Zou Nan hai8187a2b2010-05-21 09:08:55 +0800169#endif /* _INTEL_RINGBUFFER_H_ */