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Santosh Shilimkard5e9fe82013-06-10 11:33:31 -04001/*
2 * Copyright 2013 Texas Instruments, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
Santosh Shilimkareb788f42013-08-05 13:13:07 -04009#include <dt-bindings/interrupt-controller/arm-gic.h>
10
Santosh Shilimkar226d1c52013-08-05 13:17:15 -040011#include "skeleton.dtsi"
Santosh Shilimkard5e9fe82013-06-10 11:33:31 -040012
13/ {
14 model = "Texas Instruments Keystone 2 SoC";
Santosh Shilimkard5e9fe82013-06-10 11:33:31 -040015 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
18
19 aliases {
20 serial0 = &uart0;
21 };
22
23 memory {
24 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 interrupt-parent = <&gic>;
32
33 cpu@0 {
34 compatible = "arm,cortex-a15";
35 device_type = "cpu";
36 reg = <0>;
37 };
38
39 cpu@1 {
40 compatible = "arm,cortex-a15";
41 device_type = "cpu";
42 reg = <1>;
43 };
44
45 cpu@2 {
46 compatible = "arm,cortex-a15";
47 device_type = "cpu";
48 reg = <2>;
49 };
50
51 cpu@3 {
52 compatible = "arm,cortex-a15";
53 device_type = "cpu";
54 reg = <3>;
55 };
56 };
57
58 gic: interrupt-controller {
59 compatible = "arm,cortex-a15-gic";
60 #interrupt-cells = <3>;
61 #size-cells = <0>;
62 #address-cells = <1>;
63 interrupt-controller;
64 reg = <0x0 0x02561000 0x0 0x1000>,
Santosh Shilimkara18b4aa2013-11-09 14:33:13 -050065 <0x0 0x02562000 0x0 0x2000>,
66 <0x0 0x02564000 0x0 0x1000>,
67 <0x0 0x02566000 0x0 0x2000>;
Santosh Shilimkar0ee15442013-11-09 14:36:00 -050068 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
69 IRQ_TYPE_LEVEL_HIGH)>;
Santosh Shilimkard5e9fe82013-06-10 11:33:31 -040070 };
71
72 timer {
73 compatible = "arm,armv7-timer";
Santosh Shilimkareb788f42013-08-05 13:13:07 -040074 interrupts =
75 <GIC_PPI 13
76 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 14
78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 11
80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10
82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
Santosh Shilimkard5e9fe82013-06-10 11:33:31 -040083 };
84
85 pmu {
86 compatible = "arm,cortex-a15-pmu";
Santosh Shilimkareb788f42013-08-05 13:13:07 -040087 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
88 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
89 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
90 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
Santosh Shilimkard5e9fe82013-06-10 11:33:31 -040091 };
92
93 soc {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "ti,keystone","simple-bus";
97 interrupt-parent = <&gic>;
98 ranges = <0x0 0x0 0x0 0xc0000000>;
99
100 rstctrl: reset-controller {
101 compatible = "ti,keystone-reset";
102 reg = <0x023100e8 4>; /* pll reset control reg */
103 };
104
Santosh Shilimkarfeeea8f2013-07-09 12:51:51 -0400105 /include/ "keystone-clocks.dtsi"
106
Santosh Shilimkard5e9fe82013-06-10 11:33:31 -0400107 uart0: serial@02530c00 {
108 compatible = "ns16550a";
109 current-speed = <115200>;
110 reg-shift = <2>;
111 reg-io-width = <4>;
112 reg = <0x02530c00 0x100>;
Santosh Shilimkarf023bd12013-07-19 19:11:39 -0400113 clocks = <&clkuart0>;
Santosh Shilimkareb788f42013-08-05 13:13:07 -0400114 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
Santosh Shilimkard5e9fe82013-06-10 11:33:31 -0400115 };
116
117 uart1: serial@02531000 {
118 compatible = "ns16550a";
119 current-speed = <115200>;
120 reg-shift = <2>;
121 reg-io-width = <4>;
122 reg = <0x02531000 0x100>;
Santosh Shilimkarf023bd12013-07-19 19:11:39 -0400123 clocks = <&clkuart1>;
Santosh Shilimkareb788f42013-08-05 13:13:07 -0400124 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
Santosh Shilimkard5e9fe82013-06-10 11:33:31 -0400125 };
126
Santosh Shilimkar6120ac22013-07-23 20:07:07 -0400127 i2c0: i2c@2530000 {
128 compatible = "ti,davinci-i2c";
129 reg = <0x02530000 0x400>;
130 clock-frequency = <100000>;
131 clocks = <&clki2c>;
132 interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
133 #address-cells = <1>;
134 #size-cells = <0>;
135
136 dtt@50 {
137 compatible = "at,24c1024";
138 reg = <0x50>;
139 };
140 };
141
142 i2c1: i2c@2530400 {
143 compatible = "ti,davinci-i2c";
144 reg = <0x02530400 0x400>;
145 clock-frequency = <100000>;
146 clocks = <&clki2c>;
147 interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
148 };
149
150 i2c2: i2c@2530800 {
151 compatible = "ti,davinci-i2c";
152 reg = <0x02530800 0x400>;
153 clock-frequency = <100000>;
154 clocks = <&clki2c>;
155 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
156 };
Santosh Shilimkarb3bd6c52013-07-23 20:25:23 -0400157
158 spi0: spi@21000400 {
159 compatible = "ti,dm6441-spi";
160 reg = <0x21000400 0x200>;
161 num-cs = <4>;
162 ti,davinci-spi-intr-line = <0>;
163 interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
164 clocks = <&clkspi>;
165 };
166
167 spi1: spi@21000600 {
168 compatible = "ti,dm6441-spi";
169 reg = <0x21000600 0x200>;
170 num-cs = <4>;
171 ti,davinci-spi-intr-line = <0>;
172 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
173 clocks = <&clkspi>;
174 };
175
176 spi2: spi@21000800 {
177 compatible = "ti,dm6441-spi";
178 reg = <0x21000800 0x200>;
179 num-cs = <4>;
180 ti,davinci-spi-intr-line = <0>;
181 interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
182 clocks = <&clkspi>;
183 };
Santosh Shilimkard5e9fe82013-06-10 11:33:31 -0400184 };
185};