Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> |
| 3 | * |
| 4 | * This file is dual-licensed: you can use it either under the terms |
| 5 | * of the GPL or the X11 license, at your option. Note that this dual |
| 6 | * licensing only applies to this file, and not this project as a |
| 7 | * whole. |
| 8 | * |
| 9 | * a) This file is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of the |
| 12 | * License, or (at your option) any later version. |
| 13 | * |
| 14 | * This file is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * Or, alternatively, |
| 20 | * |
| 21 | * b) Permission is hereby granted, free of charge, to any person |
| 22 | * obtaining a copy of this software and associated documentation |
| 23 | * files (the "Software"), to deal in the Software without |
| 24 | * restriction, including without limitation the rights to use, |
| 25 | * copy, modify, merge, publish, distribute, sublicense, and/or |
| 26 | * sell copies of the Software, and to permit persons to whom the |
| 27 | * Software is furnished to do so, subject to the following |
| 28 | * conditions: |
| 29 | * |
| 30 | * The above copyright notice and this permission notice shall be |
| 31 | * included in all copies or substantial portions of the Software. |
| 32 | * |
| 33 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 34 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
| 35 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 36 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
| 37 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| 38 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 39 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 40 | * OTHER DEALINGS IN THE SOFTWARE. |
| 41 | */ |
| 42 | |
| 43 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 44 | #include <dt-bindings/clock/sun8i-v3s-ccu.h> |
| 45 | #include <dt-bindings/reset/sun8i-v3s-ccu.h> |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 46 | |
| 47 | / { |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <1>; |
| 50 | interrupt-parent = <&gic>; |
| 51 | |
| 52 | cpus { |
| 53 | #address-cells = <1>; |
| 54 | #size-cells = <0>; |
| 55 | |
| 56 | cpu@0 { |
| 57 | compatible = "arm,cortex-a7"; |
| 58 | device_type = "cpu"; |
| 59 | reg = <0>; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 60 | clocks = <&ccu CLK_CPU>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 61 | }; |
| 62 | }; |
| 63 | |
Icenowy Zheng | 21b2992 | 2017-05-24 19:17:23 +0800 | [diff] [blame] | 64 | de: display-engine { |
| 65 | compatible = "allwinner,sun8i-v3s-display-engine"; |
| 66 | allwinner,pipelines = <&mixer0>; |
| 67 | status = "disabled"; |
| 68 | }; |
| 69 | |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 70 | timer { |
| 71 | compatible = "arm,armv7-timer"; |
| 72 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 73 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 74 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 75 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| 76 | }; |
| 77 | |
| 78 | clocks { |
| 79 | #address-cells = <1>; |
| 80 | #size-cells = <1>; |
| 81 | ranges; |
| 82 | |
| 83 | osc24M: osc24M_clk { |
| 84 | #clock-cells = <0>; |
| 85 | compatible = "fixed-clock"; |
| 86 | clock-frequency = <24000000>; |
| 87 | clock-output-names = "osc24M"; |
| 88 | }; |
| 89 | |
| 90 | osc32k: osc32k_clk { |
| 91 | #clock-cells = <0>; |
| 92 | compatible = "fixed-clock"; |
| 93 | clock-frequency = <32768>; |
| 94 | clock-output-names = "osc32k"; |
| 95 | }; |
| 96 | }; |
| 97 | |
| 98 | soc { |
| 99 | compatible = "simple-bus"; |
| 100 | #address-cells = <1>; |
| 101 | #size-cells = <1>; |
| 102 | ranges; |
| 103 | |
Icenowy Zheng | 21b2992 | 2017-05-24 19:17:23 +0800 | [diff] [blame] | 104 | display_clocks: clock@1000000 { |
| 105 | compatible = "allwinner,sun8i-v3s-de2-clk"; |
| 106 | reg = <0x01000000 0x100000>; |
| 107 | clocks = <&ccu CLK_DE>, |
| 108 | <&ccu CLK_BUS_DE>; |
| 109 | clock-names = "mod", |
| 110 | "bus"; |
| 111 | resets = <&ccu RST_BUS_DE>; |
| 112 | #clock-cells = <1>; |
| 113 | #reset-cells = <1>; |
| 114 | }; |
| 115 | |
| 116 | mixer0: mixer@1100000 { |
| 117 | compatible = "allwinner,sun8i-v3s-de2-mixer"; |
| 118 | reg = <0x01100000 0x100000>; |
| 119 | clocks = <&display_clocks 0>, |
| 120 | <&display_clocks 6>; |
| 121 | clock-names = "bus", |
| 122 | "mod"; |
| 123 | resets = <&display_clocks 0>; |
| 124 | assigned-clocks = <&display_clocks 6>; |
| 125 | assigned-clock-rates = <150000000>; |
| 126 | |
| 127 | ports { |
| 128 | #address-cells = <1>; |
| 129 | #size-cells = <0>; |
| 130 | |
| 131 | mixer0_out: port@1 { |
| 132 | #address-cells = <1>; |
| 133 | #size-cells = <0>; |
| 134 | reg = <1>; |
| 135 | |
| 136 | mixer0_out_tcon0: endpoint@0 { |
| 137 | reg = <0>; |
| 138 | remote-endpoint = <&tcon0_in_mixer0>; |
| 139 | }; |
| 140 | }; |
| 141 | }; |
| 142 | }; |
| 143 | |
| 144 | tcon0: lcd-controller@1c0c000 { |
| 145 | compatible = "allwinner,sun8i-v3s-tcon"; |
| 146 | reg = <0x01c0c000 0x1000>; |
| 147 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 148 | clocks = <&ccu CLK_BUS_TCON0>, |
| 149 | <&ccu CLK_TCON0>; |
| 150 | clock-names = "ahb", |
| 151 | "tcon-ch0"; |
| 152 | clock-output-names = "tcon-pixel-clock"; |
| 153 | resets = <&ccu RST_BUS_TCON0>; |
| 154 | reset-names = "lcd"; |
| 155 | status = "disabled"; |
| 156 | |
| 157 | ports { |
| 158 | #address-cells = <1>; |
| 159 | #size-cells = <0>; |
| 160 | |
| 161 | tcon0_in: port@0 { |
| 162 | #address-cells = <1>; |
| 163 | #size-cells = <0>; |
| 164 | reg = <0>; |
| 165 | |
| 166 | tcon0_in_mixer0: endpoint@0 { |
| 167 | reg = <0>; |
| 168 | remote-endpoint = <&mixer0_out_tcon0>; |
| 169 | }; |
| 170 | }; |
| 171 | |
| 172 | tcon0_out: port@1 { |
| 173 | #address-cells = <1>; |
| 174 | #size-cells = <0>; |
| 175 | reg = <1>; |
| 176 | }; |
| 177 | }; |
| 178 | }; |
| 179 | |
| 180 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 181 | mmc0: mmc@1c0f000 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 182 | compatible = "allwinner,sun7i-a20-mmc"; |
| 183 | reg = <0x01c0f000 0x1000>; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 184 | clocks = <&ccu CLK_BUS_MMC0>, |
| 185 | <&ccu CLK_MMC0>, |
| 186 | <&ccu CLK_MMC0_OUTPUT>, |
| 187 | <&ccu CLK_MMC0_SAMPLE>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 188 | clock-names = "ahb", |
| 189 | "mmc", |
| 190 | "output", |
| 191 | "sample"; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 192 | resets = <&ccu RST_BUS_MMC0>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 193 | reset-names = "ahb"; |
| 194 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| 195 | status = "disabled"; |
| 196 | #address-cells = <1>; |
| 197 | #size-cells = <0>; |
| 198 | }; |
| 199 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 200 | mmc1: mmc@1c10000 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 201 | compatible = "allwinner,sun7i-a20-mmc"; |
| 202 | reg = <0x01c10000 0x1000>; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 203 | clocks = <&ccu CLK_BUS_MMC1>, |
| 204 | <&ccu CLK_MMC1>, |
| 205 | <&ccu CLK_MMC1_OUTPUT>, |
| 206 | <&ccu CLK_MMC1_SAMPLE>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 207 | clock-names = "ahb", |
| 208 | "mmc", |
| 209 | "output", |
| 210 | "sample"; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 211 | resets = <&ccu RST_BUS_MMC1>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 212 | reset-names = "ahb"; |
| 213 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
Icenowy Zheng | be3c139 | 2017-05-15 16:40:00 +0800 | [diff] [blame] | 214 | pinctrl-names = "default"; |
| 215 | pinctrl-0 = <&mmc1_pins>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 216 | status = "disabled"; |
| 217 | #address-cells = <1>; |
| 218 | #size-cells = <0>; |
| 219 | }; |
| 220 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 221 | mmc2: mmc@1c11000 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 222 | compatible = "allwinner,sun7i-a20-mmc"; |
| 223 | reg = <0x01c11000 0x1000>; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 224 | clocks = <&ccu CLK_BUS_MMC2>, |
| 225 | <&ccu CLK_MMC2>, |
| 226 | <&ccu CLK_MMC2_OUTPUT>, |
| 227 | <&ccu CLK_MMC2_SAMPLE>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 228 | clock-names = "ahb", |
| 229 | "mmc", |
| 230 | "output", |
| 231 | "sample"; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 232 | resets = <&ccu RST_BUS_MMC2>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 233 | reset-names = "ahb"; |
| 234 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| 235 | status = "disabled"; |
| 236 | #address-cells = <1>; |
| 237 | #size-cells = <0>; |
| 238 | }; |
| 239 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 240 | usb_otg: usb@1c19000 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 241 | compatible = "allwinner,sun8i-h3-musb"; |
| 242 | reg = <0x01c19000 0x0400>; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 243 | clocks = <&ccu CLK_BUS_OTG>; |
| 244 | resets = <&ccu RST_BUS_OTG>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 245 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| 246 | interrupt-names = "mc"; |
| 247 | phys = <&usbphy 0>; |
| 248 | phy-names = "usb"; |
| 249 | extcon = <&usbphy 0>; |
| 250 | status = "disabled"; |
| 251 | }; |
| 252 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 253 | usbphy: phy@1c19400 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 254 | compatible = "allwinner,sun8i-v3s-usb-phy"; |
| 255 | reg = <0x01c19400 0x2c>, |
| 256 | <0x01c1a800 0x4>; |
| 257 | reg-names = "phy_ctrl", |
| 258 | "pmu0"; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 259 | clocks = <&ccu CLK_USB_PHY0>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 260 | clock-names = "usb0_phy"; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 261 | resets = <&ccu RST_USB_PHY0>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 262 | reset-names = "usb0_reset"; |
| 263 | status = "disabled"; |
| 264 | #phy-cells = <1>; |
| 265 | }; |
| 266 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 267 | ccu: clock@1c20000 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 268 | compatible = "allwinner,sun8i-v3s-ccu"; |
| 269 | reg = <0x01c20000 0x400>; |
| 270 | clocks = <&osc24M>, <&osc32k>; |
| 271 | clock-names = "hosc", "losc"; |
| 272 | #clock-cells = <1>; |
| 273 | #reset-cells = <1>; |
| 274 | }; |
| 275 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 276 | rtc: rtc@1c20400 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 277 | compatible = "allwinner,sun6i-a31-rtc"; |
| 278 | reg = <0x01c20400 0x54>; |
| 279 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| 280 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| 281 | }; |
| 282 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 283 | pio: pinctrl@1c20800 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 284 | compatible = "allwinner,sun8i-v3s-pinctrl"; |
| 285 | reg = <0x01c20800 0x400>; |
| 286 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| 287 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 288 | clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 289 | clock-names = "apb", "hosc", "losc"; |
| 290 | gpio-controller; |
| 291 | #gpio-cells = <3>; |
| 292 | interrupt-controller; |
| 293 | #interrupt-cells = <3>; |
| 294 | |
Maxime Ripard | 980cd9a1 | 2018-11-07 10:58:01 +0100 | [diff] [blame] | 295 | i2c0_pins: i2c0-pins { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 296 | pins = "PB6", "PB7"; |
| 297 | function = "i2c0"; |
| 298 | }; |
| 299 | |
Maxime Ripard | 980cd9a1 | 2018-11-07 10:58:01 +0100 | [diff] [blame] | 300 | uart0_pb_pins: uart0-pb-pins { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 301 | pins = "PB8", "PB9"; |
| 302 | function = "uart0"; |
| 303 | }; |
| 304 | |
Maxime Ripard | 980cd9a1 | 2018-11-07 10:58:01 +0100 | [diff] [blame] | 305 | mmc0_pins: mmc0-pins { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 306 | pins = "PF0", "PF1", "PF2", "PF3", |
| 307 | "PF4", "PF5"; |
| 308 | function = "mmc0"; |
| 309 | drive-strength = <30>; |
| 310 | bias-pull-up; |
| 311 | }; |
Icenowy Zheng | be3c139 | 2017-05-15 16:40:00 +0800 | [diff] [blame] | 312 | |
Maxime Ripard | 980cd9a1 | 2018-11-07 10:58:01 +0100 | [diff] [blame] | 313 | mmc1_pins: mmc1-pins { |
Icenowy Zheng | be3c139 | 2017-05-15 16:40:00 +0800 | [diff] [blame] | 314 | pins = "PG0", "PG1", "PG2", "PG3", |
| 315 | "PG4", "PG5"; |
| 316 | function = "mmc1"; |
| 317 | drive-strength = <30>; |
| 318 | bias-pull-up; |
| 319 | }; |
Icenowy Zheng | 2a451bf | 2017-05-17 21:52:57 +0800 | [diff] [blame] | 320 | |
Maxime Ripard | 980cd9a1 | 2018-11-07 10:58:01 +0100 | [diff] [blame] | 321 | spi0_pins: spi0-pins { |
Icenowy Zheng | 2a451bf | 2017-05-17 21:52:57 +0800 | [diff] [blame] | 322 | pins = "PC0", "PC1", "PC2", "PC3"; |
| 323 | function = "spi0"; |
| 324 | }; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 325 | }; |
| 326 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 327 | timer@1c20c00 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 328 | compatible = "allwinner,sun4i-a10-timer"; |
| 329 | reg = <0x01c20c00 0xa0>; |
| 330 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
| 331 | <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 332 | clocks = <&osc24M>; |
| 333 | }; |
| 334 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 335 | wdt0: watchdog@1c20ca0 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 336 | compatible = "allwinner,sun6i-a31-wdt"; |
| 337 | reg = <0x01c20ca0 0x20>; |
| 338 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| 339 | }; |
| 340 | |
Icenowy Zheng | 37eac4f | 2017-05-15 16:39:59 +0800 | [diff] [blame] | 341 | lradc: lradc@1c22800 { |
| 342 | compatible = "allwinner,sun4i-a10-lradc-keys"; |
| 343 | reg = <0x01c22800 0x400>; |
| 344 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 345 | status = "disabled"; |
| 346 | }; |
| 347 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 348 | uart0: serial@1c28000 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 349 | compatible = "snps,dw-apb-uart"; |
| 350 | reg = <0x01c28000 0x400>; |
| 351 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
| 352 | reg-shift = <2>; |
| 353 | reg-io-width = <4>; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 354 | clocks = <&ccu CLK_BUS_UART0>; |
| 355 | resets = <&ccu RST_BUS_UART0>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 356 | status = "disabled"; |
| 357 | }; |
| 358 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 359 | uart1: serial@1c28400 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 360 | compatible = "snps,dw-apb-uart"; |
| 361 | reg = <0x01c28400 0x400>; |
| 362 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| 363 | reg-shift = <2>; |
| 364 | reg-io-width = <4>; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 365 | clocks = <&ccu CLK_BUS_UART1>; |
| 366 | resets = <&ccu RST_BUS_UART1>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 367 | status = "disabled"; |
| 368 | }; |
| 369 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 370 | uart2: serial@1c28800 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 371 | compatible = "snps,dw-apb-uart"; |
| 372 | reg = <0x01c28800 0x400>; |
| 373 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 374 | reg-shift = <2>; |
| 375 | reg-io-width = <4>; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 376 | clocks = <&ccu CLK_BUS_UART2>; |
| 377 | resets = <&ccu RST_BUS_UART2>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 378 | status = "disabled"; |
| 379 | }; |
| 380 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 381 | i2c0: i2c@1c2ac00 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 382 | compatible = "allwinner,sun6i-a31-i2c"; |
| 383 | reg = <0x01c2ac00 0x400>; |
| 384 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 385 | clocks = <&ccu CLK_BUS_I2C0>; |
| 386 | resets = <&ccu RST_BUS_I2C0>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 387 | pinctrl-names = "default"; |
| 388 | pinctrl-0 = <&i2c0_pins>; |
| 389 | status = "disabled"; |
| 390 | #address-cells = <1>; |
| 391 | #size-cells = <0>; |
| 392 | }; |
| 393 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 394 | i2c1: i2c@1c2b000 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 395 | compatible = "allwinner,sun6i-a31-i2c"; |
| 396 | reg = <0x01c2b000 0x400>; |
| 397 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
Icenowy Zheng | 8378be8 | 2017-05-15 16:39:58 +0800 | [diff] [blame] | 398 | clocks = <&ccu CLK_BUS_I2C1>; |
| 399 | resets = <&ccu RST_BUS_I2C1>; |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 400 | status = "disabled"; |
| 401 | #address-cells = <1>; |
| 402 | #size-cells = <0>; |
| 403 | }; |
| 404 | |
Icenowy Zheng | 2a451bf | 2017-05-17 21:52:57 +0800 | [diff] [blame] | 405 | spi0: spi@1c68000 { |
| 406 | compatible = "allwinner,sun8i-h3-spi"; |
| 407 | reg = <0x01c68000 0x1000>; |
| 408 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| 409 | clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; |
| 410 | clock-names = "ahb", "mod"; |
| 411 | pinctrl-names = "default"; |
| 412 | pinctrl-0 = <&spi0_pins>; |
| 413 | resets = <&ccu RST_BUS_SPI0>; |
| 414 | status = "disabled"; |
| 415 | #address-cells = <1>; |
| 416 | #size-cells = <0>; |
| 417 | }; |
| 418 | |
Rob Herring | 8dccafa | 2017-10-13 12:54:51 -0500 | [diff] [blame] | 419 | gic: interrupt-controller@1c81000 { |
Icenowy Zheng | f989086 | 2017-01-20 01:54:47 +0800 | [diff] [blame] | 420 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
| 421 | reg = <0x01c81000 0x1000>, |
| 422 | <0x01c82000 0x1000>, |
| 423 | <0x01c84000 0x2000>, |
| 424 | <0x01c86000 0x2000>; |
| 425 | interrupt-controller; |
| 426 | #interrupt-cells = <3>; |
| 427 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 428 | }; |
| 429 | }; |
| 430 | }; |