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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * SNI specific definitions
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1997, 1998 by Ralf Baechle
Thomas Bogendoerferc066a322006-12-28 18:22:32 +01009 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 */
11#ifndef __ASM_SNI_H
12#define __ASM_SNI_H
13
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010014extern unsigned int sni_brd_type;
15
16#define SNI_BRD_10 2
17#define SNI_BRD_10NEW 3
18#define SNI_BRD_TOWER_OASIC 4
19#define SNI_BRD_MINITOWER 5
20#define SNI_BRD_PCI_TOWER 6
21#define SNI_BRD_RM200 7
22#define SNI_BRD_PCI_MTOWER 8
23#define SNI_BRD_PCI_DESKTOP 9
24#define SNI_BRD_PCI_TOWER_CPLUS 10
25#define SNI_BRD_PCI_MTOWER_CPLUS 11
26
27/* RM400 cpu types */
28#define SNI_CPU_M8021 0x01
29#define SNI_CPU_M8030 0x04
30#define SNI_CPU_M8031 0x06
31#define SNI_CPU_M8034 0x0f
32#define SNI_CPU_M8037 0x07
33#define SNI_CPU_M8040 0x05
34#define SNI_CPU_M8043 0x09
35#define SNI_CPU_M8050 0x0b
36#define SNI_CPU_M8053 0x0d
37
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#define SNI_PORT_BASE 0xb4000000
39
Thomas Bogendoerferc066a322006-12-28 18:22:32 +010040#ifndef __MIPSEL__
41/*
42 * ASIC PCI registers for big endian configuration.
43 */
44#define PCIMT_UCONF 0xbfff0004
45#define PCIMT_IOADTIMEOUT2 0xbfff000c
46#define PCIMT_IOMEMCONF 0xbfff0014
47#define PCIMT_IOMMU 0xbfff001c
48#define PCIMT_IOADTIMEOUT1 0xbfff0024
49#define PCIMT_DMAACCESS 0xbfff002c
50#define PCIMT_DMAHIT 0xbfff0034
51#define PCIMT_ERRSTATUS 0xbfff003c
52#define PCIMT_ERRADDR 0xbfff0044
53#define PCIMT_SYNDROME 0xbfff004c
54#define PCIMT_ITPEND 0xbfff0054
55#define IT_INT2 0x01
56#define IT_INTD 0x02
57#define IT_INTC 0x04
58#define IT_INTB 0x08
59#define IT_INTA 0x10
60#define IT_EISA 0x20
61#define IT_SCSI 0x40
62#define IT_ETH 0x80
63#define PCIMT_IRQSEL 0xbfff005c
64#define PCIMT_TESTMEM 0xbfff0064
65#define PCIMT_ECCREG 0xbfff006c
66#define PCIMT_CONFIG_ADDRESS 0xbfff0074
67#define PCIMT_ASIC_ID 0xbfff007c /* read */
68#define PCIMT_SOFT_RESET 0xbfff007c /* write */
69#define PCIMT_PIA_OE 0xbfff0084
70#define PCIMT_PIA_DATAOUT 0xbfff008c
71#define PCIMT_PIA_DATAIN 0xbfff0094
72#define PCIMT_CACHECONF 0xbfff009c
73#define PCIMT_INVSPACE 0xbfff00a4
74#else
Linus Torvalds1da177e2005-04-16 15:20:36 -070075/*
76 * ASIC PCI registers for little endian configuration.
77 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070078#define PCIMT_UCONF 0xbfff0000
79#define PCIMT_IOADTIMEOUT2 0xbfff0008
80#define PCIMT_IOMEMCONF 0xbfff0010
81#define PCIMT_IOMMU 0xbfff0018
82#define PCIMT_IOADTIMEOUT1 0xbfff0020
83#define PCIMT_DMAACCESS 0xbfff0028
84#define PCIMT_DMAHIT 0xbfff0030
85#define PCIMT_ERRSTATUS 0xbfff0038
86#define PCIMT_ERRADDR 0xbfff0040
87#define PCIMT_SYNDROME 0xbfff0048
88#define PCIMT_ITPEND 0xbfff0050
89#define IT_INT2 0x01
90#define IT_INTD 0x02
91#define IT_INTC 0x04
92#define IT_INTB 0x08
93#define IT_INTA 0x10
94#define IT_EISA 0x20
95#define IT_SCSI 0x40
96#define IT_ETH 0x80
97#define PCIMT_IRQSEL 0xbfff0058
98#define PCIMT_TESTMEM 0xbfff0060
99#define PCIMT_ECCREG 0xbfff0068
100#define PCIMT_CONFIG_ADDRESS 0xbfff0070
101#define PCIMT_ASIC_ID 0xbfff0078 /* read */
102#define PCIMT_SOFT_RESET 0xbfff0078 /* write */
103#define PCIMT_PIA_OE 0xbfff0080
104#define PCIMT_PIA_DATAOUT 0xbfff0088
105#define PCIMT_PIA_DATAIN 0xbfff0090
106#define PCIMT_CACHECONF 0xbfff0098
107#define PCIMT_INVSPACE 0xbfff00a0
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100108#endif
109
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110#define PCIMT_PCI_CONF 0xbfff0100
111
112/*
Thomas Bogendoerfer4a0312f2006-06-13 13:59:01 +0200113 * Data port for the PCI bus in IO space
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 */
Thomas Bogendoerfer4a0312f2006-06-13 13:59:01 +0200115#define PCIMT_CONFIG_DATA 0x0cfc
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116
117/*
118 * Board specific registers
119 */
120#define PCIMT_CSMSR 0xbfd00000
121#define PCIMT_CSSWITCH 0xbfd10000
122#define PCIMT_CSITPEND 0xbfd20000
123#define PCIMT_AUTO_PO_EN 0xbfd30000
124#define PCIMT_CLR_TEMP 0xbfd40000
125#define PCIMT_AUTO_PO_DIS 0xbfd50000
126#define PCIMT_EXMSR 0xbfd60000
127#define PCIMT_UNUSED1 0xbfd70000
128#define PCIMT_CSWCSM 0xbfd80000
129#define PCIMT_UNUSED2 0xbfd90000
130#define PCIMT_CSLED 0xbfda0000
131#define PCIMT_CSMAPISA 0xbfdb0000
132#define PCIMT_CSRSTBP 0xbfdc0000
133#define PCIMT_CLRPOFF 0xbfdd0000
134#define PCIMT_CSTIMER 0xbfde0000
135#define PCIMT_PWDN 0xbfdf0000
136
137/*
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100138 * A20R based boards
139 */
140#define A20R_PT_CLOCK_BASE 0xbc040000
141#define A20R_PT_TIM0_ACK 0xbc050000
142#define A20R_PT_TIM1_ACK 0xbc060000
143
Thomas Bogendoerferf13cc012007-02-23 21:39:38 +0100144#define SNI_MIPS_IRQ_CPU_TIMER (MIPS_CPU_IRQ_BASE+7)
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100145
Thomas Bogendoerferf13cc012007-02-23 21:39:38 +0100146#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100147#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
148
149#define SNI_DS1216_A20R_BASE 0xbc081ffc
150#define SNI_DS1216_RM200_BASE 0xbcd41ffc
151
152#define SNI_PCIT_INT_REG 0xbfff000c
153
154#define SNI_PCIT_INT_START 24
155#define SNI_PCIT_INT_END 30
156
Thomas Bogendoerferf13cc012007-02-23 21:39:38 +0100157#define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5)
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100158#define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0)
159#define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1)
160#define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2)
161#define PCIT_IRQ_INTD (SNI_PCIT_INT_START + 3)
162#define PCIT_IRQ_SCSI0 (SNI_PCIT_INT_START + 4)
163#define PCIT_IRQ_SCSI1 (SNI_PCIT_INT_START + 5)
164
165
166/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167 * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned
168 * to the other interrupts generated by ASIC PCI.
169 *
170 * INT2 is a wired-or of the push button interrupt, high temperature interrupt
171 * ASIC PCI interrupt.
172 */
173#define PCIMT_KEYBOARD_IRQ 1
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100174#define PCIMT_IRQ_INT2 24
175#define PCIMT_IRQ_INTD 25
176#define PCIMT_IRQ_INTC 26
177#define PCIMT_IRQ_INTB 27
178#define PCIMT_IRQ_INTA 28
179#define PCIMT_IRQ_EISA 29
180#define PCIMT_IRQ_SCSI 30
181
Thomas Bogendoerferf13cc012007-02-23 21:39:38 +0100182#define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6)
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100183
184#if 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185#define PCIMT_IRQ_TEMPERATURE 24
186#define PCIMT_IRQ_EISA_NMI 25
187#define PCIMT_IRQ_POWER_OFF 26
188#define PCIMT_IRQ_BUTTON 27
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100189#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190
191/*
192 * Base address for the mapped 16mb EISA bus segment.
193 */
194#define PCIMT_EISA_BASE 0xb0000000
195
196/* PCI EISA Interrupt acknowledge */
197#define PCIMT_INT_ACKNOWLEDGE 0xba000000
198
Thomas Bogendoerferc066a322006-12-28 18:22:32 +0100199/* board specific init functions */
200extern void sni_a20r_init (void);
201extern void sni_pcit_init (void);
202extern void sni_rm200_init (void);
203extern void sni_pcimt_init (void);
204
205/* board specific irq init functions */
206extern void sni_a20r_irq_init (void);
207extern void sni_pcit_irq_init (void);
208extern void sni_pcit_cplus_irq_init (void);
209extern void sni_rm200_irq_init (void);
210extern void sni_pcimt_irq_init (void);
211
212/* timer inits */
213extern void sni_cpu_time_init(void);
214
215/* common irq stuff */
216extern void (*sni_hwint)(void);
217extern struct irqaction sni_isa_irq;
218
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219#endif /* __ASM_SNI_H */