Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * macserial.h: Definitions for the Macintosh Z8530 serial driver. |
| 3 | * |
| 4 | * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras. |
| 5 | * |
| 6 | * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) |
| 7 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) |
| 8 | */ |
| 9 | #ifndef _MACSERIAL_H |
| 10 | #define _MACSERIAL_H |
| 11 | |
| 12 | #include <linux/spinlock.h> |
| 13 | |
| 14 | #define NUM_ZSREGS 16 |
| 15 | |
| 16 | struct serial_struct { |
| 17 | int type; |
| 18 | int line; |
| 19 | int port; |
| 20 | int irq; |
| 21 | int flags; |
| 22 | int xmit_fifo_size; |
| 23 | int custom_divisor; |
| 24 | int baud_base; |
| 25 | unsigned short close_delay; |
| 26 | char reserved_char[2]; |
| 27 | int hub6; |
| 28 | unsigned short closing_wait; /* time to wait before closing */ |
| 29 | unsigned short closing_wait2; /* no longer used... */ |
| 30 | int reserved[4]; |
| 31 | }; |
| 32 | |
| 33 | /* |
| 34 | * For the close wait times, 0 means wait forever for serial port to |
| 35 | * flush its output. 65535 means don't wait at all. |
| 36 | */ |
| 37 | #define ZILOG_CLOSING_WAIT_INF 0 |
| 38 | #define ZILOG_CLOSING_WAIT_NONE 65535 |
| 39 | |
| 40 | /* |
| 41 | * Definitions for ZILOG_struct (and serial_struct) flags field |
| 42 | */ |
| 43 | #define ZILOG_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes |
| 44 | * on the callout port */ |
| 45 | #define ZILOG_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */ |
| 46 | #define ZILOG_SAK 0x0004 /* Secure Attention Key (Orange book) */ |
| 47 | #define ZILOG_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */ |
| 48 | |
| 49 | #define ZILOG_SPD_MASK 0x0030 |
| 50 | #define ZILOG_SPD_HI 0x0010 /* Use 56000 instead of 38400 bps */ |
| 51 | |
| 52 | #define ZILOG_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */ |
| 53 | #define ZILOG_SPD_CUST 0x0030 /* Use user-specified divisor */ |
| 54 | |
| 55 | #define ZILOG_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */ |
| 56 | #define ZILOG_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */ |
| 57 | #define ZILOG_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */ |
| 58 | #define ZILOG_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */ |
| 59 | #define ZILOG_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */ |
| 60 | |
| 61 | #define ZILOG_FLAGS 0x0FFF /* Possible legal ZILOG flags */ |
| 62 | #define ZILOG_USR_MASK 0x0430 /* Legal flags that non-privileged |
| 63 | * users can set or reset */ |
| 64 | |
| 65 | /* Internal flags used only by kernel/chr_drv/serial.c */ |
| 66 | #define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */ |
| 67 | #define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */ |
| 68 | #define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */ |
| 69 | #define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */ |
| 70 | #define ZILOG_CLOSING 0x08000000 /* Serial port is closing */ |
| 71 | #define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */ |
| 72 | #define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */ |
| 73 | #define ZILOG_SLEEPING 0x01000000 /* have shut it down for sleep */ |
| 74 | |
| 75 | /* Software state per channel */ |
| 76 | |
| 77 | #ifdef __KERNEL__ |
| 78 | /* |
| 79 | * This is our internal structure for each serial port's state. |
| 80 | * |
| 81 | * Many fields are paralleled by the structure used by the serial_struct |
| 82 | * structure. |
| 83 | * |
| 84 | * For definitions of the flags field, see tty.h |
| 85 | */ |
| 86 | |
| 87 | struct mac_serial; |
| 88 | |
| 89 | struct mac_zschannel { |
| 90 | volatile unsigned char* control; |
| 91 | volatile unsigned char* data; |
| 92 | spinlock_t lock; |
| 93 | /* Used for debugging */ |
| 94 | struct mac_serial* parent; |
| 95 | }; |
| 96 | |
| 97 | struct mac_dma { |
| 98 | volatile struct dbdma_regs dma; |
| 99 | volatile unsigned short res_count; |
| 100 | volatile unsigned short command; |
| 101 | volatile unsigned int buf_addr; |
| 102 | }; |
| 103 | |
| 104 | struct mac_serial { |
| 105 | struct mac_serial *zs_next; /* For IRQ servicing chain */ |
| 106 | struct mac_zschannel *zs_channel; /* Channel registers */ |
| 107 | struct mac_zschannel *zs_chan_a; /* A side registers */ |
| 108 | unsigned char read_reg_zero; |
| 109 | struct device_node* dev_node; |
| 110 | spinlock_t lock; |
| 111 | |
| 112 | char soft_carrier; /* Use soft carrier on this channel */ |
| 113 | char break_abort; /* Is serial console in, so process brk/abrt */ |
| 114 | char kgdb_channel; /* Kgdb is running on this channel */ |
| 115 | char is_cons; /* Is this our console. */ |
| 116 | char is_internal_modem; /* is connected to an internal modem */ |
| 117 | char is_irda; /* is connected to an IrDA codec */ |
| 118 | int port_type; /* Port type for pmac_feature */ |
| 119 | unsigned char tx_active; /* character is being xmitted */ |
| 120 | unsigned char tx_stopped; /* output is suspended */ |
| 121 | unsigned char power_wait; /* waiting for power-up delay to expire */ |
| 122 | |
| 123 | /* We need to know the current clock divisor |
| 124 | * to read the bps rate the chip has currently |
| 125 | * loaded. |
| 126 | */ |
| 127 | unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */ |
| 128 | int zs_baud; |
| 129 | |
| 130 | /* Current write register values */ |
| 131 | unsigned char curregs[NUM_ZSREGS]; |
| 132 | |
| 133 | /* Values we need to set next opportunity */ |
| 134 | unsigned char pendregs[NUM_ZSREGS]; |
| 135 | |
| 136 | char change_needed; |
| 137 | |
| 138 | int magic; |
| 139 | int baud_base; |
| 140 | int port; |
| 141 | int irq; |
| 142 | int flags; /* defined in tty.h */ |
| 143 | int type; /* UART type */ |
| 144 | struct tty_struct *tty; |
| 145 | int read_status_mask; |
| 146 | int ignore_status_mask; |
| 147 | int timeout; |
| 148 | int xmit_fifo_size; |
| 149 | int custom_divisor; |
| 150 | int x_char; /* xon/xoff character */ |
| 151 | int close_delay; |
| 152 | unsigned short closing_wait; |
| 153 | unsigned short closing_wait2; |
| 154 | unsigned long event; |
| 155 | unsigned long last_active; |
| 156 | int line; |
| 157 | int count; /* # of fd on device */ |
| 158 | int blocked_open; /* # of blocked opens */ |
| 159 | unsigned char *xmit_buf; |
| 160 | int xmit_head; |
| 161 | int xmit_tail; |
| 162 | int xmit_cnt; |
| 163 | struct work_struct tqueue; |
| 164 | wait_queue_head_t open_wait; |
| 165 | wait_queue_head_t close_wait; |
| 166 | |
| 167 | volatile struct dbdma_regs *tx_dma; |
| 168 | int tx_dma_irq; |
| 169 | volatile struct dbdma_cmd *tx_cmds; |
| 170 | volatile struct mac_dma *rx; |
| 171 | int rx_dma_irq; |
| 172 | volatile struct dbdma_cmd **rx_cmds; |
| 173 | unsigned char **rx_char_buf; |
| 174 | unsigned char **rx_flag_buf; |
| 175 | #define RX_BUF_SIZE 256 |
| 176 | int rx_nbuf; |
| 177 | int rx_done_bytes; |
| 178 | int rx_ubuf; |
| 179 | int rx_fbuf; |
| 180 | #define RX_NO_FBUF (-1) |
| 181 | int rx_cbuf; |
| 182 | spinlock_t rx_dma_lock; |
| 183 | int has_dma; |
| 184 | int dma_initted; |
| 185 | void *dma_priv; |
| 186 | struct timer_list poll_dma_timer; |
| 187 | #define RX_DMA_TIMER (jiffies + 10*HZ/1000) |
| 188 | |
| 189 | struct timer_list powerup_timer; |
| 190 | }; |
| 191 | |
| 192 | |
| 193 | #define SERIAL_MAGIC 0x5301 |
| 194 | |
| 195 | /* |
| 196 | * The size of the serial xmit buffer is 1 page, or 4096 bytes |
| 197 | */ |
| 198 | #define SERIAL_XMIT_SIZE 4096 |
| 199 | |
| 200 | /* |
| 201 | * Events are used to schedule things to happen at timer-interrupt |
| 202 | * time, instead of at rs interrupt time. |
| 203 | */ |
| 204 | #define RS_EVENT_WRITE_WAKEUP 0 |
| 205 | |
| 206 | #endif /* __KERNEL__ */ |
| 207 | |
| 208 | /* Conversion routines to/from brg time constants from/to bits |
| 209 | * per second. |
| 210 | */ |
| 211 | #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) |
| 212 | #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) |
| 213 | |
| 214 | /* The Zilog register set */ |
| 215 | |
| 216 | #define FLAG 0x7e |
| 217 | |
| 218 | /* Write Register 0 */ |
| 219 | #define R0 0 /* Register selects */ |
| 220 | #define R1 1 |
| 221 | #define R2 2 |
| 222 | #define R3 3 |
| 223 | #define R4 4 |
| 224 | #define R5 5 |
| 225 | #define R6 6 |
| 226 | #define R7 7 |
| 227 | #define R8 8 |
| 228 | #define R9 9 |
| 229 | #define R10 10 |
| 230 | #define R11 11 |
| 231 | #define R12 12 |
| 232 | #define R13 13 |
| 233 | #define R14 14 |
| 234 | #define R15 15 |
| 235 | |
| 236 | #define NULLCODE 0 /* Null Code */ |
| 237 | #define POINT_HIGH 0x8 /* Select upper half of registers */ |
| 238 | #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ |
| 239 | #define SEND_ABORT 0x18 /* HDLC Abort */ |
| 240 | #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ |
| 241 | #define RES_Tx_P 0x28 /* Reset TxINT Pending */ |
| 242 | #define ERR_RES 0x30 /* Error Reset */ |
| 243 | #define RES_H_IUS 0x38 /* Reset highest IUS */ |
| 244 | |
| 245 | #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ |
| 246 | #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ |
| 247 | #define RES_EOM_L 0xC0 /* Reset EOM latch */ |
| 248 | |
| 249 | /* Write Register 1 */ |
| 250 | |
| 251 | #define EXT_INT_ENAB 0x1 /* Ext Int Enable */ |
| 252 | #define TxINT_ENAB 0x2 /* Tx Int Enable */ |
| 253 | #define PAR_SPEC 0x4 /* Parity is special condition */ |
| 254 | |
| 255 | #define RxINT_DISAB 0 /* Rx Int Disable */ |
| 256 | #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */ |
| 257 | #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */ |
| 258 | #define INT_ERR_Rx 0x18 /* Int on error only */ |
| 259 | |
| 260 | #define WT_RDY_RT 0x20 /* W/Req reflects recv if 1, xmit if 0 */ |
| 261 | #define WT_FN_RDYFN 0x40 /* W/Req pin is DMA request if 1, wait if 0 */ |
| 262 | #define WT_RDY_ENAB 0x80 /* Enable W/Req pin */ |
| 263 | |
| 264 | /* Write Register #2 (Interrupt Vector) */ |
| 265 | |
| 266 | /* Write Register 3 */ |
| 267 | |
| 268 | #define RxENABLE 0x1 /* Rx Enable */ |
| 269 | #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ |
| 270 | #define ADD_SM 0x4 /* Address Search Mode (SDLC) */ |
| 271 | #define RxCRC_ENAB 0x8 /* Rx CRC Enable */ |
| 272 | #define ENT_HM 0x10 /* Enter Hunt Mode */ |
| 273 | #define AUTO_ENAB 0x20 /* Auto Enables */ |
| 274 | #define Rx5 0x0 /* Rx 5 Bits/Character */ |
| 275 | #define Rx7 0x40 /* Rx 7 Bits/Character */ |
| 276 | #define Rx6 0x80 /* Rx 6 Bits/Character */ |
| 277 | #define Rx8 0xc0 /* Rx 8 Bits/Character */ |
| 278 | #define RxNBITS_MASK 0xc0 |
| 279 | |
| 280 | /* Write Register 4 */ |
| 281 | |
| 282 | #define PAR_ENA 0x1 /* Parity Enable */ |
| 283 | #define PAR_EVEN 0x2 /* Parity Even/Odd* */ |
| 284 | |
| 285 | #define SYNC_ENAB 0 /* Sync Modes Enable */ |
| 286 | #define SB1 0x4 /* 1 stop bit/char */ |
| 287 | #define SB15 0x8 /* 1.5 stop bits/char */ |
| 288 | #define SB2 0xc /* 2 stop bits/char */ |
| 289 | #define SB_MASK 0xc |
| 290 | |
| 291 | #define MONSYNC 0 /* 8 Bit Sync character */ |
| 292 | #define BISYNC 0x10 /* 16 bit sync character */ |
| 293 | #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ |
| 294 | #define EXTSYNC 0x30 /* External Sync Mode */ |
| 295 | |
| 296 | #define X1CLK 0x0 /* x1 clock mode */ |
| 297 | #define X16CLK 0x40 /* x16 clock mode */ |
| 298 | #define X32CLK 0x80 /* x32 clock mode */ |
| 299 | #define X64CLK 0xC0 /* x64 clock mode */ |
| 300 | #define XCLK_MASK 0xC0 |
| 301 | |
| 302 | /* Write Register 5 */ |
| 303 | |
| 304 | #define TxCRC_ENAB 0x1 /* Tx CRC Enable */ |
| 305 | #define RTS 0x2 /* RTS */ |
| 306 | #define SDLC_CRC 0x4 /* SDLC/CRC-16 */ |
| 307 | #define TxENAB 0x8 /* Tx Enable */ |
| 308 | #define SND_BRK 0x10 /* Send Break */ |
| 309 | #define Tx5 0x0 /* Tx 5 bits (or less)/character */ |
| 310 | #define Tx7 0x20 /* Tx 7 bits/character */ |
| 311 | #define Tx6 0x40 /* Tx 6 bits/character */ |
| 312 | #define Tx8 0x60 /* Tx 8 bits/character */ |
| 313 | #define TxNBITS_MASK 0x60 |
| 314 | #define DTR 0x80 /* DTR */ |
| 315 | |
| 316 | /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */ |
| 317 | |
| 318 | /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */ |
| 319 | |
| 320 | /* Write Register 7' (Some enhanced feature control) */ |
| 321 | #define ENEXREAD 0x40 /* Enable read of some write registers */ |
| 322 | |
| 323 | /* Write Register 8 (transmit buffer) */ |
| 324 | |
| 325 | /* Write Register 9 (Master interrupt control) */ |
| 326 | #define VIS 1 /* Vector Includes Status */ |
| 327 | #define NV 2 /* No Vector */ |
| 328 | #define DLC 4 /* Disable Lower Chain */ |
| 329 | #define MIE 8 /* Master Interrupt Enable */ |
| 330 | #define STATHI 0x10 /* Status high */ |
| 331 | #define NORESET 0 /* No reset on write to R9 */ |
| 332 | #define CHRB 0x40 /* Reset channel B */ |
| 333 | #define CHRA 0x80 /* Reset channel A */ |
| 334 | #define FHWRES 0xc0 /* Force hardware reset */ |
| 335 | |
| 336 | /* Write Register 10 (misc control bits) */ |
| 337 | #define BIT6 1 /* 6 bit/8bit sync */ |
| 338 | #define LOOPMODE 2 /* SDLC Loop mode */ |
| 339 | #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */ |
| 340 | #define MARKIDLE 8 /* Mark/flag on idle */ |
| 341 | #define GAOP 0x10 /* Go active on poll */ |
| 342 | #define NRZ 0 /* NRZ mode */ |
| 343 | #define NRZI 0x20 /* NRZI mode */ |
| 344 | #define FM1 0x40 /* FM1 (transition = 1) */ |
| 345 | #define FM0 0x60 /* FM0 (transition = 0) */ |
| 346 | #define CRCPS 0x80 /* CRC Preset I/O */ |
| 347 | |
| 348 | /* Write Register 11 (Clock Mode control) */ |
| 349 | #define TRxCXT 0 /* TRxC = Xtal output */ |
| 350 | #define TRxCTC 1 /* TRxC = Transmit clock */ |
| 351 | #define TRxCBR 2 /* TRxC = BR Generator Output */ |
| 352 | #define TRxCDP 3 /* TRxC = DPLL output */ |
| 353 | #define TRxCOI 4 /* TRxC O/I */ |
| 354 | #define TCRTxCP 0 /* Transmit clock = RTxC pin */ |
| 355 | #define TCTRxCP 8 /* Transmit clock = TRxC pin */ |
| 356 | #define TCBR 0x10 /* Transmit clock = BR Generator output */ |
| 357 | #define TCDPLL 0x18 /* Transmit clock = DPLL output */ |
| 358 | #define RCRTxCP 0 /* Receive clock = RTxC pin */ |
| 359 | #define RCTRxCP 0x20 /* Receive clock = TRxC pin */ |
| 360 | #define RCBR 0x40 /* Receive clock = BR Generator output */ |
| 361 | #define RCDPLL 0x60 /* Receive clock = DPLL output */ |
| 362 | #define RTxCX 0x80 /* RTxC Xtal/No Xtal */ |
| 363 | |
| 364 | /* Write Register 12 (lower byte of baud rate generator time constant) */ |
| 365 | |
| 366 | /* Write Register 13 (upper byte of baud rate generator time constant) */ |
| 367 | |
| 368 | /* Write Register 14 (Misc control bits) */ |
| 369 | #define BRENABL 1 /* Baud rate generator enable */ |
| 370 | #define BRSRC 2 /* Baud rate generator source */ |
| 371 | #define DTRREQ 4 /* DTR/Request function */ |
| 372 | #define AUTOECHO 8 /* Auto Echo */ |
| 373 | #define LOOPBAK 0x10 /* Local loopback */ |
| 374 | #define SEARCH 0x20 /* Enter search mode */ |
| 375 | #define RMC 0x40 /* Reset missing clock */ |
| 376 | #define DISDPLL 0x60 /* Disable DPLL */ |
| 377 | #define SSBR 0x80 /* Set DPLL source = BR generator */ |
| 378 | #define SSRTxC 0xa0 /* Set DPLL source = RTxC */ |
| 379 | #define SFMM 0xc0 /* Set FM mode */ |
| 380 | #define SNRZI 0xe0 /* Set NRZI mode */ |
| 381 | |
| 382 | /* Write Register 15 (external/status interrupt control) */ |
| 383 | #define EN85C30 1 /* Enable some 85c30-enhanced registers */ |
| 384 | #define ZCIE 2 /* Zero count IE */ |
| 385 | #define ENSTFIFO 4 /* Enable status FIFO (SDLC) */ |
| 386 | #define DCDIE 8 /* DCD IE */ |
| 387 | #define SYNCIE 0x10 /* Sync/hunt IE */ |
| 388 | #define CTSIE 0x20 /* CTS IE */ |
| 389 | #define TxUIE 0x40 /* Tx Underrun/EOM IE */ |
| 390 | #define BRKIE 0x80 /* Break/Abort IE */ |
| 391 | |
| 392 | |
| 393 | /* Read Register 0 */ |
| 394 | #define Rx_CH_AV 0x1 /* Rx Character Available */ |
| 395 | #define ZCOUNT 0x2 /* Zero count */ |
| 396 | #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */ |
| 397 | #define DCD 0x8 /* DCD */ |
| 398 | #define SYNC_HUNT 0x10 /* Sync/hunt */ |
| 399 | #define CTS 0x20 /* CTS */ |
| 400 | #define TxEOM 0x40 /* Tx underrun */ |
| 401 | #define BRK_ABRT 0x80 /* Break/Abort */ |
| 402 | |
| 403 | /* Read Register 1 */ |
| 404 | #define ALL_SNT 0x1 /* All sent */ |
| 405 | /* Residue Data for 8 Rx bits/char programmed */ |
| 406 | #define RES3 0x8 /* 0/3 */ |
| 407 | #define RES4 0x4 /* 0/4 */ |
| 408 | #define RES5 0xc /* 0/5 */ |
| 409 | #define RES6 0x2 /* 0/6 */ |
| 410 | #define RES7 0xa /* 0/7 */ |
| 411 | #define RES8 0x6 /* 0/8 */ |
| 412 | #define RES18 0xe /* 1/8 */ |
| 413 | #define RES28 0x0 /* 2/8 */ |
| 414 | /* Special Rx Condition Interrupts */ |
| 415 | #define PAR_ERR 0x10 /* Parity error */ |
| 416 | #define Rx_OVR 0x20 /* Rx Overrun Error */ |
| 417 | #define FRM_ERR 0x40 /* CRC/Framing Error */ |
| 418 | #define END_FR 0x80 /* End of Frame (SDLC) */ |
| 419 | |
| 420 | /* Read Register 2 (channel b only) - Interrupt vector */ |
| 421 | #define CHB_Tx_EMPTY 0x00 |
| 422 | #define CHB_EXT_STAT 0x02 |
| 423 | #define CHB_Rx_AVAIL 0x04 |
| 424 | #define CHB_SPECIAL 0x06 |
| 425 | #define CHA_Tx_EMPTY 0x08 |
| 426 | #define CHA_EXT_STAT 0x0a |
| 427 | #define CHA_Rx_AVAIL 0x0c |
| 428 | #define CHA_SPECIAL 0x0e |
| 429 | #define STATUS_MASK 0x06 |
| 430 | |
| 431 | /* Read Register 3 (interrupt pending register) ch a only */ |
| 432 | #define CHBEXT 0x1 /* Channel B Ext/Stat IP */ |
| 433 | #define CHBTxIP 0x2 /* Channel B Tx IP */ |
| 434 | #define CHBRxIP 0x4 /* Channel B Rx IP */ |
| 435 | #define CHAEXT 0x8 /* Channel A Ext/Stat IP */ |
| 436 | #define CHATxIP 0x10 /* Channel A Tx IP */ |
| 437 | #define CHARxIP 0x20 /* Channel A Rx IP */ |
| 438 | |
| 439 | /* Read Register 8 (receive data register) */ |
| 440 | |
| 441 | /* Read Register 10 (misc status bits) */ |
| 442 | #define ONLOOP 2 /* On loop */ |
| 443 | #define LOOPSEND 0x10 /* Loop sending */ |
| 444 | #define CLK2MIS 0x40 /* Two clocks missing */ |
| 445 | #define CLK1MIS 0x80 /* One clock missing */ |
| 446 | |
| 447 | /* Read Register 12 (lower byte of baud rate generator constant) */ |
| 448 | |
| 449 | /* Read Register 13 (upper byte of baud rate generator constant) */ |
| 450 | |
| 451 | /* Read Register 15 (value of WR 15) */ |
| 452 | |
| 453 | /* Misc macros */ |
| 454 | #define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES)) |
| 455 | #define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \ |
| 456 | garbage = read_zsdata(channel); \ |
| 457 | garbage = read_zsdata(channel); \ |
| 458 | garbage = read_zsdata(channel); \ |
| 459 | } while(0) |
| 460 | |
| 461 | #endif /* !(_MACSERIAL_H) */ |