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Jon Loeligerd93daf82007-03-20 11:19:10 -05001/*
2 * MPC8544 DS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/ {
13 model = "MPC8544DS";
14 compatible = "MPC8544DS", "MPC85xxDS";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #cpus = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 PowerPC,8544@0 {
24 device_type = "cpu";
25 reg = <0>;
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>;
31 bus-frequency = <0>;
32 clock-frequency = <0>;
33 32-bit;
34 };
35 };
36
37 memory {
38 device_type = "memory";
39 reg = <00000000 00000000>; // Filled by U-Boot
40 };
41
42 soc8544@e0000000 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc";
47 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00100000>; // CCSRBAR 1M
49 bus-frequency = <0>; // Filled out by uboot.
50
Kumar Gala4da421d2007-05-15 13:20:05 -050051 memory-controller@2000 {
52 compatible = "fsl,8544-memory-controller";
53 reg = <2000 1000>;
54 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050055 interrupts = <12 2>;
Kumar Gala4da421d2007-05-15 13:20:05 -050056 };
57
58 l2-cache-controller@20000 {
59 compatible = "fsl,8544-l2-cache-controller";
60 reg = <20000 1000>;
61 cache-line-size = <20>; // 32 bytes
62 cache-size = <40000>; // L2, 256K
63 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050064 interrupts = <10 2>;
Kumar Gala4da421d2007-05-15 13:20:05 -050065 };
66
Jon Loeligerd93daf82007-03-20 11:19:10 -050067 i2c@3000 {
68 device_type = "i2c";
69 compatible = "fsl-i2c";
70 reg = <3000 100>;
Kumar Galab533f8a2007-07-03 02:35:35 -050071 interrupts = <2b 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -050072 interrupt-parent = <&mpic>;
73 dfsrr;
74 };
75
76 mdio@24520 {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 device_type = "mdio";
80 compatible = "gianfar";
81 reg = <24520 20>;
82 phy0: ethernet-phy@0 {
83 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050084 interrupts = <a 1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -050085 reg = <0>;
86 device_type = "ethernet-phy";
87 };
88 phy1: ethernet-phy@1 {
89 interrupt-parent = <&mpic>;
Kumar Galab533f8a2007-07-03 02:35:35 -050090 interrupts = <a 1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -050091 reg = <1>;
92 device_type = "ethernet-phy";
93 };
94 };
95
96 ethernet@24000 {
97 #address-cells = <1>;
98 #size-cells = <0>;
99 device_type = "network";
100 model = "TSEC";
101 compatible = "gianfar";
102 reg = <24000 1000>;
103 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Galab533f8a2007-07-03 02:35:35 -0500104 interrupts = <1d 2 1e 2 22 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500105 interrupt-parent = <&mpic>;
106 phy-handle = <&phy0>;
Kumar Gala9a9bcf42007-07-26 00:07:36 -0500107 phy-connection-type = "rgmii-id";
Jon Loeligerd93daf82007-03-20 11:19:10 -0500108 };
109
110 ethernet@26000 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 device_type = "network";
114 model = "TSEC";
115 compatible = "gianfar";
116 reg = <26000 1000>;
117 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Galab533f8a2007-07-03 02:35:35 -0500118 interrupts = <1f 2 20 2 21 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500119 interrupt-parent = <&mpic>;
120 phy-handle = <&phy1>;
Kumar Gala9a9bcf42007-07-26 00:07:36 -0500121 phy-connection-type = "rgmii-id";
Jon Loeligerd93daf82007-03-20 11:19:10 -0500122 };
123
124 serial@4500 {
125 device_type = "serial";
126 compatible = "ns16550";
127 reg = <4500 100>;
128 clock-frequency = <0>;
Kumar Galab533f8a2007-07-03 02:35:35 -0500129 interrupts = <2a 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500130 interrupt-parent = <&mpic>;
131 };
132
133 serial@4600 {
134 device_type = "serial";
135 compatible = "ns16550";
136 reg = <4600 100>;
137 clock-frequency = <0>;
Kumar Galab533f8a2007-07-03 02:35:35 -0500138 interrupts = <2a 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500139 interrupt-parent = <&mpic>;
140 };
141
Roy Zangf16dab92007-07-13 18:05:08 +0800142 pci@8000 {
143 compatible = "fsl,mpc8540-pci";
144 device_type = "pci";
145 interrupt-map-mask = <f800 0 0 7>;
146 interrupt-map = <
147
148 /* IDSEL 0x11 J17 Slot 1 */
149 8800 0 0 1 &mpic 2 1
150 8800 0 0 2 &mpic 3 1
151 8800 0 0 3 &mpic 4 1
152 8800 0 0 4 &mpic 1 1
153
154 /* IDSEL 0x12 J16 Slot 2 */
155
156 9000 0 0 1 &mpic 3 1
157 9000 0 0 2 &mpic 4 1
158 9000 0 0 3 &mpic 2 1
159 9000 0 0 4 &mpic 1 1>;
160
161 interrupt-parent = <&mpic>;
162 interrupts = <18 2>;
163 bus-range = <0 ff>;
164 ranges = <02000000 0 80000000 80000000 0 10000000
165 01000000 0 00000000 e2000000 0 00800000>;
166 clock-frequency = <3f940aa>;
167 #interrupt-cells = <1>;
168 #size-cells = <2>;
169 #address-cells = <3>;
170 reg = <8000 1000>;
171 };
172
173 pcie@9000 {
174 compatible = "fsl,mpc8548-pcie";
175 device_type = "pci";
176 #interrupt-cells = <1>;
177 #size-cells = <2>;
178 #address-cells = <3>;
179 reg = <9000 1000>;
180 bus-range = <0 ff>;
181 ranges = <02000000 0 90000000 90000000 0 10000000
182 01000000 0 00000000 e3000000 0 00800000>;
183 clock-frequency = <1fca055>;
184 interrupt-parent = <&mpic>;
185 interrupts = <1a 2>;
186 interrupt-map-mask = <f800 0 0 7>;
187 interrupt-map = <
188 /* IDSEL 0x0 */
189 0000 0 0 1 &mpic 4 1
190 0000 0 0 2 &mpic 5 1
191 0000 0 0 3 &mpic 6 1
192 0000 0 0 4 &mpic 7 1
193 >;
194 };
195
196 pcie@a000 {
197 compatible = "fsl,mpc8548-pcie";
198 device_type = "pci";
199 #interrupt-cells = <1>;
200 #size-cells = <2>;
201 #address-cells = <3>;
202 reg = <a000 1000>;
203 bus-range = <0 ff>;
204 ranges = <02000000 0 a0000000 a0000000 0 10000000
205 01000000 0 00000000 e2800000 0 00800000>;
206 clock-frequency = <1fca055>;
207 interrupt-parent = <&mpic>;
208 interrupts = <19 2>;
209 interrupt-map-mask = <f800 0 0 7>;
210 interrupt-map = <
211 /* IDSEL 0x0 */
212 0000 0 0 1 &mpic 0 1
213 0000 0 0 2 &mpic 1 1
214 0000 0 0 3 &mpic 2 1
215 0000 0 0 4 &mpic 3 1
216 >;
217 };
218
219 pcie@b000 {
220 compatible = "fsl,mpc8548-pcie";
221 device_type = "pci";
222 #interrupt-cells = <1>;
223 #size-cells = <2>;
224 #address-cells = <3>;
225 reg = <b000 1000>;
226 bus-range = <0 ff>;
227 ranges = <02000000 0 b0000000 b0000000 0 10000000
228 01000000 0 00000000 e3800000 0 00800000>;
229 clock-frequency = <1fca055>;
230 interrupt-parent = <&mpic>;
231 interrupts = <1b 2>;
232 interrupt-map-mask = <f800 0 0 7>;
233 interrupt-map = <
234
235 // IDSEL 0x1a
236 d000 0 0 1 &i8259 6 2
237 d000 0 0 2 &i8259 3 2
238 d000 0 0 3 &i8259 4 2
239 d000 0 0 4 &i8259 5 2
240
241 // IDSEL 0x1b
242 d800 0 0 1 &i8259 5 2
243 d800 0 0 2 &i8259 0 0
244 d800 0 0 3 &i8259 0 0
245 d800 0 0 4 &i8259 0 0
246
247 // IDSEL 0x1c USB
248 e000 0 0 1 &i8259 9 2
249 e000 0 0 2 &i8259 a 2
250 e000 0 0 3 &i8259 c 2
251 e000 0 0 4 &i8259 7 2
252
253 // IDSEL 0x1d Audio
254 e800 0 0 1 &i8259 9 2
255 e800 0 0 2 &i8259 a 2
256 e800 0 0 3 &i8259 b 2
257 e800 0 0 4 &i8259 0 0
258
259 // IDSEL 0x1e Legacy
260 f000 0 0 1 &i8259 c 2
261 f000 0 0 2 &i8259 0 0
262 f000 0 0 3 &i8259 0 0
263 f000 0 0 4 &i8259 0 0
264
265 // IDSEL 0x1f IDE/SATA
266 f800 0 0 1 &i8259 6 2
267 f800 0 0 2 &i8259 0 0
268 f800 0 0 3 &i8259 0 0
269 f800 0 0 4 &i8259 0 0
270 >;
271 uli1575@0 {
272 reg = <0 0 0 0 0>;
273 #size-cells = <2>;
274 #address-cells = <3>;
275 ranges = <02000000 0 b0000000
276 02000000 0 b0000000
277 0 10000000
278 01000000 0 00000000
279 01000000 0 00000000
280 0 00080000>;
281
282 pci_bridge@0 {
283 reg = <0 0 0 0 0>;
284 #size-cells = <2>;
285 #address-cells = <3>;
286 ranges = <02000000 0 b0000000
287 02000000 0 b0000000
288 0 20000000
289 01000000 0 00000000
290 01000000 0 00000000
291 0 00100000>;
292
293 isa@1e {
294 device_type = "isa";
295 #interrupt-cells = <2>;
296 #size-cells = <1>;
297 #address-cells = <2>;
298 reg = <f000 0 0 0 0>;
299 ranges = <1 0 01000000 0 0
300 00001000>;
301 interrupt-parent = <&i8259>;
302
303 i8259: interrupt-controller@20 {
304 reg = <1 20 2
305 1 a0 2
306 1 4d0 2>;
307 clock-frequency = <0>;
308 interrupt-controller;
309 device_type = "interrupt-controller";
310 #address-cells = <0>;
311 #interrupt-cells = <2>;
312 built-in;
313 compatible = "chrp,iic";
314 interrupts = <9 2>;
315 interrupt-parent =
316 <&mpic>;
317 };
318
319 i8042@60 {
320 #size-cells = <0>;
321 #address-cells = <1>;
322 reg = <1 60 1 1 64 1>;
323 interrupts = <1 3 c 3>;
324 interrupt-parent =
325 <&i8259>;
326
327 keyboard@0 {
328 reg = <0>;
329 compatible = "pnpPNP,303";
330 };
331
332 mouse@1 {
333 reg = <1>;
334 compatible = "pnpPNP,f03";
335 };
336 };
337
338 rtc@70 {
339 compatible =
340 "pnpPNP,b00";
341 reg = <1 70 2>;
342 };
343
344 gpio@400 {
345 reg = <1 400 80>;
346 };
347 };
348 };
349 };
350
351 };
352
Roy Zang10ce8c62007-07-13 17:35:33 +0800353 global-utilities@e0000 { //global utilities block
354 compatible = "fsl,mpc8548-guts";
355 reg = <e0000 1000>;
356 fsl,has-rstcr;
357 };
358
Jon Loeligerd93daf82007-03-20 11:19:10 -0500359 mpic: pic@40000 {
360 clock-frequency = <0>;
361 interrupt-controller;
362 #address-cells = <0>;
363 #interrupt-cells = <2>;
364 reg = <40000 40000>;
365 built-in;
366 compatible = "chrp,open-pic";
367 device_type = "open-pic";
368 big-endian;
369 };
370 };
371};