blob: d87a85cefb665fcc7f9af174d3d02a0c3d922232 [file] [log] [blame]
Shawn Guo179a5022012-10-04 17:13:49 -07001/*
2 * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/rtc.h>
Sanchayan Maity7f899392014-12-10 15:54:17 -080020#include <linux/clk.h>
Shawn Guo179a5022012-10-04 17:13:49 -070021
22/* These register offsets are relative to LP (Low Power) range */
23#define SNVS_LPCR 0x04
24#define SNVS_LPSR 0x18
25#define SNVS_LPSRTCMR 0x1c
26#define SNVS_LPSRTCLR 0x20
27#define SNVS_LPTAR 0x24
28#define SNVS_LPPGDR 0x30
29
30#define SNVS_LPCR_SRTC_ENV (1 << 0)
31#define SNVS_LPCR_LPTA_EN (1 << 1)
32#define SNVS_LPCR_LPWUI_EN (1 << 3)
33#define SNVS_LPSR_LPTA (1 << 0)
34
35#define SNVS_LPPGDR_INIT 0x41736166
36#define CNTR_TO_SECS_SH 15
37
38struct snvs_rtc_data {
39 struct rtc_device *rtc;
40 void __iomem *ioaddr;
41 int irq;
42 spinlock_t lock;
Sanchayan Maity7f899392014-12-10 15:54:17 -080043 struct clk *clk;
Shawn Guo179a5022012-10-04 17:13:49 -070044};
45
46static u32 rtc_read_lp_counter(void __iomem *ioaddr)
47{
48 u64 read1, read2;
49
50 do {
51 read1 = readl(ioaddr + SNVS_LPSRTCMR);
52 read1 <<= 32;
53 read1 |= readl(ioaddr + SNVS_LPSRTCLR);
54
55 read2 = readl(ioaddr + SNVS_LPSRTCMR);
56 read2 <<= 32;
57 read2 |= readl(ioaddr + SNVS_LPSRTCLR);
58 } while (read1 != read2);
59
60 /* Convert 47-bit counter to 32-bit raw second count */
61 return (u32) (read1 >> CNTR_TO_SECS_SH);
62}
63
64static void rtc_write_sync_lp(void __iomem *ioaddr)
65{
66 u32 count1, count2, count3;
67 int i;
68
69 /* Wait for 3 CKIL cycles */
70 for (i = 0; i < 3; i++) {
71 do {
72 count1 = readl(ioaddr + SNVS_LPSRTCLR);
73 count2 = readl(ioaddr + SNVS_LPSRTCLR);
74 } while (count1 != count2);
75
76 /* Now wait until counter value changes */
77 do {
78 do {
79 count2 = readl(ioaddr + SNVS_LPSRTCLR);
80 count3 = readl(ioaddr + SNVS_LPSRTCLR);
81 } while (count2 != count3);
82 } while (count3 == count1);
83 }
84}
85
86static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
87{
88 unsigned long flags;
89 int timeout = 1000;
90 u32 lpcr;
91
92 spin_lock_irqsave(&data->lock, flags);
93
94 lpcr = readl(data->ioaddr + SNVS_LPCR);
95 if (enable)
96 lpcr |= SNVS_LPCR_SRTC_ENV;
97 else
98 lpcr &= ~SNVS_LPCR_SRTC_ENV;
99 writel(lpcr, data->ioaddr + SNVS_LPCR);
100
101 spin_unlock_irqrestore(&data->lock, flags);
102
103 while (--timeout) {
104 lpcr = readl(data->ioaddr + SNVS_LPCR);
105
106 if (enable) {
107 if (lpcr & SNVS_LPCR_SRTC_ENV)
108 break;
109 } else {
110 if (!(lpcr & SNVS_LPCR_SRTC_ENV))
111 break;
112 }
113 }
114
115 if (!timeout)
116 return -ETIMEDOUT;
117
118 return 0;
119}
120
121static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
122{
123 struct snvs_rtc_data *data = dev_get_drvdata(dev);
124 unsigned long time = rtc_read_lp_counter(data->ioaddr);
125
126 rtc_time_to_tm(time, tm);
127
128 return 0;
129}
130
131static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
132{
133 struct snvs_rtc_data *data = dev_get_drvdata(dev);
134 unsigned long time;
135
136 rtc_tm_to_time(tm, &time);
137
138 /* Disable RTC first */
139 snvs_rtc_enable(data, false);
140
141 /* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
142 writel(time << CNTR_TO_SECS_SH, data->ioaddr + SNVS_LPSRTCLR);
143 writel(time >> (32 - CNTR_TO_SECS_SH), data->ioaddr + SNVS_LPSRTCMR);
144
145 /* Enable RTC again */
146 snvs_rtc_enable(data, true);
147
148 return 0;
149}
150
151static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
152{
153 struct snvs_rtc_data *data = dev_get_drvdata(dev);
154 u32 lptar, lpsr;
155
156 lptar = readl(data->ioaddr + SNVS_LPTAR);
157 rtc_time_to_tm(lptar, &alrm->time);
158
159 lpsr = readl(data->ioaddr + SNVS_LPSR);
160 alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
161
162 return 0;
163}
164
165static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
166{
167 struct snvs_rtc_data *data = dev_get_drvdata(dev);
168 u32 lpcr;
169 unsigned long flags;
170
171 spin_lock_irqsave(&data->lock, flags);
172
173 lpcr = readl(data->ioaddr + SNVS_LPCR);
174 if (enable)
175 lpcr |= (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
176 else
177 lpcr &= ~(SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN);
178 writel(lpcr, data->ioaddr + SNVS_LPCR);
179
180 spin_unlock_irqrestore(&data->lock, flags);
181
182 rtc_write_sync_lp(data->ioaddr);
183
184 return 0;
185}
186
187static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
188{
189 struct snvs_rtc_data *data = dev_get_drvdata(dev);
190 struct rtc_time *alrm_tm = &alrm->time;
191 unsigned long time;
192 unsigned long flags;
193 u32 lpcr;
194
195 rtc_tm_to_time(alrm_tm, &time);
196
197 spin_lock_irqsave(&data->lock, flags);
198
199 /* Have to clear LPTA_EN before programming new alarm time in LPTAR */
200 lpcr = readl(data->ioaddr + SNVS_LPCR);
201 lpcr &= ~SNVS_LPCR_LPTA_EN;
202 writel(lpcr, data->ioaddr + SNVS_LPCR);
203
204 spin_unlock_irqrestore(&data->lock, flags);
205
206 writel(time, data->ioaddr + SNVS_LPTAR);
207
208 /* Clear alarm interrupt status bit */
209 writel(SNVS_LPSR_LPTA, data->ioaddr + SNVS_LPSR);
210
211 return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
212}
213
214static const struct rtc_class_ops snvs_rtc_ops = {
215 .read_time = snvs_rtc_read_time,
216 .set_time = snvs_rtc_set_time,
217 .read_alarm = snvs_rtc_read_alarm,
218 .set_alarm = snvs_rtc_set_alarm,
219 .alarm_irq_enable = snvs_rtc_alarm_irq_enable,
220};
221
222static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
223{
224 struct device *dev = dev_id;
225 struct snvs_rtc_data *data = dev_get_drvdata(dev);
226 u32 lpsr;
227 u32 events = 0;
228
229 lpsr = readl(data->ioaddr + SNVS_LPSR);
230
231 if (lpsr & SNVS_LPSR_LPTA) {
232 events |= (RTC_AF | RTC_IRQF);
233
234 /* RTC alarm should be one-shot */
235 snvs_rtc_alarm_irq_enable(dev, 0);
236
237 rtc_update_irq(data->rtc, 1, events);
238 }
239
240 /* clear interrupt status */
241 writel(lpsr, data->ioaddr + SNVS_LPSR);
242
243 return events ? IRQ_HANDLED : IRQ_NONE;
244}
245
Greg Kroah-Hartman5a167f42012-12-21 13:09:38 -0800246static int snvs_rtc_probe(struct platform_device *pdev)
Shawn Guo179a5022012-10-04 17:13:49 -0700247{
248 struct snvs_rtc_data *data;
249 struct resource *res;
250 int ret;
251
252 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
253 if (!data)
254 return -ENOMEM;
255
256 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding8cbce1e2013-01-21 11:09:17 +0100257 data->ioaddr = devm_ioremap_resource(&pdev->dev, res);
258 if (IS_ERR(data->ioaddr))
259 return PTR_ERR(data->ioaddr);
Shawn Guo179a5022012-10-04 17:13:49 -0700260
261 data->irq = platform_get_irq(pdev, 0);
262 if (data->irq < 0)
263 return data->irq;
264
Sanchayan Maity7f899392014-12-10 15:54:17 -0800265 data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
266 if (IS_ERR(data->clk)) {
267 data->clk = NULL;
268 } else {
269 ret = clk_prepare_enable(data->clk);
270 if (ret) {
271 dev_err(&pdev->dev,
272 "Could not prepare or enable the snvs clock\n");
273 return ret;
274 }
275 }
276
Shawn Guo179a5022012-10-04 17:13:49 -0700277 platform_set_drvdata(pdev, data);
278
279 spin_lock_init(&data->lock);
280
281 /* Initialize glitch detect */
282 writel(SNVS_LPPGDR_INIT, data->ioaddr + SNVS_LPPGDR);
283
284 /* Clear interrupt status */
285 writel(0xffffffff, data->ioaddr + SNVS_LPSR);
286
287 /* Enable RTC */
288 snvs_rtc_enable(data, true);
289
290 device_init_wakeup(&pdev->dev, true);
291
292 ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
293 IRQF_SHARED, "rtc alarm", &pdev->dev);
294 if (ret) {
295 dev_err(&pdev->dev, "failed to request irq %d: %d\n",
296 data->irq, ret);
Sanchayan Maity7f899392014-12-10 15:54:17 -0800297 goto error_rtc_device_register;
Shawn Guo179a5022012-10-04 17:13:49 -0700298 }
299
Jingoo Han904784c2013-04-29 16:19:12 -0700300 data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
Shawn Guo179a5022012-10-04 17:13:49 -0700301 &snvs_rtc_ops, THIS_MODULE);
302 if (IS_ERR(data->rtc)) {
303 ret = PTR_ERR(data->rtc);
304 dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
Sanchayan Maity7f899392014-12-10 15:54:17 -0800305 goto error_rtc_device_register;
Shawn Guo179a5022012-10-04 17:13:49 -0700306 }
307
308 return 0;
Sanchayan Maity7f899392014-12-10 15:54:17 -0800309
310error_rtc_device_register:
311 if (data->clk)
312 clk_disable_unprepare(data->clk);
313
314 return ret;
Shawn Guo179a5022012-10-04 17:13:49 -0700315}
316
Shawn Guo179a5022012-10-04 17:13:49 -0700317#ifdef CONFIG_PM_SLEEP
318static int snvs_rtc_suspend(struct device *dev)
319{
320 struct snvs_rtc_data *data = dev_get_drvdata(dev);
321
322 if (device_may_wakeup(dev))
323 enable_irq_wake(data->irq);
324
Stefan Agner119434f2015-05-21 17:29:35 +0200325 return 0;
326}
327
328static int snvs_rtc_suspend_noirq(struct device *dev)
329{
330 struct snvs_rtc_data *data = dev_get_drvdata(dev);
331
Sanchayan Maity7f899392014-12-10 15:54:17 -0800332 if (data->clk)
333 clk_disable_unprepare(data->clk);
334
Shawn Guo179a5022012-10-04 17:13:49 -0700335 return 0;
336}
337
338static int snvs_rtc_resume(struct device *dev)
339{
340 struct snvs_rtc_data *data = dev_get_drvdata(dev);
341
342 if (device_may_wakeup(dev))
Stefan Agner119434f2015-05-21 17:29:35 +0200343 return disable_irq_wake(data->irq);
Shawn Guo179a5022012-10-04 17:13:49 -0700344
Stefan Agner119434f2015-05-21 17:29:35 +0200345 return 0;
346}
347
348static int snvs_rtc_resume_noirq(struct device *dev)
349{
350 struct snvs_rtc_data *data = dev_get_drvdata(dev);
351
352 if (data->clk)
353 return clk_prepare_enable(data->clk);
Sanchayan Maity7f899392014-12-10 15:54:17 -0800354
Shawn Guo179a5022012-10-04 17:13:49 -0700355 return 0;
356}
Shawn Guo179a5022012-10-04 17:13:49 -0700357
Sanchayan Maity7654e9d2014-12-10 15:54:20 -0800358static const struct dev_pm_ops snvs_rtc_pm_ops = {
Stefan Agner119434f2015-05-21 17:29:35 +0200359 .suspend = snvs_rtc_suspend,
360 .suspend_noirq = snvs_rtc_suspend_noirq,
361 .resume = snvs_rtc_resume,
362 .resume_noirq = snvs_rtc_resume_noirq,
Sanchayan Maity7654e9d2014-12-10 15:54:20 -0800363};
Shawn Guo179a5022012-10-04 17:13:49 -0700364
Guenter Roeck88221c32014-12-12 16:54:12 -0800365#define SNVS_RTC_PM_OPS (&snvs_rtc_pm_ops)
366
367#else
368
369#define SNVS_RTC_PM_OPS NULL
370
371#endif
372
Greg Kroah-Hartman5a167f42012-12-21 13:09:38 -0800373static const struct of_device_id snvs_dt_ids[] = {
Shawn Guo179a5022012-10-04 17:13:49 -0700374 { .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
375 { /* sentinel */ }
376};
377MODULE_DEVICE_TABLE(of, snvs_dt_ids);
378
379static struct platform_driver snvs_rtc_driver = {
380 .driver = {
381 .name = "snvs_rtc",
Guenter Roeck88221c32014-12-12 16:54:12 -0800382 .pm = SNVS_RTC_PM_OPS,
Sachin Kamatc39b3712013-11-12 15:10:57 -0800383 .of_match_table = snvs_dt_ids,
Shawn Guo179a5022012-10-04 17:13:49 -0700384 },
385 .probe = snvs_rtc_probe,
Shawn Guo179a5022012-10-04 17:13:49 -0700386};
387module_platform_driver(snvs_rtc_driver);
388
389MODULE_AUTHOR("Freescale Semiconductor, Inc.");
390MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
391MODULE_LICENSE("GPL");