Ramkumar Ramachandra | a3ea015 | 2014-01-05 15:51:14 +0530 | [diff] [blame] | 1 | Intel P-state driver |
| 2 | -------------------- |
| 3 | |
Dirk Brandewie | 2f86dc4 | 2014-11-06 09:40:47 -0800 | [diff] [blame] | 4 | This driver provides an interface to control the P state selection for |
| 5 | SandyBridge+ Intel processors. The driver can operate two different |
Prarit Bhargava | 1df1b36 | 2015-06-01 09:36:04 -0400 | [diff] [blame] | 6 | modes based on the processor model, legacy mode and Hardware P state (HWP) |
Dirk Brandewie | 2f86dc4 | 2014-11-06 09:40:47 -0800 | [diff] [blame] | 7 | mode. |
Ramkumar Ramachandra | a3ea015 | 2014-01-05 15:51:14 +0530 | [diff] [blame] | 8 | |
Prarit Bhargava | 1df1b36 | 2015-06-01 09:36:04 -0400 | [diff] [blame] | 9 | In legacy mode, the Intel P-state implements two internal governors, |
| 10 | performance and powersave, that differ from the general cpufreq governors of |
| 11 | the same name (the general cpufreq governors implement target(), whereas the |
| 12 | internal Intel P-state governors implement setpolicy()). The internal |
| 13 | performance governor sets the max_perf_pct and min_perf_pct to 100; that is, |
| 14 | the governor selects the highest available P state to maximize the performance |
| 15 | of the core. The internal powersave governor selects the appropriate P state |
| 16 | based on the current load on the CPU. |
Ramkumar Ramachandra | a3ea015 | 2014-01-05 15:51:14 +0530 | [diff] [blame] | 17 | |
Dirk Brandewie | 2f86dc4 | 2014-11-06 09:40:47 -0800 | [diff] [blame] | 18 | In HWP mode P state selection is implemented in the processor |
| 19 | itself. The driver provides the interfaces between the cpufreq core and |
| 20 | the processor to control P state selection based on user preferences |
| 21 | and reporting frequency to the cpufreq core. In this mode the |
Prarit Bhargava | 1df1b36 | 2015-06-01 09:36:04 -0400 | [diff] [blame] | 22 | internal Intel P-state governor code is disabled. |
Dirk Brandewie | 2f86dc4 | 2014-11-06 09:40:47 -0800 | [diff] [blame] | 23 | |
Prarit Bhargava | 1df1b36 | 2015-06-01 09:36:04 -0400 | [diff] [blame] | 24 | In addition to the interfaces provided by the cpufreq core for |
Dirk Brandewie | 2f86dc4 | 2014-11-06 09:40:47 -0800 | [diff] [blame] | 25 | controlling frequency the driver provides sysfs files for |
| 26 | controlling P state selection. These files have been added to |
Ramkumar Ramachandra | a3ea015 | 2014-01-05 15:51:14 +0530 | [diff] [blame] | 27 | /sys/devices/system/cpu/intel_pstate/ |
| 28 | |
| 29 | max_perf_pct: limits the maximum P state that will be requested by |
Dirk Brandewie | 41629a8 | 2014-06-20 07:28:00 -0700 | [diff] [blame] | 30 | the driver stated as a percentage of the available performance. The |
| 31 | available (P states) performance may be reduced by the no_turbo |
| 32 | setting described below. |
Ramkumar Ramachandra | a3ea015 | 2014-01-05 15:51:14 +0530 | [diff] [blame] | 33 | |
| 34 | min_perf_pct: limits the minimum P state that will be requested by |
Dirk Brandewie | 41629a8 | 2014-06-20 07:28:00 -0700 | [diff] [blame] | 35 | the driver stated as a percentage of the max (non-turbo) |
| 36 | performance level. |
Ramkumar Ramachandra | a3ea015 | 2014-01-05 15:51:14 +0530 | [diff] [blame] | 37 | |
| 38 | no_turbo: limits the driver to selecting P states below the turbo |
| 39 | frequency range. |
| 40 | |
Kristen Carlson Accardi | d01b1f4 | 2015-01-28 15:03:27 -0800 | [diff] [blame] | 41 | turbo_pct: displays the percentage of the total performance that |
| 42 | is supported by hardware that is in the turbo range. This number |
| 43 | is independent of whether turbo has been disabled or not. |
| 44 | |
Kristen Carlson Accardi | 0522424 | 2015-01-28 15:03:28 -0800 | [diff] [blame] | 45 | num_pstates: displays the number of pstates that are supported |
| 46 | by hardware. This number is independent of whether turbo has |
| 47 | been disabled or not. |
| 48 | |
Ramkumar Ramachandra | a3ea015 | 2014-01-05 15:51:14 +0530 | [diff] [blame] | 49 | For contemporary Intel processors, the frequency is controlled by the |
| 50 | processor itself and the P-states exposed to software are related to |
| 51 | performance levels. The idea that frequency can be set to a single |
| 52 | frequency is fiction for Intel Core processors. Even if the scaling |
| 53 | driver selects a single P state the actual frequency the processor |
| 54 | will run at is selected by the processor itself. |
| 55 | |
Dirk Brandewie | 2f86dc4 | 2014-11-06 09:40:47 -0800 | [diff] [blame] | 56 | For legacy mode debugfs files have also been added to allow tuning of |
| 57 | the internal governor algorythm. These files are located at |
| 58 | /sys/kernel/debug/pstate_snb/ These files are NOT present in HWP mode. |
Ramkumar Ramachandra | a3ea015 | 2014-01-05 15:51:14 +0530 | [diff] [blame] | 59 | |
| 60 | deadband |
| 61 | d_gain_pct |
| 62 | i_gain_pct |
| 63 | p_gain_pct |
| 64 | sample_rate_ms |
| 65 | setpoint |