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gerrit-public.fairphone.software / kernel / msm-4.19 / 11ff376fcfc0135b8947d27ab80162c218d1af90 / . / drivers / clk / rockchip / clk-rk3188.c
blob: 1c5e6442dcfba66d712ae2aa15310e7e7b07c6a6 [file] [log] [blame]
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <dt-bindings/clock/rk3188-cru-common.h>
20#include "clk.h"
21
Heiko Stuebner11ff3762014-09-01 23:52:40 +0200[diff] [blame^]22#define RK3066_GRF_SOC_STATUS 0x15c
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]23#define RK3188_GRF_SOC_STATUS 0xac
24
25enum rk3188_plls {
26 apll, cpll, dpll, gpll,
27};
28
29struct rockchip_pll_rate_table rk3188_pll_rates[] = {
30 RK3066_PLL_RATE(2208000000, 1, 92, 1),
31 RK3066_PLL_RATE(2184000000, 1, 91, 1),
32 RK3066_PLL_RATE(2160000000, 1, 90, 1),
33 RK3066_PLL_RATE(2136000000, 1, 89, 1),
34 RK3066_PLL_RATE(2112000000, 1, 88, 1),
35 RK3066_PLL_RATE(2088000000, 1, 87, 1),
36 RK3066_PLL_RATE(2064000000, 1, 86, 1),
37 RK3066_PLL_RATE(2040000000, 1, 85, 1),
38 RK3066_PLL_RATE(2016000000, 1, 84, 1),
39 RK3066_PLL_RATE(1992000000, 1, 83, 1),
40 RK3066_PLL_RATE(1968000000, 1, 82, 1),
41 RK3066_PLL_RATE(1944000000, 1, 81, 1),
42 RK3066_PLL_RATE(1920000000, 1, 80, 1),
43 RK3066_PLL_RATE(1896000000, 1, 79, 1),
44 RK3066_PLL_RATE(1872000000, 1, 78, 1),
45 RK3066_PLL_RATE(1848000000, 1, 77, 1),
46 RK3066_PLL_RATE(1824000000, 1, 76, 1),
47 RK3066_PLL_RATE(1800000000, 1, 75, 1),
48 RK3066_PLL_RATE(1776000000, 1, 74, 1),
49 RK3066_PLL_RATE(1752000000, 1, 73, 1),
50 RK3066_PLL_RATE(1728000000, 1, 72, 1),
51 RK3066_PLL_RATE(1704000000, 1, 71, 1),
52 RK3066_PLL_RATE(1680000000, 1, 70, 1),
53 RK3066_PLL_RATE(1656000000, 1, 69, 1),
54 RK3066_PLL_RATE(1632000000, 1, 68, 1),
55 RK3066_PLL_RATE(1608000000, 1, 67, 1),
56 RK3066_PLL_RATE(1560000000, 1, 65, 1),
57 RK3066_PLL_RATE(1512000000, 1, 63, 1),
58 RK3066_PLL_RATE(1488000000, 1, 62, 1),
59 RK3066_PLL_RATE(1464000000, 1, 61, 1),
60 RK3066_PLL_RATE(1440000000, 1, 60, 1),
61 RK3066_PLL_RATE(1416000000, 1, 59, 1),
62 RK3066_PLL_RATE(1392000000, 1, 58, 1),
63 RK3066_PLL_RATE(1368000000, 1, 57, 1),
64 RK3066_PLL_RATE(1344000000, 1, 56, 1),
65 RK3066_PLL_RATE(1320000000, 1, 55, 1),
66 RK3066_PLL_RATE(1296000000, 1, 54, 1),
67 RK3066_PLL_RATE(1272000000, 1, 53, 1),
68 RK3066_PLL_RATE(1248000000, 1, 52, 1),
69 RK3066_PLL_RATE(1224000000, 1, 51, 1),
70 RK3066_PLL_RATE(1200000000, 1, 50, 1),
71 RK3066_PLL_RATE(1188000000, 2, 99, 1),
72 RK3066_PLL_RATE(1176000000, 1, 49, 1),
73 RK3066_PLL_RATE(1128000000, 1, 47, 1),
74 RK3066_PLL_RATE(1104000000, 1, 46, 1),
75 RK3066_PLL_RATE(1008000000, 1, 84, 2),
76 RK3066_PLL_RATE( 912000000, 1, 76, 2),
77 RK3066_PLL_RATE( 891000000, 8, 594, 2),
78 RK3066_PLL_RATE( 888000000, 1, 74, 2),
79 RK3066_PLL_RATE( 816000000, 1, 68, 2),
80 RK3066_PLL_RATE( 798000000, 2, 133, 2),
81 RK3066_PLL_RATE( 792000000, 1, 66, 2),
82 RK3066_PLL_RATE( 768000000, 1, 64, 2),
83 RK3066_PLL_RATE( 742500000, 8, 495, 2),
84 RK3066_PLL_RATE( 696000000, 1, 58, 2),
85 RK3066_PLL_RATE( 600000000, 1, 50, 2),
86 RK3066_PLL_RATE( 594000000, 2, 198, 4),
87 RK3066_PLL_RATE( 552000000, 1, 46, 2),
88 RK3066_PLL_RATE( 504000000, 1, 84, 4),
89 RK3066_PLL_RATE( 456000000, 1, 76, 4),
90 RK3066_PLL_RATE( 408000000, 1, 68, 4),
91 RK3066_PLL_RATE( 384000000, 2, 128, 4),
92 RK3066_PLL_RATE( 360000000, 1, 60, 4),
93 RK3066_PLL_RATE( 312000000, 1, 52, 4),
94 RK3066_PLL_RATE( 300000000, 1, 50, 4),
95 RK3066_PLL_RATE( 297000000, 2, 198, 8),
96 RK3066_PLL_RATE( 252000000, 1, 84, 8),
97 RK3066_PLL_RATE( 216000000, 1, 72, 8),
98 RK3066_PLL_RATE( 148500000, 2, 99, 8),
99 RK3066_PLL_RATE( 126000000, 1, 84, 16),
100 RK3066_PLL_RATE( 48000000, 1, 64, 32),
101 { /* sentinel */ },
102};
103
104PNAME(mux_pll_p) = { "xin24m", "xin32k" };
105PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
106PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" };
107PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" };
108PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
109PNAME(mux_aclk_cpu_p) = { "apll", "gpll" };
110PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" };
111PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" };
112PNAME(mux_sclk_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" };
113PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" };
114PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" };
115PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" };
116PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" };
117PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" };
118PNAME(mux_mac_p) = { "gpll", "dpll" };
119PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" };
120
121static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
122 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
123 RK2928_MODE_CON, 0, 6, rk3188_pll_rates),
124 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
125 RK2928_MODE_CON, 4, 5, NULL),
126 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
127 RK2928_MODE_CON, 8, 7, rk3188_pll_rates),
128 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
129 RK2928_MODE_CON, 12, 8, rk3188_pll_rates),
130};
131
132#define MFLAGS CLK_MUX_HIWORD_MASK
133#define DFLAGS CLK_DIVIDER_HIWORD_MASK
134#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
135
136/* 2 ^ (val + 1) */
137static struct clk_div_table div_core_peri_t[] = {
138 { .val = 0, .div = 2 },
139 { .val = 1, .div = 4 },
140 { .val = 2, .div = 8 },
141 { .val = 3, .div = 16 },
142 { /* sentinel */ },
143};
144
145static struct rockchip_clk_branch common_clk_branches[] __initdata = {
146 /*
147 * Clock-Architecture Diagram 2
148 */
149
150 GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
151
152 /* these two are set by the cpuclk and should not be changed */
153 COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0,
154 RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
155 div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
156
157 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
158 RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
159 RK2928_CLKGATE_CON(3), 9, GFLAGS),
160 GATE(0, "hclk_vepu", "aclk_vepu", 0,
161 RK2928_CLKGATE_CON(3), 10, GFLAGS),
162 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
163 RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
164 RK2928_CLKGATE_CON(3), 11, GFLAGS),
165 GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
166 RK2928_CLKGATE_CON(3), 12, GFLAGS),
167
168 GATE(0, "gpll_ddr", "gpll", 0,
169 RK2928_CLKGATE_CON(1), 7, GFLAGS),
170 COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0,
171 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
172 RK2928_CLKGATE_CON(0), 2, GFLAGS),
173
174 GATE(0, "aclk_cpu", "aclk_cpu_pre", 0,
175 RK2928_CLKGATE_CON(0), 3, GFLAGS),
176
177 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
178 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
179 GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
180 RK2928_CLKGATE_CON(0), 6, GFLAGS),
181 GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
182 RK2928_CLKGATE_CON(0), 5, GFLAGS),
183 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
184 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
185 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
186 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
187 RK2928_CLKGATE_CON(4), 9, GFLAGS),
188 GATE(0, "hclk_cpu", "hclk_cpu_pre", 0,
189 RK2928_CLKGATE_CON(0), 4, GFLAGS),
190
191 COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 0,
192 RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
193 RK2928_CLKGATE_CON(3), 0, GFLAGS),
194 COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
195 RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
196 RK2928_CLKGATE_CON(1), 4, GFLAGS),
197
198 GATE(0, "aclk_peri", "aclk_peri_pre", 0,
199 RK2928_CLKGATE_CON(2), 1, GFLAGS),
200 COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0,
201 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
202 RK2928_CLKGATE_CON(2), 2, GFLAGS),
203 COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0,
204 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
205 RK2928_CLKGATE_CON(2), 3, GFLAGS),
206
207 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
208 RK2928_CLKSEL_CON(29), 0, 1, MFLAGS),
209 COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0,
210 RK2928_CLKSEL_CON(29), 1, 5, DFLAGS,
211 RK2928_CLKGATE_CON(3), 7, GFLAGS),
212 MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
213 RK2928_CLKSEL_CON(29), 7, 1, MFLAGS),
214
215 GATE(0, "pclkin_cif0", "ext_cif0", 0,
216 RK2928_CLKGATE_CON(3), 3, GFLAGS),
217
218 /*
219 * the 480m are generated inside the usb block from these clocks,
220 * but they are also a source for the hsicphy clock.
221 */
222 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
223 RK2928_CLKGATE_CON(1), 5, GFLAGS),
224 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
225 RK2928_CLKGATE_CON(1), 6, GFLAGS),
226
227 COMPOSITE(0, "mac_src", mux_mac_p, 0,
228 RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS,
229 RK2928_CLKGATE_CON(2), 5, GFLAGS),
230 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
231 RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
232 GATE(0, "sclk_mac_lbtest", "sclk_macref",
233 RK2928_CLKGATE_CON(2), 12, 0, GFLAGS),
234
235 COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
236 RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
237 RK2928_CLKGATE_CON(2), 6, GFLAGS),
238 COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src",
239 RK2928_CLKSEL_CON(23), 0,
240 RK2928_CLKGATE_CON(2), 7, 0, GFLAGS),
241 MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0,
242 RK2928_CLKSEL_CON(22), 4, 2, MFLAGS),
243
244 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
245 RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
246 RK2928_CLKGATE_CON(2), 8, GFLAGS),
247
248 /*
249 * Clock-Architecture Diagram 4
250 */
251
252 GATE(SCLK_SMC, "sclk_smc", "hclk_peri",
253 RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),
254
255 COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
256 RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
257 RK2928_CLKGATE_CON(2), 9, GFLAGS),
258 COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0,
259 RK2928_CLKSEL_CON(25), 8, 7, DFLAGS,
260 RK2928_CLKGATE_CON(2), 10, GFLAGS),
261
262 COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0,
263 RK2928_CLKSEL_CON(11), 0, 6, DFLAGS,
264 RK2928_CLKGATE_CON(2), 11, GFLAGS),
265 COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0,
266 RK2928_CLKSEL_CON(12), 0, 6, DFLAGS,
267 RK2928_CLKGATE_CON(2), 13, GFLAGS),
268 COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0,
269 RK2928_CLKSEL_CON(12), 8, 6, DFLAGS,
270 RK2928_CLKGATE_CON(2), 14, GFLAGS),
271
272 MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
273 RK2928_CLKSEL_CON(12), 15, 1, MFLAGS),
274 COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
275 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
276 RK2928_CLKGATE_CON(1), 8, GFLAGS),
277 COMPOSITE_FRAC(0, "uart0_frac", "uart0_pre", 0,
278 RK2928_CLKSEL_CON(17), 0,
279 RK2928_CLKGATE_CON(1), 9, GFLAGS),
280 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
281 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
282 COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
283 RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
284 RK2928_CLKGATE_CON(1), 10, GFLAGS),
285 COMPOSITE_FRAC(0, "uart1_frac", "uart1_pre", 0,
286 RK2928_CLKSEL_CON(18), 0,
287 RK2928_CLKGATE_CON(1), 11, GFLAGS),
288 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
289 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
290 COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
291 RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
292 RK2928_CLKGATE_CON(1), 12, GFLAGS),
293 COMPOSITE_FRAC(0, "uart2_frac", "uart2_pre", 0,
294 RK2928_CLKSEL_CON(19), 0,
295 RK2928_CLKGATE_CON(1), 13, GFLAGS),
296 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
297 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
298 COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
299 RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
300 RK2928_CLKGATE_CON(1), 14, GFLAGS),
301 COMPOSITE_FRAC(0, "uart3_frac", "uart3_pre", 0,
302 RK2928_CLKSEL_CON(20), 0,
303 RK2928_CLKGATE_CON(1), 15, GFLAGS),
304 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
305 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS),
306
307 GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
308
309 GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
310 GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS),
311
312 /* clk_core_pre gates */
313 GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
314
315 /* aclk_cpu gates */
316 GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
317 GATE(0, "aclk_intmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 12, GFLAGS),
318 GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 10, GFLAGS),
319
320 /* hclk_cpu gates */
321 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
322 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
323 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
324 GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
325 /* hclk_ahb2apb is part of a clk branch */
326 GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
327 GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
328 GATE(HCLK_LCDC1, "hclk_lcdc1", "aclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
329 GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
330 GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
331 GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
332
333 /* hclk_peri gates */
334 GATE(0, "hclk_peri_axi_matrix", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 0, GFLAGS),
335 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 6, GFLAGS),
336 GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS),
337 GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
338 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
339 GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 5, GFLAGS),
340 GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS),
341 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
342 GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
343 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
344 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
345 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS),
346
347 /* aclk_lcdc0_pre gates */
348 GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS),
349 GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
350 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
351 GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS),
352
353 /* aclk_lcdc1_pre gates */
354 GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
355 GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS),
356 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
357
358 /* atclk_cpu gates */
359 GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS),
360 GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
361
362 /* pclk_cpu gates */
363 GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
364 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
365 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
366 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
367 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
368 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
369 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
370 GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
371 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS),
372 GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
373 GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
374 GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
375 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 4, GFLAGS),
376 GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 5, GFLAGS),
377
378 /* aclk_peri */
379 GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
380 GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
381 GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 4, GFLAGS),
382 GATE(0, "aclk_cpu_peri", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 2, GFLAGS),
383 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 3, GFLAGS),
384
385 /* pclk_peri gates */
386 GATE(0, "pclk_peri_axi_matrix", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 1, GFLAGS),
387 GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
388 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
389 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
390 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS),
391 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
392 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
393 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
394 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
395 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
396 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
397 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
398};
399
400PNAME(mux_rk3066_lcdc0_p) = { "dclk_lcdc0_src", "xin27m" };
401PNAME(mux_rk3066_lcdc1_p) = { "dclk_lcdc1_src", "xin27m" };
402PNAME(mux_sclk_cif1_p) = { "cif1_pre", "xin24m" };
403PNAME(mux_sclk_i2s1_p) = { "i2s1_pre", "i2s1_frac", "xin12m" };
404PNAME(mux_sclk_i2s2_p) = { "i2s2_pre", "i2s2_frac", "xin12m" };
405
406static struct clk_div_table div_aclk_cpu_t[] = {
407 { .val = 0, .div = 1 },
408 { .val = 1, .div = 2 },
409 { .val = 2, .div = 3 },
410 { .val = 3, .div = 4 },
411 { .val = 4, .div = 8 },
412 { /* sentinel */ },
413};
414
415static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
416 COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0,
417 RK2928_CLKSEL_CON(0), 8, 1, MFLAGS, 0, 5, DFLAGS),
418 DIVTBL(0, "aclk_cpu_pre", "armclk", 0,
419 RK2928_CLKSEL_CON(1), 0, 3, DFLAGS, div_aclk_cpu_t),
420
421 GATE(CORE_L2C, "core_l2c", "aclk_cpu", 0,
422 RK2928_CLKGATE_CON(9), 4, GFLAGS),
423
424 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
425 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
426 RK2928_CLKGATE_CON(2), 0, GFLAGS),
427
428 COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
429 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
430 RK2928_CLKGATE_CON(3), 1, GFLAGS),
431 MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0,
432 RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
433 COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
434 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
435 RK2928_CLKGATE_CON(3), 2, GFLAGS),
436 MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0,
437 RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
438
439 COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,
440 RK2928_CLKSEL_CON(29), 8, 5, DFLAGS,
441 RK2928_CLKGATE_CON(3), 8, GFLAGS),
442 MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0,
443 RK2928_CLKSEL_CON(29), 15, 1, MFLAGS),
444
445 GATE(0, "pclkin_cif1", "ext_cif1", 0,
446 RK2928_CLKGATE_CON(3), 4, GFLAGS),
447
448 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
449 RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS,
450 RK2928_CLKGATE_CON(3), 13, GFLAGS),
451 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
452 RK2928_CLKGATE_CON(5), 15, GFLAGS),
453
454 GATE(SCLK_TIMER2, "timer2", "xin24m", 0,
455 RK2928_CLKGATE_CON(3), 2, GFLAGS),
456
457 COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0,
458 RK2928_CLKSEL_CON(34), 0, 16, DFLAGS,
459 RK2928_CLKGATE_CON(2), 15, GFLAGS),
460
461 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
462 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
463 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
464 RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
465 RK2928_CLKGATE_CON(0), 7, GFLAGS),
466 COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0,
467 RK2928_CLKSEL_CON(6), 0,
468 RK2928_CLKGATE_CON(0), 8, GFLAGS),
469 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
470 RK2928_CLKSEL_CON(2), 8, 2, MFLAGS),
471 COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
472 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
473 RK2928_CLKGATE_CON(0), 9, GFLAGS),
474 COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_pre", 0,
475 RK2928_CLKSEL_CON(7), 0,
476 RK2928_CLKGATE_CON(0), 10, GFLAGS),
477 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
478 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
479 COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
480 RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
481 RK2928_CLKGATE_CON(0), 11, GFLAGS),
482 COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_pre", 0,
483 RK2928_CLKSEL_CON(8), 0,
484 RK2928_CLKGATE_CON(0), 12, GFLAGS),
485 MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
486 RK2928_CLKSEL_CON(4), 8, 2, MFLAGS),
487 COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
488 RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
489 RK2928_CLKGATE_CON(0), 13, GFLAGS),
490 COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
491 RK2928_CLKSEL_CON(9), 0,
492 RK2928_CLKGATE_CON(0), 14, GFLAGS),
493 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
494 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
495
496 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
497 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
498 GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
499 GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
500
501 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
502
503 GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
504
505 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
506 GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
507 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
508 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
509 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
510
511 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
512 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS),
513};
514
515static struct clk_div_table div_rk3188_aclk_core_t[] = {
516 { .val = 0, .div = 1 },
517 { .val = 1, .div = 2 },
518 { .val = 2, .div = 3 },
519 { .val = 3, .div = 4 },
520 { .val = 4, .div = 8 },
521 { /* sentinel */ },
522};
523
524PNAME(mux_hsicphy_p) = { "sclk_otgphy0", "sclk_otgphy1",
525 "gpll", "cpll" };
526
527static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
528 COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0,
529 RK2928_CLKSEL_CON(0), 8, 1, MFLAGS, 9, 5, DFLAGS),
530 COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", 0,
531 RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
532 div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
533
534 /* do not source aclk_cpu_pre from the apll, to keep complexity down */
535 COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
536 RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
537
538 GATE(CORE_L2C, "core_l2c", "armclk", 0,
539 RK2928_CLKGATE_CON(9), 4, GFLAGS),
540
541 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
542 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
543 RK2928_CLKGATE_CON(2), 0, GFLAGS),
544
545 COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0,
546 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
547 RK2928_CLKGATE_CON(3), 1, GFLAGS),
548 COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0,
549 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
550 RK2928_CLKGATE_CON(3), 2, GFLAGS),
551
552 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
553 RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS,
554 RK2928_CLKGATE_CON(3), 15, GFLAGS),
555 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
556 RK2928_CLKGATE_CON(9), 7, GFLAGS),
557
558 GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS),
559 GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS),
560 GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
561 GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
562 GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
563
564 COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0,
565 RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
566 RK2928_CLKGATE_CON(3), 6, GFLAGS),
567 DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
568 RK2928_CLKGATE_CON(11), 8, 6, DFLAGS),
569
570 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
571 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
572 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
573 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
574 RK2928_CLKGATE_CON(0), 9, GFLAGS),
575 COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0,
576 RK2928_CLKSEL_CON(7), 0,
577 RK2928_CLKGATE_CON(0), 10, GFLAGS),
578 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
579 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
580 COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
581 RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
582 RK2928_CLKGATE_CON(13), 13, GFLAGS),
583 COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
584 RK2928_CLKSEL_CON(9), 0,
585 RK2928_CLKGATE_CON(0), 14, GFLAGS),
586 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
587 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
588
589 GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
590 GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
591
592 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
593 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
594
595 GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
596
597 GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
598 GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
599
600 GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
601};
602
Heiko Stübnerfe94f972014-08-14 23:00:26 +0200[diff] [blame]603static const char *rk3188_critical_clocks[] __initconst = {
604 "aclk_cpu",
605 "aclk_peri",
Heiko Stübner2fed71e2014-09-10 17:52:02 +0200[diff] [blame]606 "hclk_peri",
Heiko Stübnerfe94f972014-08-14 23:00:26 +0200[diff] [blame]607};
608
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]609static void __init rk3188_common_clk_init(struct device_node *np)
610{
611 void __iomem *reg_base;
612 struct clk *clk;
613
614 reg_base = of_iomap(np, 0);
615 if (!reg_base) {
616 pr_err("%s: could not map cru region\n", __func__);
617 return;
618 }
619
620 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
621
622 /* xin12m is created by an cru-internal divider */
623 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
624 if (IS_ERR(clk))
625 pr_warn("%s: could not register clock xin12m: %ld\n",
626 __func__, PTR_ERR(clk));
627
628 clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
629 if (IS_ERR(clk))
630 pr_warn("%s: could not register clock usb480m: %ld\n",
631 __func__, PTR_ERR(clk));
632
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]633 rockchip_clk_register_branches(common_clk_branches,
634 ARRAY_SIZE(common_clk_branches));
Heiko Stübnerfe94f972014-08-14 23:00:26 +0200[diff] [blame]635 rockchip_clk_protect_critical(rk3188_critical_clocks,
636 ARRAY_SIZE(rk3188_critical_clocks));
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]637
638 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
639 ROCKCHIP_SOFTRST_HIWORD_MASK);
640}
641
642static void __init rk3066a_clk_init(struct device_node *np)
643{
644 rk3188_common_clk_init(np);
Heiko Stuebner11ff3762014-09-01 23:52:40 +0200[diff] [blame^]645 rockchip_clk_register_plls(rk3188_pll_clks,
646 ARRAY_SIZE(rk3188_pll_clks),
647 RK3066_GRF_SOC_STATUS);
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]648 rockchip_clk_register_branches(rk3066a_clk_branches,
649 ARRAY_SIZE(rk3066a_clk_branches));
650}
651CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
652
653static void __init rk3188a_clk_init(struct device_node *np)
654{
655 rk3188_common_clk_init(np);
Heiko Stuebner11ff3762014-09-01 23:52:40 +0200[diff] [blame^]656 rockchip_clk_register_plls(rk3188_pll_clks,
657 ARRAY_SIZE(rk3188_pll_clks),
658 RK3188_GRF_SOC_STATUS);
Heiko Stübner2c14736c2014-07-03 02:01:14 +0200[diff] [blame]659 rockchip_clk_register_branches(rk3188_clk_branches,
660 ARRAY_SIZE(rk3188_clk_branches));
661}
662CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);
663
664static void __init rk3188_clk_init(struct device_node *np)
665{
666 int i;
667
668 for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) {
669 struct rockchip_pll_clock *pll = &rk3188_pll_clks[i];
670 struct rockchip_pll_rate_table *rate;
671
672 if (!pll->rate_table)
673 continue;
674
675 rate = pll->rate_table;
676 while (rate->rate > 0) {
677 rate->bwadj = 0;
678 rate++;
679 }
680 }
681
682 rk3188a_clk_init(np);
683}
684CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init);