Yakir Yang | 12df9c5 | 2016-02-15 19:01:43 +0800 | [diff] [blame^] | 1 | Rockchip specific extensions to the Analogix Display Port PHY |
| 2 | ------------------------------------ |
| 3 | |
| 4 | Required properties: |
| 5 | - compatible : should be one of the following supported values: |
| 6 | - "rockchip.rk3288-dp-phy" |
| 7 | - clocks: from common clock binding: handle to dp clock. |
| 8 | of memory mapped region. |
| 9 | - clock-names: from common clock binding: |
| 10 | Required elements: "24m" |
| 11 | - rockchip,grf: phandle to the syscon managing the "general register files" |
| 12 | - #phy-cells : from the generic PHY bindings, must be 0; |
| 13 | |
| 14 | Example: |
| 15 | |
| 16 | edp_phy: edp-phy { |
| 17 | compatible = "rockchip,rk3288-dp-phy"; |
| 18 | rockchip,grf = <&grf>; |
| 19 | clocks = <&cru SCLK_EDP_24M>; |
| 20 | clock-names = "24m"; |
| 21 | #phy-cells = <0>; |
| 22 | }; |