blob: 20e664e341632df52877c78ef10ce96f6bc57301 [file] [log] [blame]
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -03001/*
2 * Register interface file for Samsung Camera Interface (FIMC) driver
3 *
4 * Copyright (c) 2010 Samsung Electronics
5 *
6 * Sylwester Nawrocki, s.nawrocki@samsung.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <linux/delay.h>
15#include <mach/map.h>
Sylwester Nawrockidf7e09a2010-12-27 14:42:15 -030016#include <media/s5p_fimc.h>
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -030017
18#include "fimc-core.h"
19
20
21void fimc_hw_reset(struct fimc_dev *dev)
22{
23 u32 cfg;
24
25 cfg = readl(dev->regs + S5P_CISRCFMT);
26 cfg |= S5P_CISRCFMT_ITU601_8BIT;
27 writel(cfg, dev->regs + S5P_CISRCFMT);
28
29 /* Software reset. */
30 cfg = readl(dev->regs + S5P_CIGCTRL);
31 cfg |= (S5P_CIGCTRL_SWRST | S5P_CIGCTRL_IRQ_LEVEL);
32 writel(cfg, dev->regs + S5P_CIGCTRL);
Sylwester Nawrockie9e21082011-09-02 06:25:32 -030033 udelay(10);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -030034
35 cfg = readl(dev->regs + S5P_CIGCTRL);
36 cfg &= ~S5P_CIGCTRL_SWRST;
37 writel(cfg, dev->regs + S5P_CIGCTRL);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -030038}
39
Sylwester Nawrockiac759342010-12-27 14:47:32 -030040static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -030041{
42 u32 flip = S5P_MSCTRL_FLIP_NORMAL;
43
Sylwester Nawrocki131b6c62011-08-24 19:25:10 -030044 if (ctx->hflip)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -030045 flip = S5P_MSCTRL_FLIP_X_MIRROR;
Sylwester Nawrocki131b6c62011-08-24 19:25:10 -030046 if (ctx->vflip)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -030047 flip = S5P_MSCTRL_FLIP_Y_MIRROR;
Sylwester Nawrocki131b6c62011-08-24 19:25:10 -030048
Sylwester Nawrockiac759342010-12-27 14:47:32 -030049 if (ctx->rotation <= 90)
50 return flip;
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -030051
Sylwester Nawrockiac759342010-12-27 14:47:32 -030052 return (flip ^ S5P_MSCTRL_FLIP_180) & S5P_MSCTRL_FLIP_180;
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -030053}
54
Sylwester Nawrockiac759342010-12-27 14:47:32 -030055static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -030056{
57 u32 flip = S5P_CITRGFMT_FLIP_NORMAL;
58
Sylwester Nawrocki131b6c62011-08-24 19:25:10 -030059 if (ctx->hflip)
60 flip |= S5P_CITRGFMT_FLIP_X_MIRROR;
61 if (ctx->vflip)
62 flip |= S5P_CITRGFMT_FLIP_Y_MIRROR;
63
Sylwester Nawrockiac759342010-12-27 14:47:32 -030064 if (ctx->rotation <= 90)
65 return flip;
66
67 return (flip ^ S5P_CITRGFMT_FLIP_180) & S5P_CITRGFMT_FLIP_180;
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -030068}
69
Sylwester Nawrocki47654df2010-10-08 05:01:22 -030070void fimc_hw_set_rotation(struct fimc_ctx *ctx)
71{
72 u32 cfg, flip;
73 struct fimc_dev *dev = ctx->fimc_dev;
74
75 cfg = readl(dev->regs + S5P_CITRGFMT);
76 cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90 |
Sylwester Nawrockiac759342010-12-27 14:47:32 -030077 S5P_CITRGFMT_FLIP_180);
Sylwester Nawrocki47654df2010-10-08 05:01:22 -030078
79 /*
80 * The input and output rotator cannot work simultaneously.
81 * Use the output rotator in output DMA mode or the input rotator
82 * in direct fifo output mode.
83 */
84 if (ctx->rotation == 90 || ctx->rotation == 270) {
Sylwester Nawrocki47654df2010-10-08 05:01:22 -030085 if (ctx->out_path == FIMC_LCDFIFO)
Sylwester Nawrockiac759342010-12-27 14:47:32 -030086 cfg |= S5P_CITRGFMT_INROT90;
Sylwester Nawrocki47654df2010-10-08 05:01:22 -030087 else
Sylwester Nawrockiac759342010-12-27 14:47:32 -030088 cfg |= S5P_CITRGFMT_OUTROT90;
Sylwester Nawrocki47654df2010-10-08 05:01:22 -030089 }
Sylwester Nawrocki47654df2010-10-08 05:01:22 -030090
Sylwester Nawrockiac759342010-12-27 14:47:32 -030091 if (ctx->out_path == FIMC_DMA) {
92 cfg |= fimc_hw_get_target_flip(ctx);
93 writel(cfg, dev->regs + S5P_CITRGFMT);
94 } else {
95 /* LCD FIFO path */
96 flip = readl(dev->regs + S5P_MSCTRL);
97 flip &= ~S5P_MSCTRL_FLIP_MASK;
98 flip |= fimc_hw_get_in_flip(ctx);
99 writel(flip, dev->regs + S5P_MSCTRL);
100 }
Sylwester Nawrocki47654df2010-10-08 05:01:22 -0300101}
102
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300103void fimc_hw_set_target_format(struct fimc_ctx *ctx)
104{
105 u32 cfg;
106 struct fimc_dev *dev = ctx->fimc_dev;
107 struct fimc_frame *frame = &ctx->d_frame;
108
109 dbg("w= %d, h= %d color: %d", frame->width,
110 frame->height, frame->fmt->color);
111
112 cfg = readl(dev->regs + S5P_CITRGFMT);
113 cfg &= ~(S5P_CITRGFMT_FMT_MASK | S5P_CITRGFMT_HSIZE_MASK |
114 S5P_CITRGFMT_VSIZE_MASK);
115
116 switch (frame->fmt->color) {
Sylwester Nawrockiac759342010-12-27 14:47:32 -0300117 case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300118 cfg |= S5P_CITRGFMT_RGB;
119 break;
120 case S5P_FIMC_YCBCR420:
121 cfg |= S5P_CITRGFMT_YCBCR420;
122 break;
Sylwester Nawrockiac759342010-12-27 14:47:32 -0300123 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422:
Sylwester Nawrockief7af592010-12-08 14:05:08 -0300124 if (frame->fmt->colplanes == 1)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300125 cfg |= S5P_CITRGFMT_YCBCR422_1P;
126 else
127 cfg |= S5P_CITRGFMT_YCBCR422;
128 break;
129 default:
130 break;
131 }
132
Sylwester Nawrocki47654df2010-10-08 05:01:22 -0300133 if (ctx->rotation == 90 || ctx->rotation == 270) {
134 cfg |= S5P_CITRGFMT_HSIZE(frame->height);
135 cfg |= S5P_CITRGFMT_VSIZE(frame->width);
136 } else {
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300137
Sylwester Nawrocki47654df2010-10-08 05:01:22 -0300138 cfg |= S5P_CITRGFMT_HSIZE(frame->width);
139 cfg |= S5P_CITRGFMT_VSIZE(frame->height);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300140 }
Sylwester Nawrocki47654df2010-10-08 05:01:22 -0300141
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300142 writel(cfg, dev->regs + S5P_CITRGFMT);
143
144 cfg = readl(dev->regs + S5P_CITAREA) & ~S5P_CITAREA_MASK;
145 cfg |= (frame->width * frame->height);
146 writel(cfg, dev->regs + S5P_CITAREA);
147}
148
149static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
150{
151 struct fimc_dev *dev = ctx->fimc_dev;
152 struct fimc_frame *frame = &ctx->d_frame;
Sylwester Nawrocki47654df2010-10-08 05:01:22 -0300153 u32 cfg;
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300154
Sylwester Nawrocki47654df2010-10-08 05:01:22 -0300155 cfg = S5P_ORIG_SIZE_HOR(frame->f_width);
156 cfg |= S5P_ORIG_SIZE_VER(frame->f_height);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300157 writel(cfg, dev->regs + S5P_ORGOSIZE);
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300158
159 /* Select color space conversion equation (HD/SD size).*/
160 cfg = readl(dev->regs + S5P_CIGCTRL);
161 if (frame->f_width >= 1280) /* HD */
162 cfg |= S5P_CIGCTRL_CSC_ITU601_709;
163 else /* SD */
164 cfg &= ~S5P_CIGCTRL_CSC_ITU601_709;
165 writel(cfg, dev->regs + S5P_CIGCTRL);
166
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300167}
168
169void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
170{
171 u32 cfg;
172 struct fimc_dev *dev = ctx->fimc_dev;
173 struct fimc_frame *frame = &ctx->d_frame;
174 struct fimc_dma_offset *offset = &frame->dma_offset;
175
176 /* Set the input dma offsets. */
177 cfg = 0;
178 cfg |= S5P_CIO_OFFS_HOR(offset->y_h);
179 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
180 writel(cfg, dev->regs + S5P_CIOYOFF);
181
182 cfg = 0;
183 cfg |= S5P_CIO_OFFS_HOR(offset->cb_h);
184 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
185 writel(cfg, dev->regs + S5P_CIOCBOFF);
186
187 cfg = 0;
188 cfg |= S5P_CIO_OFFS_HOR(offset->cr_h);
189 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
190 writel(cfg, dev->regs + S5P_CIOCROFF);
191
192 fimc_hw_set_out_dma_size(ctx);
193
194 /* Configure chroma components order. */
195 cfg = readl(dev->regs + S5P_CIOCTRL);
196
197 cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK |
198 S5P_CIOCTRL_YCBCR_PLANE_MASK);
199
Sylwester Nawrockief7af592010-12-08 14:05:08 -0300200 if (frame->fmt->colplanes == 1)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300201 cfg |= ctx->out_order_1p;
Sylwester Nawrockief7af592010-12-08 14:05:08 -0300202 else if (frame->fmt->colplanes == 2)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300203 cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE;
Sylwester Nawrockief7af592010-12-08 14:05:08 -0300204 else if (frame->fmt->colplanes == 3)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300205 cfg |= S5P_CIOCTRL_YCBCR_3PLANE;
206
207 writel(cfg, dev->regs + S5P_CIOCTRL);
208}
209
210static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
211{
212 u32 cfg = readl(dev->regs + S5P_ORGISIZE);
213 if (enable)
214 cfg |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
215 else
216 cfg &= ~S5P_CIREAL_ISIZE_AUTOLOAD_EN;
217 writel(cfg, dev->regs + S5P_ORGISIZE);
218}
219
220void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
221{
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300222 u32 cfg = readl(dev->regs + S5P_CIOCTRL);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300223 if (enable)
224 cfg |= S5P_CIOCTRL_LASTIRQ_ENABLE;
225 else
226 cfg &= ~S5P_CIOCTRL_LASTIRQ_ENABLE;
227 writel(cfg, dev->regs + S5P_CIOCTRL);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300228}
229
Hyunwoong Kimb241c6d2010-12-28 11:27:13 -0300230void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300231{
232 struct fimc_dev *dev = ctx->fimc_dev;
233 struct fimc_scaler *sc = &ctx->scaler;
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300234 u32 cfg, shfactor;
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300235
236 shfactor = 10 - (sc->hfactor + sc->vfactor);
237
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300238 cfg = S5P_CISCPRERATIO_SHFACTOR(shfactor);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300239 cfg |= S5P_CISCPRERATIO_HOR(sc->pre_hratio);
240 cfg |= S5P_CISCPRERATIO_VER(sc->pre_vratio);
241 writel(cfg, dev->regs + S5P_CISCPRERATIO);
242
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300243 cfg = S5P_CISCPREDST_WIDTH(sc->pre_dst_width);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300244 cfg |= S5P_CISCPREDST_HEIGHT(sc->pre_dst_height);
245 writel(cfg, dev->regs + S5P_CISCPREDST);
246}
247
Hyunwoong Kimb241c6d2010-12-28 11:27:13 -0300248static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300249{
250 struct fimc_dev *dev = ctx->fimc_dev;
251 struct fimc_scaler *sc = &ctx->scaler;
252 struct fimc_frame *src_frame = &ctx->s_frame;
253 struct fimc_frame *dst_frame = &ctx->d_frame;
254 u32 cfg = 0;
255
256 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
257 cfg |= (S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE);
258
259 if (!sc->enabled)
260 cfg |= S5P_CISCCTRL_SCALERBYPASS;
261
262 if (sc->scaleup_h)
263 cfg |= S5P_CISCCTRL_SCALEUP_H;
264
265 if (sc->scaleup_v)
266 cfg |= S5P_CISCCTRL_SCALEUP_V;
267
268 if (sc->copy_mode)
269 cfg |= S5P_CISCCTRL_ONE2ONE;
270
271
272 if (ctx->in_path == FIMC_DMA) {
273 if (src_frame->fmt->color == S5P_FIMC_RGB565)
274 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB565;
275 else if (src_frame->fmt->color == S5P_FIMC_RGB666)
276 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB666;
277 else if (src_frame->fmt->color == S5P_FIMC_RGB888)
278 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB888;
279 }
280
281 if (ctx->out_path == FIMC_DMA) {
282 if (dst_frame->fmt->color == S5P_FIMC_RGB565)
283 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB565;
284 else if (dst_frame->fmt->color == S5P_FIMC_RGB666)
285 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB666;
286 else if (dst_frame->fmt->color == S5P_FIMC_RGB888)
287 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
288 } else {
289 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
290
291 if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
292 cfg |= S5P_CISCCTRL_INTERLACE;
293 }
294
Hyunwoong Kimb241c6d2010-12-28 11:27:13 -0300295 writel(cfg, dev->regs + S5P_CISCCTRL);
296}
297
298void fimc_hw_set_mainscaler(struct fimc_ctx *ctx)
299{
300 struct fimc_dev *dev = ctx->fimc_dev;
Sylwester Nawrocki70f66ea2010-12-28 11:37:55 -0300301 struct samsung_fimc_variant *variant = dev->variant;
Hyunwoong Kimb241c6d2010-12-28 11:27:13 -0300302 struct fimc_scaler *sc = &ctx->scaler;
303 u32 cfg;
304
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300305 dbg("main_hratio= 0x%X main_vratio= 0x%X",
306 sc->main_hratio, sc->main_vratio);
307
Hyunwoong Kimb241c6d2010-12-28 11:27:13 -0300308 fimc_hw_set_scaler(ctx);
309
310 cfg = readl(dev->regs + S5P_CISCCTRL);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300311
Sylwester Nawrocki70f66ea2010-12-28 11:37:55 -0300312 if (variant->has_mainscaler_ext) {
313 cfg &= ~(S5P_CISCCTRL_MHRATIO_MASK | S5P_CISCCTRL_MVRATIO_MASK);
314 cfg |= S5P_CISCCTRL_MHRATIO_EXT(sc->main_hratio);
315 cfg |= S5P_CISCCTRL_MVRATIO_EXT(sc->main_vratio);
316 writel(cfg, dev->regs + S5P_CISCCTRL);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300317
Sylwester Nawrocki70f66ea2010-12-28 11:37:55 -0300318 cfg = readl(dev->regs + S5P_CIEXTEN);
Hyunwoong Kimb241c6d2010-12-28 11:27:13 -0300319
Sylwester Nawrocki70f66ea2010-12-28 11:37:55 -0300320 cfg &= ~(S5P_CIEXTEN_MVRATIO_EXT_MASK |
321 S5P_CIEXTEN_MHRATIO_EXT_MASK);
322 cfg |= S5P_CIEXTEN_MHRATIO_EXT(sc->main_hratio);
323 cfg |= S5P_CIEXTEN_MVRATIO_EXT(sc->main_vratio);
324 writel(cfg, dev->regs + S5P_CIEXTEN);
325 } else {
326 cfg &= ~(S5P_CISCCTRL_MHRATIO_MASK | S5P_CISCCTRL_MVRATIO_MASK);
327 cfg |= S5P_CISCCTRL_MHRATIO(sc->main_hratio);
328 cfg |= S5P_CISCCTRL_MVRATIO(sc->main_vratio);
329 writel(cfg, dev->regs + S5P_CISCCTRL);
330 }
Hyunwoong Kimb241c6d2010-12-28 11:27:13 -0300331}
332
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300333void fimc_hw_en_capture(struct fimc_ctx *ctx)
334{
335 struct fimc_dev *dev = ctx->fimc_dev;
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300336
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300337 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
338
339 if (ctx->out_path == FIMC_DMA) {
340 /* one shot mode */
341 cfg |= S5P_CIIMGCPT_CPT_FREN_ENABLE | S5P_CIIMGCPT_IMGCPTEN;
342 } else {
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300343 /* Continuous frame capture mode (freerun). */
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300344 cfg &= ~(S5P_CIIMGCPT_CPT_FREN_ENABLE |
345 S5P_CIIMGCPT_CPT_FRMOD_CNT);
346 cfg |= S5P_CIIMGCPT_IMGCPTEN;
347 }
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300348
349 if (ctx->scaler.enabled)
350 cfg |= S5P_CIIMGCPT_IMGCPTEN_SC;
351
352 writel(cfg | S5P_CIIMGCPT_IMGCPTEN, dev->regs + S5P_CIIMGCPT);
353}
354
Sylwester Nawrockiee7160e2011-08-26 14:57:06 -0300355void fimc_hw_set_effect(struct fimc_ctx *ctx, bool active)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300356{
357 struct fimc_dev *dev = ctx->fimc_dev;
358 struct fimc_effect *effect = &ctx->effect;
Sylwester Nawrockiee7160e2011-08-26 14:57:06 -0300359 u32 cfg = 0;
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300360
Sylwester Nawrockiee7160e2011-08-26 14:57:06 -0300361 if (active) {
362 cfg |= S5P_CIIMGEFF_IE_SC_AFTER | S5P_CIIMGEFF_IE_ENABLE;
363 cfg |= effect->type;
364 if (effect->type == S5P_FIMC_EFFECT_ARBITRARY) {
365 cfg |= S5P_CIIMGEFF_PAT_CB(effect->pat_cb);
366 cfg |= S5P_CIIMGEFF_PAT_CR(effect->pat_cr);
367 }
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300368 }
369
370 writel(cfg, dev->regs + S5P_CIIMGEFF);
371}
372
373static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
374{
375 struct fimc_dev *dev = ctx->fimc_dev;
376 struct fimc_frame *frame = &ctx->s_frame;
377 u32 cfg_o = 0;
378 u32 cfg_r = 0;
379
380 if (FIMC_LCDFIFO == ctx->out_path)
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300381 cfg_r |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300382
383 cfg_o |= S5P_ORIG_SIZE_HOR(frame->f_width);
384 cfg_o |= S5P_ORIG_SIZE_VER(frame->f_height);
385 cfg_r |= S5P_CIREAL_ISIZE_WIDTH(frame->width);
386 cfg_r |= S5P_CIREAL_ISIZE_HEIGHT(frame->height);
387
388 writel(cfg_o, dev->regs + S5P_ORGISIZE);
389 writel(cfg_r, dev->regs + S5P_CIREAL_ISIZE);
390}
391
392void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
393{
394 struct fimc_dev *dev = ctx->fimc_dev;
395 struct fimc_frame *frame = &ctx->s_frame;
396 struct fimc_dma_offset *offset = &frame->dma_offset;
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300397 u32 cfg;
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300398
399 /* Set the pixel offsets. */
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300400 cfg = S5P_CIO_OFFS_HOR(offset->y_h);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300401 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
402 writel(cfg, dev->regs + S5P_CIIYOFF);
403
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300404 cfg = S5P_CIO_OFFS_HOR(offset->cb_h);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300405 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
406 writel(cfg, dev->regs + S5P_CIICBOFF);
407
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300408 cfg = S5P_CIO_OFFS_HOR(offset->cr_h);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300409 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
410 writel(cfg, dev->regs + S5P_CIICROFF);
411
412 /* Input original and real size. */
413 fimc_hw_set_in_dma_size(ctx);
414
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300415 /* Use DMA autoload only in FIFO mode. */
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300416 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO);
417
418 /* Set the input DMA to process single frame only. */
419 cfg = readl(dev->regs + S5P_MSCTRL);
Sylwester Nawrockiac759342010-12-27 14:47:32 -0300420 cfg &= ~(S5P_MSCTRL_INFORMAT_MASK
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300421 | S5P_MSCTRL_IN_BURST_COUNT_MASK
422 | S5P_MSCTRL_INPUT_MASK
423 | S5P_MSCTRL_C_INT_IN_MASK
424 | S5P_MSCTRL_2P_IN_ORDER_MASK);
425
Hyunwoong Kim5bbe425e2010-12-29 07:08:32 -0300426 cfg |= (S5P_MSCTRL_IN_BURST_COUNT(4)
427 | S5P_MSCTRL_INPUT_MEMORY
428 | S5P_MSCTRL_FIFO_CTRL_FULL);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300429
430 switch (frame->fmt->color) {
Sylwester Nawrockid9160af2010-12-08 12:48:23 -0300431 case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300432 cfg |= S5P_MSCTRL_INFORMAT_RGB;
433 break;
434 case S5P_FIMC_YCBCR420:
435 cfg |= S5P_MSCTRL_INFORMAT_YCBCR420;
436
Sylwester Nawrockief7af592010-12-08 14:05:08 -0300437 if (frame->fmt->colplanes == 2)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300438 cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE;
439 else
440 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
441
442 break;
Sylwester Nawrockid9160af2010-12-08 12:48:23 -0300443 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422:
Sylwester Nawrockief7af592010-12-08 14:05:08 -0300444 if (frame->fmt->colplanes == 1) {
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300445 cfg |= ctx->in_order_1p
446 | S5P_MSCTRL_INFORMAT_YCBCR422_1P;
447 } else {
448 cfg |= S5P_MSCTRL_INFORMAT_YCBCR422;
449
Sylwester Nawrockief7af592010-12-08 14:05:08 -0300450 if (frame->fmt->colplanes == 2)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300451 cfg |= ctx->in_order_2p
452 | S5P_MSCTRL_C_INT_IN_2PLANE;
453 else
454 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
455 }
456 break;
457 default:
458 break;
459 }
460
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300461 writel(cfg, dev->regs + S5P_MSCTRL);
462
463 /* Input/output DMA linear/tiled mode. */
464 cfg = readl(dev->regs + S5P_CIDMAPARAM);
465 cfg &= ~S5P_CIDMAPARAM_TILE_MASK;
466
467 if (tiled_fmt(ctx->s_frame.fmt))
468 cfg |= S5P_CIDMAPARAM_R_64X32;
469
470 if (tiled_fmt(ctx->d_frame.fmt))
471 cfg |= S5P_CIDMAPARAM_W_64X32;
472
473 writel(cfg, dev->regs + S5P_CIDMAPARAM);
474}
475
476
477void fimc_hw_set_input_path(struct fimc_ctx *ctx)
478{
479 struct fimc_dev *dev = ctx->fimc_dev;
480
481 u32 cfg = readl(dev->regs + S5P_MSCTRL);
482 cfg &= ~S5P_MSCTRL_INPUT_MASK;
483
484 if (ctx->in_path == FIMC_DMA)
485 cfg |= S5P_MSCTRL_INPUT_MEMORY;
486 else
487 cfg |= S5P_MSCTRL_INPUT_EXTCAM;
488
489 writel(cfg, dev->regs + S5P_MSCTRL);
490}
491
492void fimc_hw_set_output_path(struct fimc_ctx *ctx)
493{
494 struct fimc_dev *dev = ctx->fimc_dev;
495
496 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
497 cfg &= ~S5P_CISCCTRL_LCDPATHEN_FIFO;
498 if (ctx->out_path == FIMC_LCDFIFO)
499 cfg |= S5P_CISCCTRL_LCDPATHEN_FIFO;
500 writel(cfg, dev->regs + S5P_CISCCTRL);
501}
502
503void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
504{
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300505 u32 cfg = readl(dev->regs + S5P_CIREAL_ISIZE);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300506 cfg |= S5P_CIREAL_ISIZE_ADDR_CH_DIS;
507 writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
508
Sylwester Nawrocki77e62082010-09-28 05:49:11 -0300509 writel(paddr->y, dev->regs + S5P_CIIYSA(0));
510 writel(paddr->cb, dev->regs + S5P_CIICBSA(0));
511 writel(paddr->cr, dev->regs + S5P_CIICRSA(0));
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300512
513 cfg &= ~S5P_CIREAL_ISIZE_ADDR_CH_DIS;
514 writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
515}
516
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300517void fimc_hw_set_output_addr(struct fimc_dev *dev,
518 struct fimc_addr *paddr, int index)
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300519{
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300520 int i = (index == -1) ? 0 : index;
521 do {
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300522 writel(paddr->y, dev->regs + S5P_CIOYSA(i));
523 writel(paddr->cb, dev->regs + S5P_CIOCBSA(i));
524 writel(paddr->cr, dev->regs + S5P_CIOCRSA(i));
Sylwester Nawrocki548aafc2010-10-08 05:01:14 -0300525 dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
526 i, paddr->y, paddr->cb, paddr->cr);
527 } while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
Sylwester Nawrocki5fd8f732010-08-03 09:50:29 -0300528}
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300529
530int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
Sylwester Nawrockidf7e09a2010-12-27 14:42:15 -0300531 struct s5p_fimc_isp_info *cam)
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300532{
533 u32 cfg = readl(fimc->regs + S5P_CIGCTRL);
534
535 cfg &= ~(S5P_CIGCTRL_INVPOLPCLK | S5P_CIGCTRL_INVPOLVSYNC |
Sylwester Nawrocki12ecf562011-09-19 12:38:35 -0300536 S5P_CIGCTRL_INVPOLHREF | S5P_CIGCTRL_INVPOLHSYNC |
537 S5P_CIGCTRL_INVPOLFIELD);
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300538
Sylwester Nawrocki12ecf562011-09-19 12:38:35 -0300539 if (cam->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300540 cfg |= S5P_CIGCTRL_INVPOLPCLK;
541
Sylwester Nawrocki12ecf562011-09-19 12:38:35 -0300542 if (cam->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300543 cfg |= S5P_CIGCTRL_INVPOLVSYNC;
544
Sylwester Nawrocki12ecf562011-09-19 12:38:35 -0300545 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300546 cfg |= S5P_CIGCTRL_INVPOLHREF;
547
Sylwester Nawrocki12ecf562011-09-19 12:38:35 -0300548 if (cam->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300549 cfg |= S5P_CIGCTRL_INVPOLHSYNC;
550
Sylwester Nawrocki12ecf562011-09-19 12:38:35 -0300551 if (cam->flags & V4L2_MBUS_FIELD_EVEN_LOW)
552 cfg |= S5P_CIGCTRL_INVPOLFIELD;
553
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300554 writel(cfg, fimc->regs + S5P_CIGCTRL);
555
556 return 0;
557}
558
559int fimc_hw_set_camera_source(struct fimc_dev *fimc,
Sylwester Nawrockidf7e09a2010-12-27 14:42:15 -0300560 struct s5p_fimc_isp_info *cam)
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300561{
562 struct fimc_frame *f = &fimc->vid_cap.ctx->s_frame;
563 u32 cfg = 0;
Sylwester Nawrocki3d0ce7e2010-12-27 15:02:16 -0300564 u32 bus_width;
565 int i;
566
567 static const struct {
568 u32 pixelcode;
569 u32 cisrcfmt;
570 u16 bus_width;
571 } pix_desc[] = {
572 { V4L2_MBUS_FMT_YUYV8_2X8, S5P_CISRCFMT_ORDER422_YCBYCR, 8 },
573 { V4L2_MBUS_FMT_YVYU8_2X8, S5P_CISRCFMT_ORDER422_YCRYCB, 8 },
574 { V4L2_MBUS_FMT_VYUY8_2X8, S5P_CISRCFMT_ORDER422_CRYCBY, 8 },
575 { V4L2_MBUS_FMT_UYVY8_2X8, S5P_CISRCFMT_ORDER422_CBYCRY, 8 },
576 /* TODO: Add pixel codes for 16-bit bus width */
577 };
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300578
579 if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) {
Sylwester Nawrocki3d0ce7e2010-12-27 15:02:16 -0300580 for (i = 0; i < ARRAY_SIZE(pix_desc); i++) {
Sylwester Nawrocki237e0262011-08-24 20:35:30 -0300581 if (fimc->vid_cap.mf.code == pix_desc[i].pixelcode) {
Sylwester Nawrocki3d0ce7e2010-12-27 15:02:16 -0300582 cfg = pix_desc[i].cisrcfmt;
583 bus_width = pix_desc[i].bus_width;
584 break;
585 }
586 }
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300587
Sylwester Nawrocki3d0ce7e2010-12-27 15:02:16 -0300588 if (i == ARRAY_SIZE(pix_desc)) {
Sylwester Nawrocki30c99392011-06-10 15:36:48 -0300589 v4l2_err(fimc->vid_cap.vfd,
Sylwester Nawrocki3d0ce7e2010-12-27 15:02:16 -0300590 "Camera color format not supported: %d\n",
Sylwester Nawrocki237e0262011-08-24 20:35:30 -0300591 fimc->vid_cap.mf.code);
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300592 return -EINVAL;
593 }
594
595 if (cam->bus_type == FIMC_ITU_601) {
Sylwester Nawrocki3d0ce7e2010-12-27 15:02:16 -0300596 if (bus_width == 8)
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300597 cfg |= S5P_CISRCFMT_ITU601_8BIT;
Sylwester Nawrocki3d0ce7e2010-12-27 15:02:16 -0300598 else if (bus_width == 16)
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300599 cfg |= S5P_CISRCFMT_ITU601_16BIT;
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300600 } /* else defaults to ITU-R BT.656 8-bit */
Sylwester Nawrockiee7160e2011-08-26 14:57:06 -0300601 } else if (cam->bus_type == FIMC_MIPI_CSI2) {
602 if (fimc_fmt_is_jpeg(f->fmt->color))
603 cfg |= S5P_CISRCFMT_ITU601_8BIT;
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300604 }
605
606 cfg |= S5P_CISRCFMT_HSIZE(f->o_width) | S5P_CISRCFMT_VSIZE(f->o_height);
607 writel(cfg, fimc->regs + S5P_CISRCFMT);
608 return 0;
609}
610
611
612int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f)
613{
614 u32 hoff2, voff2;
615
616 u32 cfg = readl(fimc->regs + S5P_CIWDOFST);
617
618 cfg &= ~(S5P_CIWDOFST_HOROFF_MASK | S5P_CIWDOFST_VEROFF_MASK);
619 cfg |= S5P_CIWDOFST_OFF_EN |
620 S5P_CIWDOFST_HOROFF(f->offs_h) |
621 S5P_CIWDOFST_VEROFF(f->offs_v);
622
623 writel(cfg, fimc->regs + S5P_CIWDOFST);
624
625 /* See CIWDOFSTn register description in the datasheet for details. */
626 hoff2 = f->o_width - f->width - f->offs_h;
627 voff2 = f->o_height - f->height - f->offs_v;
628 cfg = S5P_CIWDOFST2_HOROFF(hoff2) | S5P_CIWDOFST2_VEROFF(voff2);
629
630 writel(cfg, fimc->regs + S5P_CIWDOFST2);
631 return 0;
632}
633
634int fimc_hw_set_camera_type(struct fimc_dev *fimc,
Sylwester Nawrockidf7e09a2010-12-27 14:42:15 -0300635 struct s5p_fimc_isp_info *cam)
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300636{
637 u32 cfg, tmp;
638 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
639
640 cfg = readl(fimc->regs + S5P_CIGCTRL);
641
642 /* Select ITU B interface, disable Writeback path and test pattern. */
643 cfg &= ~(S5P_CIGCTRL_TESTPAT_MASK | S5P_CIGCTRL_SELCAM_ITU_A |
644 S5P_CIGCTRL_SELCAM_MIPI | S5P_CIGCTRL_CAMIF_SELWB |
Sylwester Nawrockiee7160e2011-08-26 14:57:06 -0300645 S5P_CIGCTRL_SELCAM_MIPI_A | S5P_CIGCTRL_CAM_JPEG);
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300646
647 if (cam->bus_type == FIMC_MIPI_CSI2) {
648 cfg |= S5P_CIGCTRL_SELCAM_MIPI;
649
650 if (cam->mux_id == 0)
651 cfg |= S5P_CIGCTRL_SELCAM_MIPI_A;
652
653 /* TODO: add remaining supported formats. */
Sylwester Nawrockiee7160e2011-08-26 14:57:06 -0300654 switch (vid_cap->mf.code) {
655 case V4L2_MBUS_FMT_VYUY8_2X8:
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300656 tmp = S5P_CSIIMGFMT_YCBCR422_8BIT;
Sylwester Nawrockiee7160e2011-08-26 14:57:06 -0300657 break;
658 case V4L2_MBUS_FMT_JPEG_1X8:
659 tmp = S5P_CSIIMGFMT_USER(1);
660 cfg |= S5P_CIGCTRL_CAM_JPEG;
661 break;
662 default:
Sylwester Nawrocki30c99392011-06-10 15:36:48 -0300663 v4l2_err(fimc->vid_cap.vfd,
664 "Not supported camera pixel format: %d",
Sylwester Nawrocki237e0262011-08-24 20:35:30 -0300665 vid_cap->mf.code);
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300666 return -EINVAL;
667 }
Sylwester Nawrockie0eec9a2011-02-21 12:09:01 -0300668 tmp |= (cam->csi_data_align == 32) << 8;
669
670 writel(tmp, fimc->regs + S5P_CSIIMGFMT);
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300671
672 } else if (cam->bus_type == FIMC_ITU_601 ||
Sylwester Nawrockie0eec9a2011-02-21 12:09:01 -0300673 cam->bus_type == FIMC_ITU_656) {
Sylwester Nawrocki5f3cc442010-10-07 10:06:16 -0300674 if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */
675 cfg |= S5P_CIGCTRL_SELCAM_ITU_A;
676 } else if (cam->bus_type == FIMC_LCD_WB) {
677 cfg |= S5P_CIGCTRL_CAMIF_SELWB;
678 } else {
679 err("invalid camera bus type selected\n");
680 return -EINVAL;
681 }
682 writel(cfg, fimc->regs + S5P_CIGCTRL);
683
684 return 0;
685}