blob: 8fcec1cc101e09be617340f8c7e91b6e004b636f [file] [log] [blame]
Heiko Stuebnera7a2b312013-06-17 22:29:23 +02001/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/smp.h>
19#include <linux/io.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
Heiko Stuebnerd003b582014-10-15 10:23:00 -070022#include <linux/regmap.h>
23#include <linux/mfd/syscon.h>
Heiko Stuebnera7a2b312013-06-17 22:29:23 +020024
Kever Yang3ee851e2014-10-15 10:23:03 -070025#include <linux/reset.h>
26#include <linux/cpu.h>
Heiko Stuebnera7a2b312013-06-17 22:29:23 +020027#include <asm/cacheflush.h>
Romain Perierf54b91f2014-07-19 13:03:26 +000028#include <asm/cp15.h>
Heiko Stuebnera7a2b312013-06-17 22:29:23 +020029#include <asm/smp_scu.h>
30#include <asm/smp_plat.h>
31#include <asm/mach/map.h>
32
33#include "core.h"
34
35static void __iomem *scu_base_addr;
36static void __iomem *sram_base_addr;
37static int ncores;
38
39#define PMU_PWRDN_CON 0x08
40#define PMU_PWRDN_ST 0x0c
41
42#define PMU_PWRDN_SCU 4
43
Heiko Stuebnerd003b582014-10-15 10:23:00 -070044static struct regmap *pmu;
Heiko Stuebnera7a2b312013-06-17 22:29:23 +020045
Heiko Stuebnerd003b582014-10-15 10:23:00 -070046static int pmu_power_domain_is_on(int pd)
Heiko Stuebnera7a2b312013-06-17 22:29:23 +020047{
Heiko Stuebnerd003b582014-10-15 10:23:00 -070048 u32 val;
49 int ret;
50
51 ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
52 if (ret < 0)
53 return ret;
54
55 return !(val & BIT(pd));
Heiko Stuebnera7a2b312013-06-17 22:29:23 +020056}
57
Krzysztof Kozlowskibd76d732015-03-02 00:12:03 +010058static struct reset_control *rockchip_get_core_reset(int cpu)
Kever Yang3ee851e2014-10-15 10:23:03 -070059{
60 struct device *dev = get_cpu_device(cpu);
61 struct device_node *np;
62
63 /* The cpu device is only available after the initial core bringup */
64 if (dev)
65 np = dev->of_node;
66 else
67 np = of_get_cpu_node(cpu, 0);
68
69 return of_reset_control_get(np, NULL);
70}
71
Heiko Stuebnerd003b582014-10-15 10:23:00 -070072static int pmu_set_power_domain(int pd, bool on)
Heiko Stuebnera7a2b312013-06-17 22:29:23 +020073{
Heiko Stuebnerd003b582014-10-15 10:23:00 -070074 u32 val = (on) ? 0 : BIT(pd);
75 int ret;
Heiko Stuebnera7a2b312013-06-17 22:29:23 +020076
Kever Yang3ee851e2014-10-15 10:23:03 -070077 /*
78 * We need to soft reset the cpu when we turn off the cpu power domain,
79 * or else the active processors might be stalled when the individual
80 * processor is powered down.
81 */
82 if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
83 struct reset_control *rstc = rockchip_get_core_reset(pd);
84
85 if (IS_ERR(rstc)) {
86 pr_err("%s: could not get reset control for core %d\n",
87 __func__, pd);
88 return PTR_ERR(rstc);
89 }
90
91 if (on)
92 reset_control_deassert(rstc);
93 else
94 reset_control_assert(rstc);
95
96 reset_control_put(rstc);
97 }
98
Heiko Stuebnerd003b582014-10-15 10:23:00 -070099 ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
100 if (ret < 0) {
101 pr_err("%s: could not update power domain\n", __func__);
102 return ret;
103 }
104
105 ret = -1;
106 while (ret != on) {
107 ret = pmu_power_domain_is_on(pd);
108 if (ret < 0) {
109 pr_err("%s: could not read power domain state\n",
110 __func__);
111 return ret;
112 }
113 }
114
115 return 0;
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200116}
117
118/*
119 * Handling of CPU cores
120 */
121
Paul Gortmaker374d4dd2015-01-17 16:48:41 -0500122static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200123{
Kever Yang3ee851e2014-10-15 10:23:03 -0700124 int ret;
125
Heiko Stuebnerd003b582014-10-15 10:23:00 -0700126 if (!sram_base_addr || !pmu) {
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200127 pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
128 return -ENXIO;
129 }
130
131 if (cpu >= ncores) {
132 pr_err("%s: cpu %d outside maximum number of cpus %d\n",
133 __func__, cpu, ncores);
134 return -ENXIO;
135 }
136
137 /* start the core */
Kever Yang3ee851e2014-10-15 10:23:03 -0700138 ret = pmu_set_power_domain(0 + cpu, true);
139 if (ret < 0)
140 return ret;
141
142 if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
143 /* We communicate with the bootrom to active the cpus other
144 * than cpu0, after a blob of initialize code, they will
145 * stay at wfe state, once they are actived, they will check
146 * the mailbox:
147 * sram_base_addr + 4: 0xdeadbeaf
148 * sram_base_addr + 8: start address for pc
149 * */
150 udelay(10);
Russell King02b4e272015-05-19 17:06:44 +0100151 writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
Kever Yang3ee851e2014-10-15 10:23:03 -0700152 writel(0xDEADBEAF, sram_base_addr + 4);
153 dsb_sev();
154 }
155
156 return 0;
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200157}
158
159/**
160 * rockchip_smp_prepare_sram - populate necessary sram block
161 * Starting cores execute the code residing at the start of the on-chip sram
162 * after power-on. Therefore make sure, this sram region is reserved and
163 * big enough. After this check, copy the trampoline code that directs the
164 * core to the real startup code in ram into the sram-region.
165 * @node: mmio-sram device node
166 */
167static int __init rockchip_smp_prepare_sram(struct device_node *node)
168{
169 unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
170 &rockchip_secondary_trampoline;
171 struct resource res;
172 unsigned int rsize;
173 int ret;
174
175 ret = of_address_to_resource(node, 0, &res);
176 if (ret < 0) {
177 pr_err("%s: could not get address for node %s\n",
178 __func__, node->full_name);
179 return ret;
180 }
181
182 rsize = resource_size(&res);
183 if (rsize < trampoline_sz) {
184 pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
185 __func__, rsize, trampoline_sz);
186 return -EINVAL;
187 }
188
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200189 /* set the boot function for the sram code */
Russell King02b4e272015-05-19 17:06:44 +0100190 rockchip_boot_fn = virt_to_phys(secondary_startup);
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200191
192 /* copy the trampoline to sram, that runs during startup of the core */
193 memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
194 flush_cache_all();
195 outer_clean_range(0, trampoline_sz);
196
197 dsb_sev();
198
199 return 0;
200}
201
Krzysztof Kozlowskibd76d732015-03-02 00:12:03 +0100202static const struct regmap_config rockchip_pmu_regmap_config = {
Heiko Stuebnerd003b582014-10-15 10:23:00 -0700203 .reg_bits = 32,
204 .val_bits = 32,
205 .reg_stride = 4,
206};
207
208static int __init rockchip_smp_prepare_pmu(void)
209{
210 struct device_node *node;
211 void __iomem *pmu_base;
212
Heiko Stuebner6de2d212014-10-15 10:23:01 -0700213 /*
214 * This function is only called via smp_ops->smp_prepare_cpu().
215 * That only happens if a "/cpus" device tree node exists
216 * and has an "enable-method" property that selects the SMP
217 * operations defined herein.
218 */
219 node = of_find_node_by_path("/cpus");
220
221 pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
222 of_node_put(node);
223 if (!IS_ERR(pmu))
224 return 0;
225
Heiko Stuebnerd003b582014-10-15 10:23:00 -0700226 pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
227 if (!IS_ERR(pmu))
228 return 0;
229
230 /* fallback, create our own regmap for the pmu area */
231 pmu = NULL;
232 node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
233 if (!node) {
234 pr_err("%s: could not find pmu dt node\n", __func__);
235 return -ENODEV;
236 }
237
238 pmu_base = of_iomap(node, 0);
239 if (!pmu_base) {
240 pr_err("%s: could not map pmu registers\n", __func__);
241 return -ENOMEM;
242 }
243
244 pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
245 if (IS_ERR(pmu)) {
246 int ret = PTR_ERR(pmu);
247
248 iounmap(pmu_base);
249 pmu = NULL;
250 pr_err("%s: regmap init failed\n", __func__);
251 return ret;
252 }
253
254 return 0;
255}
256
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200257static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
258{
259 struct device_node *node;
260 unsigned int i;
261
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200262 node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
263 if (!node) {
264 pr_err("%s: could not find sram dt node\n", __func__);
265 return;
266 }
267
Kever Yang3ee851e2014-10-15 10:23:03 -0700268 sram_base_addr = of_iomap(node, 0);
269 if (!sram_base_addr) {
270 pr_err("%s: could not map sram registers\n", __func__);
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200271 return;
Kever Yang3ee851e2014-10-15 10:23:03 -0700272 }
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200273
Heiko Stuebnerd003b582014-10-15 10:23:00 -0700274 if (rockchip_smp_prepare_pmu())
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200275 return;
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200276
Kever Yang3ee851e2014-10-15 10:23:03 -0700277 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
278 if (rockchip_smp_prepare_sram(node))
279 return;
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200280
Kever Yang3ee851e2014-10-15 10:23:03 -0700281 /* enable the SCU power domain */
282 pmu_set_power_domain(PMU_PWRDN_SCU, true);
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200283
Kever Yang3ee851e2014-10-15 10:23:03 -0700284 node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
285 if (!node) {
286 pr_err("%s: missing scu\n", __func__);
287 return;
288 }
289
290 scu_base_addr = of_iomap(node, 0);
291 if (!scu_base_addr) {
292 pr_err("%s: could not map scu registers\n", __func__);
293 return;
294 }
295
296 /*
297 * While the number of cpus is gathered from dt, also get the
298 * number of cores from the scu to verify this value when
299 * booting the cores.
300 */
301 ncores = scu_get_core_count(scu_base_addr);
302 pr_err("%s: ncores %d\n", __func__, ncores);
303
304 scu_enable(scu_base_addr);
305 } else {
306 unsigned int l2ctlr;
307
308 asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
309 ncores = ((l2ctlr >> 24) & 0x3) + 1;
310 }
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200311
312 /* Make sure that all cores except the first are really off */
313 for (i = 1; i < ncores; i++)
314 pmu_set_power_domain(0 + i, false);
315}
316
Romain Perierf54b91f2014-07-19 13:03:26 +0000317#ifdef CONFIG_HOTPLUG_CPU
318static int rockchip_cpu_kill(unsigned int cpu)
319{
320 pmu_set_power_domain(0 + cpu, false);
321 return 1;
322}
323
324static void rockchip_cpu_die(unsigned int cpu)
325{
326 v7_exit_coherency_flush(louis);
327 while(1)
328 cpu_do_idle();
329}
330#endif
331
Heiko Stübner26ab69c2014-03-27 01:06:32 +0100332static struct smp_operations rockchip_smp_ops __initdata = {
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200333 .smp_prepare_cpus = rockchip_smp_prepare_cpus,
334 .smp_boot_secondary = rockchip_boot_secondary,
Romain Perierf54b91f2014-07-19 13:03:26 +0000335#ifdef CONFIG_HOTPLUG_CPU
336 .cpu_kill = rockchip_cpu_kill,
337 .cpu_die = rockchip_cpu_die,
338#endif
Heiko Stuebnera7a2b312013-06-17 22:29:23 +0200339};
Heiko Stübner26ab69c2014-03-27 01:06:32 +0100340CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);