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Marcus Folkesson2e62c492018-03-16 16:14:11 +01001/* SPDX-License-Identifier: GPL-2.0+ */
Russell Kinga09e64f2008-08-05 16:14:15 +01002/*
Jean-Christophe Plagniol-Villarde7b39142011-07-15 01:52:05 +02003 * drivers/watchdog/at91sam9_wdt.h
Russell Kinga09e64f2008-08-05 16:14:15 +01004 *
Andrew Victor3d73e892008-09-18 21:44:20 +01005 * Copyright (C) 2007 Andrew Victor
6 * Copyright (C) 2007 Atmel Corporation.
7 *
Russell Kinga09e64f2008-08-05 16:14:15 +01008 * Watchdog Timer (WDT) - System peripherals regsters.
9 * Based on AT91SAM9261 datasheet revision D.
10 *
Russell Kinga09e64f2008-08-05 16:14:15 +010011 */
12
13#ifndef AT91_WDT_H
14#define AT91_WDT_H
15
Jean-Christophe PLAGNIOL-VILLARDc1c30a22011-11-02 01:43:31 +080016#define AT91_WDT_CR 0x00 /* Watchdog Control Register */
Russell Kinga09e64f2008-08-05 16:14:15 +010017#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
18#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */
19
Jean-Christophe PLAGNIOL-VILLARDc1c30a22011-11-02 01:43:31 +080020#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
Russell Kinga09e64f2008-08-05 16:14:15 +010021#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
Wenyou Yang76534862015-08-06 18:16:46 +080022#define AT91_WDT_SET_WDV(x) ((x) & AT91_WDT_WDV)
Russell Kinga09e64f2008-08-05 16:14:15 +010023#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
24#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
25#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
26#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
27#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
Wenyou Yang76534862015-08-06 18:16:46 +080028#define AT91_WDT_SET_WDD(x) (((x) << 16) & AT91_WDT_WDD)
Russell Kinga09e64f2008-08-05 16:14:15 +010029#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
30#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
31
Jean-Christophe PLAGNIOL-VILLARDc1c30a22011-11-02 01:43:31 +080032#define AT91_WDT_SR 0x08 /* Watchdog Status Register */
Russell Kinga09e64f2008-08-05 16:14:15 +010033#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
34#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
35
36#endif