blob: 38ae56f17916b69ad6a530796eccadd1f7f10492 [file] [log] [blame]
Shawn Guofba311f2010-12-18 21:39:31 +08001/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/gpio.h>
Shawn Guo8d7cf832011-06-06 09:37:58 -060028#include <linux/platform_device.h>
29#include <linux/slab.h>
Shawn Guo06f88a82011-06-06 22:31:29 +080030#include <linux/basic_mmio_gpio.h>
Paul Gortmakerbb207ef2011-07-03 13:38:09 -040031#include <linux/module.h>
Shawn Guofba311f2010-12-18 21:39:31 +080032
Shawn Guo8d7cf832011-06-06 09:37:58 -060033#define MXS_SET 0x4
34#define MXS_CLR 0x8
Shawn Guofba311f2010-12-18 21:39:31 +080035
Shawn Guo164387d2012-05-03 23:32:52 +080036#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
37#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
38#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
39#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
40#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
41#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
42#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
43#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
Shawn Guofba311f2010-12-18 21:39:31 +080044
45#define GPIO_INT_FALL_EDGE 0x0
46#define GPIO_INT_LOW_LEV 0x1
47#define GPIO_INT_RISE_EDGE 0x2
48#define GPIO_INT_HIGH_LEV 0x3
49#define GPIO_INT_LEV_MASK (1 << 0)
50#define GPIO_INT_POL_MASK (1 << 1)
51
Shawn Guo7e6c53a2011-08-14 00:14:06 +080052#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START)
53
Shawn Guo164387d2012-05-03 23:32:52 +080054enum mxs_gpio_id {
55 IMX23_GPIO,
56 IMX28_GPIO,
57};
58
Grant Likely7b2fa572011-06-06 09:37:58 -060059struct mxs_gpio_port {
60 void __iomem *base;
61 int id;
62 int irq;
Grant Likely7b2fa572011-06-06 09:37:58 -060063 int virtual_irq_start;
Shawn Guo06f88a82011-06-06 22:31:29 +080064 struct bgpio_chip bgc;
Shawn Guo164387d2012-05-03 23:32:52 +080065 enum mxs_gpio_id devid;
Grant Likely7b2fa572011-06-06 09:37:58 -060066};
67
Shawn Guo164387d2012-05-03 23:32:52 +080068static inline int is_imx23_gpio(struct mxs_gpio_port *port)
69{
70 return port->devid == IMX23_GPIO;
71}
72
73static inline int is_imx28_gpio(struct mxs_gpio_port *port)
74{
75 return port->devid == IMX28_GPIO;
76}
77
Shawn Guofba311f2010-12-18 21:39:31 +080078/* Note: This driver assumes 32 GPIOs are handled in one register */
79
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010080static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
Shawn Guofba311f2010-12-18 21:39:31 +080081{
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010082 u32 gpio = irq_to_gpio(d->irq);
Shawn Guofba311f2010-12-18 21:39:31 +080083 u32 pin_mask = 1 << (gpio & 31);
Shawn Guo498c17c2011-06-07 22:00:54 +080084 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
85 struct mxs_gpio_port *port = gc->private;
Shawn Guofba311f2010-12-18 21:39:31 +080086 void __iomem *pin_addr;
87 int edge;
88
89 switch (type) {
90 case IRQ_TYPE_EDGE_RISING:
91 edge = GPIO_INT_RISE_EDGE;
92 break;
93 case IRQ_TYPE_EDGE_FALLING:
94 edge = GPIO_INT_FALL_EDGE;
95 break;
96 case IRQ_TYPE_LEVEL_LOW:
97 edge = GPIO_INT_LOW_LEV;
98 break;
99 case IRQ_TYPE_LEVEL_HIGH:
100 edge = GPIO_INT_HIGH_LEV;
101 break;
102 default:
103 return -EINVAL;
104 }
105
106 /* set level or edge */
Shawn Guo164387d2012-05-03 23:32:52 +0800107 pin_addr = port->base + PINCTRL_IRQLEV(port);
Shawn Guofba311f2010-12-18 21:39:31 +0800108 if (edge & GPIO_INT_LEV_MASK)
Shawn Guo8d7cf832011-06-06 09:37:58 -0600109 writel(pin_mask, pin_addr + MXS_SET);
Shawn Guofba311f2010-12-18 21:39:31 +0800110 else
Shawn Guo8d7cf832011-06-06 09:37:58 -0600111 writel(pin_mask, pin_addr + MXS_CLR);
Shawn Guofba311f2010-12-18 21:39:31 +0800112
113 /* set polarity */
Shawn Guo164387d2012-05-03 23:32:52 +0800114 pin_addr = port->base + PINCTRL_IRQPOL(port);
Shawn Guofba311f2010-12-18 21:39:31 +0800115 if (edge & GPIO_INT_POL_MASK)
Shawn Guo8d7cf832011-06-06 09:37:58 -0600116 writel(pin_mask, pin_addr + MXS_SET);
Shawn Guofba311f2010-12-18 21:39:31 +0800117 else
Shawn Guo8d7cf832011-06-06 09:37:58 -0600118 writel(pin_mask, pin_addr + MXS_CLR);
Shawn Guofba311f2010-12-18 21:39:31 +0800119
Shawn Guo498c17c2011-06-07 22:00:54 +0800120 writel(1 << (gpio & 0x1f),
Shawn Guo164387d2012-05-03 23:32:52 +0800121 port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
Shawn Guofba311f2010-12-18 21:39:31 +0800122
123 return 0;
124}
125
126/* MXS has one interrupt *per* gpio port */
127static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
128{
129 u32 irq_stat;
Shawn Guo8d7cf832011-06-06 09:37:58 -0600130 struct mxs_gpio_port *port = irq_get_handler_data(irq);
Shawn Guofba311f2010-12-18 21:39:31 +0800131 u32 gpio_irq_no_base = port->virtual_irq_start;
132
Uwe Kleine-König1f6b5dd2011-01-25 16:54:22 +0100133 desc->irq_data.chip->irq_ack(&desc->irq_data);
134
Shawn Guo164387d2012-05-03 23:32:52 +0800135 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
136 readl(port->base + PINCTRL_IRQEN(port));
Shawn Guofba311f2010-12-18 21:39:31 +0800137
138 while (irq_stat != 0) {
139 int irqoffset = fls(irq_stat) - 1;
140 generic_handle_irq(gpio_irq_no_base + irqoffset);
141 irq_stat &= ~(1 << irqoffset);
142 }
143}
144
145/*
146 * Set interrupt number "irq" in the GPIO as a wake-up source.
147 * While system is running, all registered GPIO interrupts need to have
148 * wake-up enabled. When system is suspended, only selected GPIO interrupts
149 * need to have wake-up enabled.
150 * @param irq interrupt source number
151 * @param enable enable as wake-up if equal to non-zero
152 * @return This function returns 0 on success.
153 */
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +0100154static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
Shawn Guofba311f2010-12-18 21:39:31 +0800155{
Shawn Guo498c17c2011-06-07 22:00:54 +0800156 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
157 struct mxs_gpio_port *port = gc->private;
Shawn Guofba311f2010-12-18 21:39:31 +0800158
Shawn Guo61617152011-06-07 22:00:53 +0800159 if (enable)
160 enable_irq_wake(port->irq);
161 else
162 disable_irq_wake(port->irq);
Shawn Guofba311f2010-12-18 21:39:31 +0800163
164 return 0;
165}
166
Shawn Guo498c17c2011-06-07 22:00:54 +0800167static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
168{
169 struct irq_chip_generic *gc;
170 struct irq_chip_type *ct;
171
172 gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
173 port->base, handle_level_irq);
174 gc->private = port;
175
176 ct = gc->chip_types;
Shawn Guo591567a2011-07-19 21:16:56 +0800177 ct->chip.irq_ack = irq_gc_ack_set_bit;
Shawn Guo498c17c2011-06-07 22:00:54 +0800178 ct->chip.irq_mask = irq_gc_mask_clr_bit;
179 ct->chip.irq_unmask = irq_gc_mask_set_bit;
180 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
Shawn Guo591567a2011-07-19 21:16:56 +0800181 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
Shawn Guo164387d2012-05-03 23:32:52 +0800182 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
183 ct->regs.mask = PINCTRL_IRQEN(port);
Shawn Guo498c17c2011-06-07 22:00:54 +0800184
185 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
186}
Shawn Guofba311f2010-12-18 21:39:31 +0800187
Shawn Guo06f88a82011-06-06 22:31:29 +0800188static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
Shawn Guofba311f2010-12-18 21:39:31 +0800189{
Shawn Guo06f88a82011-06-06 22:31:29 +0800190 struct bgpio_chip *bgc = to_bgpio_chip(gc);
Shawn Guofba311f2010-12-18 21:39:31 +0800191 struct mxs_gpio_port *port =
Shawn Guo06f88a82011-06-06 22:31:29 +0800192 container_of(bgc, struct mxs_gpio_port, bgc);
Shawn Guofba311f2010-12-18 21:39:31 +0800193
194 return port->virtual_irq_start + offset;
195}
196
Shawn Guo164387d2012-05-03 23:32:52 +0800197static struct platform_device_id mxs_gpio_ids[] = {
198 {
199 .name = "imx23-gpio",
200 .driver_data = IMX23_GPIO,
201 }, {
202 .name = "imx28-gpio",
203 .driver_data = IMX28_GPIO,
204 }, {
205 /* sentinel */
206 }
207};
208MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
209
Shawn Guo8d7cf832011-06-06 09:37:58 -0600210static int __devinit mxs_gpio_probe(struct platform_device *pdev)
Shawn Guofba311f2010-12-18 21:39:31 +0800211{
Shawn Guo8d7cf832011-06-06 09:37:58 -0600212 static void __iomem *base;
213 struct mxs_gpio_port *port;
214 struct resource *iores = NULL;
Shawn Guo498c17c2011-06-07 22:00:54 +0800215 int err;
Shawn Guofba311f2010-12-18 21:39:31 +0800216
Shawn Guo940a4f72012-05-04 10:30:14 +0800217 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
Shawn Guo8d7cf832011-06-06 09:37:58 -0600218 if (!port)
219 return -ENOMEM;
Shawn Guofba311f2010-12-18 21:39:31 +0800220
Shawn Guo8d7cf832011-06-06 09:37:58 -0600221 port->id = pdev->id;
Shawn Guo164387d2012-05-03 23:32:52 +0800222 port->devid = pdev->id_entry->driver_data;
Shawn Guo8d7cf832011-06-06 09:37:58 -0600223 port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
Shawn Guofba311f2010-12-18 21:39:31 +0800224
Shawn Guo940a4f72012-05-04 10:30:14 +0800225 port->irq = platform_get_irq(pdev, 0);
226 if (port->irq < 0)
227 return port->irq;
228
Shawn Guo8d7cf832011-06-06 09:37:58 -0600229 /*
230 * map memory region only once, as all the gpio ports
231 * share the same one
232 */
233 if (!base) {
234 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Shawn Guo940a4f72012-05-04 10:30:14 +0800235 base = devm_request_and_ioremap(&pdev->dev, iores);
236 if (!base)
237 return -EADDRNOTAVAIL;
Shawn Guofba311f2010-12-18 21:39:31 +0800238 }
Shawn Guo8d7cf832011-06-06 09:37:58 -0600239 port->base = base;
240
Shawn Guo498c17c2011-06-07 22:00:54 +0800241 /*
242 * select the pin interrupt functionality but initially
243 * disable the interrupts
244 */
Shawn Guo164387d2012-05-03 23:32:52 +0800245 writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
246 writel(0, port->base + PINCTRL_IRQEN(port));
Shawn Guo8d7cf832011-06-06 09:37:58 -0600247
248 /* clear address has to be used to clear IRQSTAT bits */
Shawn Guo164387d2012-05-03 23:32:52 +0800249 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
Shawn Guo8d7cf832011-06-06 09:37:58 -0600250
Shawn Guo498c17c2011-06-07 22:00:54 +0800251 /* gpio-mxs can be a generic irq chip */
252 mxs_gpio_init_gc(port);
Shawn Guo8d7cf832011-06-06 09:37:58 -0600253
254 /* setup one handler for each entry */
255 irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
256 irq_set_handler_data(port->irq, port);
257
Shawn Guo06f88a82011-06-06 22:31:29 +0800258 err = bgpio_init(&port->bgc, &pdev->dev, 4,
Shawn Guo164387d2012-05-03 23:32:52 +0800259 port->base + PINCTRL_DIN(port),
260 port->base + PINCTRL_DOUT(port), NULL,
261 port->base + PINCTRL_DOE(port), NULL, false);
Shawn Guo8d7cf832011-06-06 09:37:58 -0600262 if (err)
Shawn Guo940a4f72012-05-04 10:30:14 +0800263 return err;
Shawn Guofba311f2010-12-18 21:39:31 +0800264
Shawn Guo06f88a82011-06-06 22:31:29 +0800265 port->bgc.gc.to_irq = mxs_gpio_to_irq;
266 port->bgc.gc.base = port->id * 32;
267
268 err = gpiochip_add(&port->bgc.gc);
Shawn Guo940a4f72012-05-04 10:30:14 +0800269 if (err) {
270 bgpio_remove(&port->bgc);
271 return err;
272 }
Shawn Guo06f88a82011-06-06 22:31:29 +0800273
Shawn Guofba311f2010-12-18 21:39:31 +0800274 return 0;
275}
276
Shawn Guo8d7cf832011-06-06 09:37:58 -0600277static struct platform_driver mxs_gpio_driver = {
278 .driver = {
279 .name = "gpio-mxs",
280 .owner = THIS_MODULE,
281 },
282 .probe = mxs_gpio_probe,
Shawn Guo164387d2012-05-03 23:32:52 +0800283 .id_table = mxs_gpio_ids,
Shawn Guofba311f2010-12-18 21:39:31 +0800284};
Sascha Haueref196602011-01-24 12:57:46 +0100285
Shawn Guo8d7cf832011-06-06 09:37:58 -0600286static int __init mxs_gpio_init(void)
Sascha Haueref196602011-01-24 12:57:46 +0100287{
Shawn Guo8d7cf832011-06-06 09:37:58 -0600288 return platform_driver_register(&mxs_gpio_driver);
Sascha Haueref196602011-01-24 12:57:46 +0100289}
Shawn Guo8d7cf832011-06-06 09:37:58 -0600290postcore_initcall(mxs_gpio_init);
Shawn Guofba311f2010-12-18 21:39:31 +0800291
Shawn Guo8d7cf832011-06-06 09:37:58 -0600292MODULE_AUTHOR("Freescale Semiconductor, "
293 "Daniel Mack <danielncaiaq.de>, "
294 "Juergen Beisert <kernel@pengutronix.de>");
295MODULE_DESCRIPTION("Freescale MXS GPIO");
296MODULE_LICENSE("GPL");