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Wolfram Sang95f25ef2010-10-15 12:21:04 +02001/*
2 * Freescale eSDHC i.MX controller driver for the platform bus.
3 *
4 * derived from the OF-version.
5 *
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/clk.h>
Wolfram Sang0c6d49c2011-02-26 14:44:39 +010018#include <linux/gpio.h>
Shawn Guo66506f72011-08-15 10:28:18 +080019#include <linux/module.h>
Richard Zhue1498602011-03-25 09:18:27 -040020#include <linux/slab.h>
Wolfram Sang95f25ef2010-10-15 12:21:04 +020021#include <linux/mmc/host.h>
Richard Zhu58ac8172011-03-21 13:22:16 +080022#include <linux/mmc/mmc.h>
23#include <linux/mmc/sdio.h>
Shawn Guofbe5fdd2012-12-11 22:32:20 +080024#include <linux/mmc/slot-gpio.h>
Shawn Guoabfafc22011-06-30 15:44:44 +080025#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/of_gpio.h>
Dong Aishenge62d8b82012-05-11 14:56:01 +080028#include <linux/pinctrl/consumer.h>
Arnd Bergmann82906b12012-08-24 15:14:29 +020029#include <linux/platform_data/mmc-esdhc-imx.h>
Dong Aisheng89d7e5c2013-11-04 16:38:29 +080030#include <linux/pm_runtime.h>
Wolfram Sang95f25ef2010-10-15 12:21:04 +020031#include "sdhci-pltfm.h"
32#include "sdhci-esdhc.h"
33
Shawn Guo60bf6392013-01-15 23:36:53 +080034#define ESDHC_CTRL_D3CD 0x08
Richard Zhu58ac8172011-03-21 13:22:16 +080035/* VENDOR SPEC register */
Shawn Guo60bf6392013-01-15 23:36:53 +080036#define ESDHC_VENDOR_SPEC 0xc0
37#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
Dong Aisheng03221912013-09-13 19:11:34 +080038#define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
Dong Aishengfed2f6e2013-09-13 19:11:33 +080039#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
Shawn Guo60bf6392013-01-15 23:36:53 +080040#define ESDHC_WTMK_LVL 0x44
41#define ESDHC_MIX_CTRL 0x48
Dong Aishengde5bdbf2013-10-18 19:48:46 +080042#define ESDHC_MIX_CTRL_DDREN (1 << 3)
Shawn Guo2a15f982013-01-21 19:02:26 +080043#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
Dong Aisheng03221912013-09-13 19:11:34 +080044#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
45#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
46#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
Shawn Guo2a15f982013-01-21 19:02:26 +080047/* Bits 3 and 6 are not SDHCI standard definitions */
48#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
Dong Aishengd131a712013-11-04 16:38:26 +080049/* Tuning bits */
50#define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
Richard Zhu58ac8172011-03-21 13:22:16 +080051
Dong Aisheng602519b2013-10-18 19:48:47 +080052/* dll control register */
53#define ESDHC_DLL_CTRL 0x60
54#define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
55#define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
56
Dong Aisheng03221912013-09-13 19:11:34 +080057/* tune control register */
58#define ESDHC_TUNE_CTRL_STATUS 0x68
59#define ESDHC_TUNE_CTRL_STEP 1
60#define ESDHC_TUNE_CTRL_MIN 0
61#define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
62
Dong Aisheng6e9fd282013-10-18 19:48:43 +080063#define ESDHC_TUNING_CTRL 0xcc
64#define ESDHC_STD_TUNING_EN (1 << 24)
65/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
66#define ESDHC_TUNING_START_TAP 0x1
67
Dong Aisheng03221912013-09-13 19:11:34 +080068#define ESDHC_TUNING_BLOCK_PATTERN_LEN 64
69
Dong Aishengad932202013-09-13 19:11:35 +080070/* pinctrl state */
71#define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
72#define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
73
Richard Zhu58ac8172011-03-21 13:22:16 +080074/*
Sascha Haueraf510792013-01-21 19:02:28 +080075 * Our interpretation of the SDHCI_HOST_CONTROL register
76 */
77#define ESDHC_CTRL_4BITBUS (0x1 << 1)
78#define ESDHC_CTRL_8BITBUS (0x2 << 1)
79#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
80
81/*
Richard Zhu97e4ba62011-08-11 16:51:46 -040082 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
83 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
84 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
85 * Define this macro DMA error INT for fsl eSDHC
86 */
Shawn Guo60bf6392013-01-15 23:36:53 +080087#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
Richard Zhu97e4ba62011-08-11 16:51:46 -040088
89/*
Richard Zhu58ac8172011-03-21 13:22:16 +080090 * The CMDTYPE of the CMD register (offset 0xE) should be set to
91 * "11" when the STOP CMD12 is issued on imx53 to abort one
92 * open ended multi-blk IO. Otherwise the TC INT wouldn't
93 * be generated.
94 * In exact block transfer, the controller doesn't complete the
95 * operations automatically as required at the end of the
96 * transfer and remains on hold if the abort command is not sent.
97 * As a result, the TC flag is not asserted and SW received timeout
98 * exeception. Bit1 of Vendor Spec registor is used to fix it.
99 */
Shawn Guo31fbb302013-10-17 15:19:44 +0800100#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
101/*
102 * The flag enables the workaround for ESDHC errata ENGcm07207 which
103 * affects i.MX25 and i.MX35.
104 */
105#define ESDHC_FLAG_ENGCM07207 BIT(2)
Shawn Guo9d61c002013-10-17 15:19:45 +0800106/*
107 * The flag tells that the ESDHC controller is an USDHC block that is
108 * integrated on the i.MX6 series.
109 */
110#define ESDHC_FLAG_USDHC BIT(3)
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800111/* The IP supports manual tuning process */
112#define ESDHC_FLAG_MAN_TUNING BIT(4)
113/* The IP supports standard tuning process */
114#define ESDHC_FLAG_STD_TUNING BIT(5)
115/* The IP has SDHCI_CAPABILITIES_1 register */
116#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
Richard Zhue1498602011-03-25 09:18:27 -0400117
Shawn Guof47c4bb2013-10-17 15:19:47 +0800118struct esdhc_soc_data {
119 u32 flags;
120};
121
122static struct esdhc_soc_data esdhc_imx25_data = {
123 .flags = ESDHC_FLAG_ENGCM07207,
124};
125
126static struct esdhc_soc_data esdhc_imx35_data = {
127 .flags = ESDHC_FLAG_ENGCM07207,
128};
129
130static struct esdhc_soc_data esdhc_imx51_data = {
131 .flags = 0,
132};
133
134static struct esdhc_soc_data esdhc_imx53_data = {
135 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
136};
137
138static struct esdhc_soc_data usdhc_imx6q_data = {
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800139 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
140};
141
142static struct esdhc_soc_data usdhc_imx6sl_data = {
143 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
144 | ESDHC_FLAG_HAVE_CAP1,
Shawn Guo57ed3312011-06-30 09:24:26 +0800145};
146
Richard Zhue1498602011-03-25 09:18:27 -0400147struct pltfm_imx_data {
Richard Zhue1498602011-03-25 09:18:27 -0400148 u32 scratchpad;
Dong Aishenge62d8b82012-05-11 14:56:01 +0800149 struct pinctrl *pinctrl;
Dong Aishengad932202013-09-13 19:11:35 +0800150 struct pinctrl_state *pins_default;
151 struct pinctrl_state *pins_100mhz;
152 struct pinctrl_state *pins_200mhz;
Shawn Guof47c4bb2013-10-17 15:19:47 +0800153 const struct esdhc_soc_data *socdata;
Shawn Guo842afc02011-07-06 22:57:48 +0800154 struct esdhc_platform_data boarddata;
Sascha Hauer52dac612012-03-07 09:31:34 +0100155 struct clk *clk_ipg;
156 struct clk *clk_ahb;
157 struct clk *clk_per;
Lucas Stach361b8482013-03-15 09:49:26 +0100158 enum {
159 NO_CMD_PENDING, /* no multiblock command pending*/
160 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
161 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
162 } multiblock_status;
Dong Aisheng03221912013-09-13 19:11:34 +0800163 u32 uhs_mode;
Dong Aishengde5bdbf2013-10-18 19:48:46 +0800164 u32 is_ddr;
Richard Zhue1498602011-03-25 09:18:27 -0400165};
166
Shawn Guo57ed3312011-06-30 09:24:26 +0800167static struct platform_device_id imx_esdhc_devtype[] = {
168 {
169 .name = "sdhci-esdhc-imx25",
Shawn Guof47c4bb2013-10-17 15:19:47 +0800170 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
Shawn Guo57ed3312011-06-30 09:24:26 +0800171 }, {
172 .name = "sdhci-esdhc-imx35",
Shawn Guof47c4bb2013-10-17 15:19:47 +0800173 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
Shawn Guo57ed3312011-06-30 09:24:26 +0800174 }, {
175 .name = "sdhci-esdhc-imx51",
Shawn Guof47c4bb2013-10-17 15:19:47 +0800176 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
Shawn Guo57ed3312011-06-30 09:24:26 +0800177 }, {
Shawn Guo57ed3312011-06-30 09:24:26 +0800178 /* sentinel */
179 }
180};
181MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
182
Shawn Guoabfafc22011-06-30 15:44:44 +0800183static const struct of_device_id imx_esdhc_dt_ids[] = {
Shawn Guof47c4bb2013-10-17 15:19:47 +0800184 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
185 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
186 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
187 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800188 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
Shawn Guof47c4bb2013-10-17 15:19:47 +0800189 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
Shawn Guoabfafc22011-06-30 15:44:44 +0800190 { /* sentinel */ }
191};
192MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
193
Shawn Guo57ed3312011-06-30 09:24:26 +0800194static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
195{
Shawn Guof47c4bb2013-10-17 15:19:47 +0800196 return data->socdata == &esdhc_imx25_data;
Shawn Guo57ed3312011-06-30 09:24:26 +0800197}
198
199static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
200{
Shawn Guof47c4bb2013-10-17 15:19:47 +0800201 return data->socdata == &esdhc_imx53_data;
Shawn Guo57ed3312011-06-30 09:24:26 +0800202}
203
Shawn Guo95a24822011-09-19 17:32:21 +0800204static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
205{
Shawn Guof47c4bb2013-10-17 15:19:47 +0800206 return data->socdata == &usdhc_imx6q_data;
Shawn Guo95a24822011-09-19 17:32:21 +0800207}
208
Shawn Guo9d61c002013-10-17 15:19:45 +0800209static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
210{
Shawn Guof47c4bb2013-10-17 15:19:47 +0800211 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
Shawn Guo9d61c002013-10-17 15:19:45 +0800212}
213
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200214static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
215{
216 void __iomem *base = host->ioaddr + (reg & ~0x3);
217 u32 shift = (reg & 0x3) * 8;
218
219 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
220}
221
Wolfram Sang7e29c302011-02-26 14:44:41 +0100222static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
223{
Lucas Stach361b8482013-03-15 09:49:26 +0100224 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
225 struct pltfm_imx_data *imx_data = pltfm_host->priv;
Wolfram Sang7e29c302011-02-26 14:44:41 +0100226 u32 val = readl(host->ioaddr + reg);
227
Dong Aisheng03221912013-09-13 19:11:34 +0800228 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
229 u32 fsl_prss = val;
230 /* save the least 20 bits */
231 val = fsl_prss & 0x000FFFFF;
232 /* move dat[0-3] bits */
233 val |= (fsl_prss & 0x0F000000) >> 4;
234 /* move cmd line bit */
235 val |= (fsl_prss & 0x00800000) << 1;
236 }
237
Richard Zhu97e4ba62011-08-11 16:51:46 -0400238 if (unlikely(reg == SDHCI_CAPABILITIES)) {
Dong Aisheng6b4fb672013-10-18 19:48:44 +0800239 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
240 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
241 val &= 0xffff0000;
242
Richard Zhu97e4ba62011-08-11 16:51:46 -0400243 /* In FSL esdhc IC module, only bit20 is used to indicate the
244 * ADMA2 capability of esdhc, but this bit is messed up on
245 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
246 * don't actually support ADMA2). So set the BROKEN_ADMA
247 * uirk on MX25/35 platforms.
248 */
249
250 if (val & SDHCI_CAN_DO_ADMA1) {
251 val &= ~SDHCI_CAN_DO_ADMA1;
252 val |= SDHCI_CAN_DO_ADMA2;
253 }
254 }
255
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800256 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
257 if (esdhc_is_usdhc(imx_data)) {
258 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
259 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
260 else
261 /* imx6q/dl does not have cap_1 register, fake one */
262 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
Dong Aisheng888824b2013-10-18 19:48:48 +0800263 | SDHCI_SUPPORT_SDR50
264 | SDHCI_USE_SDR50_TUNING;
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800265 }
266 }
Dong Aisheng03221912013-09-13 19:11:34 +0800267
Shawn Guo9d61c002013-10-17 15:19:45 +0800268 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
Dong Aisheng03221912013-09-13 19:11:34 +0800269 val = 0;
270 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
271 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
272 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
273 }
274
Richard Zhu97e4ba62011-08-11 16:51:46 -0400275 if (unlikely(reg == SDHCI_INT_STATUS)) {
Shawn Guo60bf6392013-01-15 23:36:53 +0800276 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
277 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
Richard Zhu97e4ba62011-08-11 16:51:46 -0400278 val |= SDHCI_INT_ADMA_ERROR;
279 }
Lucas Stach361b8482013-03-15 09:49:26 +0100280
281 /*
282 * mask off the interrupt we get in response to the manually
283 * sent CMD12
284 */
285 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
286 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
287 val &= ~SDHCI_INT_RESPONSE;
288 writel(SDHCI_INT_RESPONSE, host->ioaddr +
289 SDHCI_INT_STATUS);
290 imx_data->multiblock_status = NO_CMD_PENDING;
291 }
Richard Zhu97e4ba62011-08-11 16:51:46 -0400292 }
293
Wolfram Sang7e29c302011-02-26 14:44:41 +0100294 return val;
295}
296
297static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
298{
Richard Zhue1498602011-03-25 09:18:27 -0400299 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
300 struct pltfm_imx_data *imx_data = pltfm_host->priv;
Tony Lin0d588642011-08-11 16:45:59 -0400301 u32 data;
Richard Zhue1498602011-03-25 09:18:27 -0400302
Tony Lin0d588642011-08-11 16:45:59 -0400303 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
Tony Lin0d588642011-08-11 16:45:59 -0400304 if (val & SDHCI_INT_CARD_INT) {
305 /*
306 * Clear and then set D3CD bit to avoid missing the
307 * card interrupt. This is a eSDHC controller problem
308 * so we need to apply the following workaround: clear
309 * and set D3CD bit will make eSDHC re-sample the card
310 * interrupt. In case a card interrupt was lost,
311 * re-sample it by the following steps.
312 */
313 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
Shawn Guo60bf6392013-01-15 23:36:53 +0800314 data &= ~ESDHC_CTRL_D3CD;
Tony Lin0d588642011-08-11 16:45:59 -0400315 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
Shawn Guo60bf6392013-01-15 23:36:53 +0800316 data |= ESDHC_CTRL_D3CD;
Tony Lin0d588642011-08-11 16:45:59 -0400317 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
318 }
319 }
Wolfram Sang7e29c302011-02-26 14:44:41 +0100320
Shawn Guof47c4bb2013-10-17 15:19:47 +0800321 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
Richard Zhu58ac8172011-03-21 13:22:16 +0800322 && (reg == SDHCI_INT_STATUS)
323 && (val & SDHCI_INT_DATA_END))) {
324 u32 v;
Shawn Guo60bf6392013-01-15 23:36:53 +0800325 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
326 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
327 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
Lucas Stach361b8482013-03-15 09:49:26 +0100328
329 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
330 {
331 /* send a manual CMD12 with RESPTYP=none */
332 data = MMC_STOP_TRANSMISSION << 24 |
333 SDHCI_CMD_ABORTCMD << 16;
334 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
335 imx_data->multiblock_status = WAIT_FOR_INT;
336 }
Richard Zhu58ac8172011-03-21 13:22:16 +0800337 }
338
Richard Zhu97e4ba62011-08-11 16:51:46 -0400339 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
340 if (val & SDHCI_INT_ADMA_ERROR) {
341 val &= ~SDHCI_INT_ADMA_ERROR;
Shawn Guo60bf6392013-01-15 23:36:53 +0800342 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
Richard Zhu97e4ba62011-08-11 16:51:46 -0400343 }
344 }
345
Wolfram Sang7e29c302011-02-26 14:44:41 +0100346 writel(val, host->ioaddr + reg);
347}
348
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200349static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
350{
Shawn Guoef4d0882013-01-15 23:30:27 +0800351 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
352 struct pltfm_imx_data *imx_data = pltfm_host->priv;
Dong Aisheng03221912013-09-13 19:11:34 +0800353 u16 ret = 0;
354 u32 val;
Shawn Guoef4d0882013-01-15 23:30:27 +0800355
Shawn Guo95a24822011-09-19 17:32:21 +0800356 if (unlikely(reg == SDHCI_HOST_VERSION)) {
Shawn Guoef4d0882013-01-15 23:30:27 +0800357 reg ^= 2;
Shawn Guo9d61c002013-10-17 15:19:45 +0800358 if (esdhc_is_usdhc(imx_data)) {
Shawn Guoef4d0882013-01-15 23:30:27 +0800359 /*
360 * The usdhc register returns a wrong host version.
361 * Correct it here.
362 */
363 return SDHCI_SPEC_300;
364 }
Shawn Guo95a24822011-09-19 17:32:21 +0800365 }
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200366
Dong Aisheng03221912013-09-13 19:11:34 +0800367 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
368 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
369 if (val & ESDHC_VENDOR_SPEC_VSELECT)
370 ret |= SDHCI_CTRL_VDD_180;
371
Shawn Guo9d61c002013-10-17 15:19:45 +0800372 if (esdhc_is_usdhc(imx_data)) {
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800373 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
374 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
375 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
376 /* the std tuning bits is in ACMD12_ERR for imx6sl */
377 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
Dong Aisheng03221912013-09-13 19:11:34 +0800378 }
379
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800380 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
381 ret |= SDHCI_CTRL_EXEC_TUNING;
382 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
383 ret |= SDHCI_CTRL_TUNED_CLK;
384
Dong Aisheng03221912013-09-13 19:11:34 +0800385 ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK);
386 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
387
388 return ret;
389 }
390
Dong Aisheng7dd109e2013-10-30 22:09:49 +0800391 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
392 if (esdhc_is_usdhc(imx_data)) {
393 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
394 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
395 /* Swap AC23 bit */
396 if (m & ESDHC_MIX_CTRL_AC23EN) {
397 ret &= ~ESDHC_MIX_CTRL_AC23EN;
398 ret |= SDHCI_TRNS_AUTO_CMD23;
399 }
400 } else {
401 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
402 }
403
404 return ret;
405 }
406
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200407 return readw(host->ioaddr + reg);
408}
409
410static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
411{
412 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Richard Zhue1498602011-03-25 09:18:27 -0400413 struct pltfm_imx_data *imx_data = pltfm_host->priv;
Dong Aisheng03221912013-09-13 19:11:34 +0800414 u32 new_val = 0;
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200415
416 switch (reg) {
Dong Aisheng03221912013-09-13 19:11:34 +0800417 case SDHCI_CLOCK_CONTROL:
418 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
419 if (val & SDHCI_CLOCK_CARD_EN)
420 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
421 else
422 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
423 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
424 return;
425 case SDHCI_HOST_CONTROL2:
426 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
427 if (val & SDHCI_CTRL_VDD_180)
428 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
429 else
430 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
431 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
432 imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK;
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800433 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
434 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
435 if (val & SDHCI_CTRL_TUNED_CLK)
436 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
437 else
438 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
439 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
440 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
441 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
442 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
Dong Aisheng8b2bb0ad2013-11-04 16:38:27 +0800443 if (val & SDHCI_CTRL_TUNED_CLK) {
444 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800445 } else {
Dong Aisheng8b2bb0ad2013-11-04 16:38:27 +0800446 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800447 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
448 }
449
Dong Aisheng8b2bb0ad2013-11-04 16:38:27 +0800450 if (val & SDHCI_CTRL_EXEC_TUNING) {
451 v |= ESDHC_MIX_CTRL_EXE_TUNE;
452 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
453 } else {
454 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
455 }
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800456
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800457 writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
458 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
459 }
Dong Aisheng03221912013-09-13 19:11:34 +0800460 return;
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200461 case SDHCI_TRANSFER_MODE:
Shawn Guof47c4bb2013-10-17 15:19:47 +0800462 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
Richard Zhu58ac8172011-03-21 13:22:16 +0800463 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
464 && (host->cmd->data->blocks > 1)
465 && (host->cmd->data->flags & MMC_DATA_READ)) {
466 u32 v;
Shawn Guo60bf6392013-01-15 23:36:53 +0800467 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
468 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
469 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
Richard Zhu58ac8172011-03-21 13:22:16 +0800470 }
Shawn Guo69f54692013-01-21 19:02:24 +0800471
Shawn Guo9d61c002013-10-17 15:19:45 +0800472 if (esdhc_is_usdhc(imx_data)) {
Shawn Guo69f54692013-01-21 19:02:24 +0800473 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
Shawn Guo2a15f982013-01-21 19:02:26 +0800474 /* Swap AC23 bit */
475 if (val & SDHCI_TRNS_AUTO_CMD23) {
476 val &= ~SDHCI_TRNS_AUTO_CMD23;
477 val |= ESDHC_MIX_CTRL_AC23EN;
478 }
479 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
Shawn Guo69f54692013-01-21 19:02:24 +0800480 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
481 } else {
482 /*
483 * Postpone this write, we must do it together with a
484 * command write that is down below.
485 */
486 imx_data->scratchpad = val;
487 }
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200488 return;
489 case SDHCI_COMMAND:
Lucas Stach361b8482013-03-15 09:49:26 +0100490 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
Richard Zhu58ac8172011-03-21 13:22:16 +0800491 val |= SDHCI_CMD_ABORTCMD;
Shawn Guo95a24822011-09-19 17:32:21 +0800492
Lucas Stach361b8482013-03-15 09:49:26 +0100493 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
Shawn Guof47c4bb2013-10-17 15:19:47 +0800494 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
Lucas Stach361b8482013-03-15 09:49:26 +0100495 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
496
Shawn Guo9d61c002013-10-17 15:19:45 +0800497 if (esdhc_is_usdhc(imx_data))
Shawn Guo95a24822011-09-19 17:32:21 +0800498 writel(val << 16,
499 host->ioaddr + SDHCI_TRANSFER_MODE);
Shawn Guo69f54692013-01-21 19:02:24 +0800500 else
Shawn Guo95a24822011-09-19 17:32:21 +0800501 writel(val << 16 | imx_data->scratchpad,
502 host->ioaddr + SDHCI_TRANSFER_MODE);
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200503 return;
504 case SDHCI_BLOCK_SIZE:
505 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
506 break;
507 }
508 esdhc_clrset_le(host, 0xffff, val, reg);
509}
510
511static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
512{
Wilson Callan9a0985b2012-07-19 02:49:16 -0400513 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
514 struct pltfm_imx_data *imx_data = pltfm_host->priv;
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200515 u32 new_val;
Sascha Haueraf510792013-01-21 19:02:28 +0800516 u32 mask;
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200517
518 switch (reg) {
519 case SDHCI_POWER_CONTROL:
520 /*
521 * FSL put some DMA bits here
522 * If your board has a regulator, code should be here
523 */
524 return;
525 case SDHCI_HOST_CONTROL:
Shawn Guo6b40d182013-01-15 23:36:52 +0800526 /* FSL messed up here, so we need to manually compose it. */
Sascha Haueraf510792013-01-21 19:02:28 +0800527 new_val = val & SDHCI_CTRL_LED;
Masanari Iida7122bbb2012-08-05 23:25:40 +0900528 /* ensure the endianness */
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200529 new_val |= ESDHC_HOST_CONTROL_LE;
Wilson Callan9a0985b2012-07-19 02:49:16 -0400530 /* bits 8&9 are reserved on mx25 */
531 if (!is_imx25_esdhc(imx_data)) {
532 /* DMA mode bits are shifted */
533 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
534 }
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200535
Sascha Haueraf510792013-01-21 19:02:28 +0800536 /*
537 * Do not touch buswidth bits here. This is done in
538 * esdhc_pltfm_bus_width.
Martin Fuzzeyf6825742013-04-15 17:08:35 +0200539 * Do not touch the D3CD bit either which is used for the
540 * SDIO interrupt errata workaround.
Sascha Haueraf510792013-01-21 19:02:28 +0800541 */
Martin Fuzzeyf6825742013-04-15 17:08:35 +0200542 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
Sascha Haueraf510792013-01-21 19:02:28 +0800543
544 esdhc_clrset_le(host, mask, new_val, reg);
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200545 return;
546 }
547 esdhc_clrset_le(host, 0xff, val, reg);
Shawn Guo913413c2011-06-21 22:41:51 +0800548
549 /*
550 * The esdhc has a design violation to SDHC spec which tells
551 * that software reset should not affect card detection circuit.
552 * But esdhc clears its SYSCTL register bits [0..2] during the
553 * software reset. This will stop those clocks that card detection
554 * circuit relies on. To work around it, we turn the clocks on back
555 * to keep card detection circuit functional.
556 */
Shawn Guo58c8c4f2013-01-21 19:02:25 +0800557 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
Shawn Guo913413c2011-06-21 22:41:51 +0800558 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
Shawn Guo58c8c4f2013-01-21 19:02:25 +0800559 /*
560 * The reset on usdhc fails to clear MIX_CTRL register.
561 * Do it manually here.
562 */
Dong Aishengde5bdbf2013-10-18 19:48:46 +0800563 if (esdhc_is_usdhc(imx_data)) {
Dong Aishengd131a712013-11-04 16:38:26 +0800564 /* the tuning bits should be kept during reset */
565 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
566 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
567 host->ioaddr + ESDHC_MIX_CTRL);
Dong Aishengde5bdbf2013-10-18 19:48:46 +0800568 imx_data->is_ddr = 0;
569 }
Shawn Guo58c8c4f2013-01-21 19:02:25 +0800570 }
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200571}
572
Lucas Stach0ddf03c2013-06-05 15:13:26 +0200573static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
574{
575 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
576 struct pltfm_imx_data *imx_data = pltfm_host->priv;
577 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
578
Dong Aishenga9748622013-12-26 15:23:53 +0800579 if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock))
Lucas Stach0ddf03c2013-06-05 15:13:26 +0200580 return boarddata->f_max;
581 else
Dong Aishenga9748622013-12-26 15:23:53 +0800582 return pltfm_host->clock;
Lucas Stach0ddf03c2013-06-05 15:13:26 +0200583}
584
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200585static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
586{
587 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
588
Dong Aishenga9748622013-12-26 15:23:53 +0800589 return pltfm_host->clock / 256 / 16;
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200590}
591
Lucas Stach8ba95802013-06-05 15:13:25 +0200592static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
593 unsigned int clock)
594{
595 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800596 struct pltfm_imx_data *imx_data = pltfm_host->priv;
Dong Aishenga9748622013-12-26 15:23:53 +0800597 unsigned int host_clock = pltfm_host->clock;
Dong Aishengd31fc002013-09-13 19:11:32 +0800598 int pre_div = 2;
599 int div = 1;
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800600 u32 temp, val;
Lucas Stach8ba95802013-06-05 15:13:25 +0200601
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800602 if (clock == 0) {
Russell King1650d0c2014-04-25 12:58:50 +0100603 host->mmc->actual_clock = 0;
604
Shawn Guo9d61c002013-10-17 15:19:45 +0800605 if (esdhc_is_usdhc(imx_data)) {
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800606 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
607 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
608 host->ioaddr + ESDHC_VENDOR_SPEC);
609 }
Russell King373073e2014-04-25 12:58:45 +0100610 return;
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800611 }
Dong Aishengd31fc002013-09-13 19:11:32 +0800612
Dong Aishengde5bdbf2013-10-18 19:48:46 +0800613 if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
Dong Aisheng5f7886c2013-09-13 19:11:36 +0800614 pre_div = 1;
615
Dong Aishengd31fc002013-09-13 19:11:32 +0800616 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
617 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
618 | ESDHC_CLOCK_MASK);
619 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
620
621 while (host_clock / pre_div / 16 > clock && pre_div < 256)
622 pre_div *= 2;
623
624 while (host_clock / pre_div / div > clock && div < 16)
625 div++;
626
Dong Aishenge76b8552013-09-13 19:11:37 +0800627 host->mmc->actual_clock = host_clock / pre_div / div;
Dong Aishengd31fc002013-09-13 19:11:32 +0800628 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
Dong Aishenge76b8552013-09-13 19:11:37 +0800629 clock, host->mmc->actual_clock);
Dong Aishengd31fc002013-09-13 19:11:32 +0800630
Dong Aishengde5bdbf2013-10-18 19:48:46 +0800631 if (imx_data->is_ddr)
632 pre_div >>= 2;
633 else
634 pre_div >>= 1;
Dong Aishengd31fc002013-09-13 19:11:32 +0800635 div--;
636
637 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
638 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
639 | (div << ESDHC_DIVIDER_SHIFT)
640 | (pre_div << ESDHC_PREDIV_SHIFT));
641 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800642
Shawn Guo9d61c002013-10-17 15:19:45 +0800643 if (esdhc_is_usdhc(imx_data)) {
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800644 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
645 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
646 host->ioaddr + ESDHC_VENDOR_SPEC);
647 }
648
Dong Aishengd31fc002013-09-13 19:11:32 +0800649 mdelay(1);
Lucas Stach8ba95802013-06-05 15:13:25 +0200650}
651
Shawn Guo913413c2011-06-21 22:41:51 +0800652static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
653{
Shawn Guo842afc02011-07-06 22:57:48 +0800654 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
655 struct pltfm_imx_data *imx_data = pltfm_host->priv;
656 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
Shawn Guo913413c2011-06-21 22:41:51 +0800657
658 switch (boarddata->wp_type) {
659 case ESDHC_WP_GPIO:
Shawn Guofbe5fdd2012-12-11 22:32:20 +0800660 return mmc_gpio_get_ro(host->mmc);
Shawn Guo913413c2011-06-21 22:41:51 +0800661 case ESDHC_WP_CONTROLLER:
662 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
663 SDHCI_WRITE_PROTECT);
664 case ESDHC_WP_NONE:
665 break;
666 }
667
668 return -ENOSYS;
669}
670
Russell King2317f562014-04-25 12:57:07 +0100671static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
Sascha Haueraf510792013-01-21 19:02:28 +0800672{
673 u32 ctrl;
674
675 switch (width) {
676 case MMC_BUS_WIDTH_8:
677 ctrl = ESDHC_CTRL_8BITBUS;
678 break;
679 case MMC_BUS_WIDTH_4:
680 ctrl = ESDHC_CTRL_4BITBUS;
681 break;
682 default:
683 ctrl = 0;
684 break;
685 }
686
687 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
688 SDHCI_HOST_CONTROL);
Sascha Haueraf510792013-01-21 19:02:28 +0800689}
690
Dong Aisheng03221912013-09-13 19:11:34 +0800691static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
692{
693 u32 reg;
694
695 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
696 mdelay(1);
697
Dong Aishengce090a42013-11-04 16:38:28 +0800698 pm_runtime_get_sync(host->mmc->parent);
Dong Aisheng03221912013-09-13 19:11:34 +0800699 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
700 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
701 ESDHC_MIX_CTRL_FBCLK_SEL;
702 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
703 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
704 dev_dbg(mmc_dev(host->mmc),
705 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
706 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
707}
708
709static void esdhc_request_done(struct mmc_request *mrq)
710{
711 complete(&mrq->completion);
712}
713
714static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode)
715{
716 struct mmc_command cmd = {0};
Fabio Estevama50145f2013-10-04 22:59:23 -0300717 struct mmc_request mrq = {NULL};
Dong Aisheng03221912013-09-13 19:11:34 +0800718 struct mmc_data data = {0};
719 struct scatterlist sg;
720 char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN];
721
722 cmd.opcode = opcode;
723 cmd.arg = 0;
724 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
725
726 data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN;
727 data.blocks = 1;
728 data.flags = MMC_DATA_READ;
729 data.sg = &sg;
730 data.sg_len = 1;
731
732 sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern));
733
734 mrq.cmd = &cmd;
735 mrq.cmd->mrq = &mrq;
736 mrq.data = &data;
737 mrq.data->mrq = &mrq;
738 mrq.cmd->data = mrq.data;
739
740 mrq.done = esdhc_request_done;
741 init_completion(&(mrq.completion));
742
743 disable_irq(host->irq);
744 spin_lock(&host->lock);
745 host->mrq = &mrq;
746
747 sdhci_send_command(host, mrq.cmd);
748
749 spin_unlock(&host->lock);
750 enable_irq(host->irq);
751
752 wait_for_completion(&mrq.completion);
753
754 if (cmd.error)
755 return cmd.error;
756 if (data.error)
757 return data.error;
758
759 return 0;
760}
761
762static void esdhc_post_tuning(struct sdhci_host *host)
763{
764 u32 reg;
765
766 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
767 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
768 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
769}
770
771static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
772{
773 int min, max, avg, ret;
774
775 /* find the mininum delay first which can pass tuning */
776 min = ESDHC_TUNE_CTRL_MIN;
777 while (min < ESDHC_TUNE_CTRL_MAX) {
778 esdhc_prepare_tuning(host, min);
779 if (!esdhc_send_tuning_cmd(host, opcode))
780 break;
781 min += ESDHC_TUNE_CTRL_STEP;
782 }
783
784 /* find the maxinum delay which can not pass tuning */
785 max = min + ESDHC_TUNE_CTRL_STEP;
786 while (max < ESDHC_TUNE_CTRL_MAX) {
787 esdhc_prepare_tuning(host, max);
788 if (esdhc_send_tuning_cmd(host, opcode)) {
789 max -= ESDHC_TUNE_CTRL_STEP;
790 break;
791 }
792 max += ESDHC_TUNE_CTRL_STEP;
793 }
794
795 /* use average delay to get the best timing */
796 avg = (min + max) / 2;
797 esdhc_prepare_tuning(host, avg);
798 ret = esdhc_send_tuning_cmd(host, opcode);
799 esdhc_post_tuning(host);
800
801 dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
802 ret ? "failed" : "passed", avg, ret);
803
804 return ret;
805}
806
Dong Aishengad932202013-09-13 19:11:35 +0800807static int esdhc_change_pinstate(struct sdhci_host *host,
808 unsigned int uhs)
809{
810 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
811 struct pltfm_imx_data *imx_data = pltfm_host->priv;
812 struct pinctrl_state *pinctrl;
813
814 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
815
816 if (IS_ERR(imx_data->pinctrl) ||
817 IS_ERR(imx_data->pins_default) ||
818 IS_ERR(imx_data->pins_100mhz) ||
819 IS_ERR(imx_data->pins_200mhz))
820 return -EINVAL;
821
822 switch (uhs) {
823 case MMC_TIMING_UHS_SDR50:
824 pinctrl = imx_data->pins_100mhz;
825 break;
826 case MMC_TIMING_UHS_SDR104:
Dong Aisheng429a5b42013-10-30 22:10:42 +0800827 case MMC_TIMING_MMC_HS200:
Dong Aishengad932202013-09-13 19:11:35 +0800828 pinctrl = imx_data->pins_200mhz;
829 break;
830 default:
831 /* back to default state for other legacy timing */
832 pinctrl = imx_data->pins_default;
833 }
834
835 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
836}
837
838static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
839{
840 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
841 struct pltfm_imx_data *imx_data = pltfm_host->priv;
Dong Aisheng602519b2013-10-18 19:48:47 +0800842 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
Dong Aishengad932202013-09-13 19:11:35 +0800843
844 switch (uhs) {
845 case MMC_TIMING_UHS_SDR12:
846 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12;
847 break;
848 case MMC_TIMING_UHS_SDR25:
849 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25;
850 break;
851 case MMC_TIMING_UHS_SDR50:
852 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50;
853 break;
854 case MMC_TIMING_UHS_SDR104:
Dong Aisheng429a5b42013-10-30 22:10:42 +0800855 case MMC_TIMING_MMC_HS200:
Dong Aishengad932202013-09-13 19:11:35 +0800856 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104;
857 break;
858 case MMC_TIMING_UHS_DDR50:
859 imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50;
Dong Aishengde5bdbf2013-10-18 19:48:46 +0800860 writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
861 ESDHC_MIX_CTRL_DDREN,
862 host->ioaddr + ESDHC_MIX_CTRL);
863 imx_data->is_ddr = 1;
Dong Aisheng602519b2013-10-18 19:48:47 +0800864 if (boarddata->delay_line) {
865 u32 v;
866 v = boarddata->delay_line <<
867 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
868 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
869 if (is_imx53_esdhc(imx_data))
870 v <<= 1;
871 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
872 }
Dong Aishengad932202013-09-13 19:11:35 +0800873 break;
874 }
875
876 return esdhc_change_pinstate(host, uhs);
877}
878
Russell King0718e592014-04-25 12:57:18 +0100879static void esdhc_reset(struct sdhci_host *host, u8 mask)
880{
881 sdhci_reset(host, mask);
882
883 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
884 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
885}
886
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800887static struct sdhci_ops sdhci_esdhc_ops = {
Richard Zhue1498602011-03-25 09:18:27 -0400888 .read_l = esdhc_readl_le,
Wolfram Sang0c6d49c2011-02-26 14:44:39 +0100889 .read_w = esdhc_readw_le,
Richard Zhue1498602011-03-25 09:18:27 -0400890 .write_l = esdhc_writel_le,
Wolfram Sang0c6d49c2011-02-26 14:44:39 +0100891 .write_w = esdhc_writew_le,
892 .write_b = esdhc_writeb_le,
Lucas Stach8ba95802013-06-05 15:13:25 +0200893 .set_clock = esdhc_pltfm_set_clock,
Lucas Stach0ddf03c2013-06-05 15:13:26 +0200894 .get_max_clock = esdhc_pltfm_get_max_clock,
Wolfram Sang0c6d49c2011-02-26 14:44:39 +0100895 .get_min_clock = esdhc_pltfm_get_min_clock,
Shawn Guo913413c2011-06-21 22:41:51 +0800896 .get_ro = esdhc_pltfm_get_ro,
Russell King2317f562014-04-25 12:57:07 +0100897 .set_bus_width = esdhc_pltfm_set_bus_width,
Dong Aishengad932202013-09-13 19:11:35 +0800898 .set_uhs_signaling = esdhc_set_uhs_signaling,
Russell King0718e592014-04-25 12:57:18 +0100899 .reset = esdhc_reset,
Wolfram Sang0c6d49c2011-02-26 14:44:39 +0100900};
901
Lars-Peter Clausen1db5eeb2013-03-13 19:26:03 +0100902static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
Richard Zhu97e4ba62011-08-11 16:51:46 -0400903 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
904 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
905 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
Shawn Guo85d65092011-05-27 23:48:12 +0800906 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
Shawn Guo85d65092011-05-27 23:48:12 +0800907 .ops = &sdhci_esdhc_ops,
908};
909
Shawn Guoabfafc22011-06-30 15:44:44 +0800910#ifdef CONFIG_OF
Bill Pembertonc3be1ef2012-11-19 13:23:06 -0500911static int
Shawn Guoabfafc22011-06-30 15:44:44 +0800912sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
913 struct esdhc_platform_data *boarddata)
914{
915 struct device_node *np = pdev->dev.of_node;
916
917 if (!np)
918 return -ENODEV;
919
Arnd Bergmann7f217792012-05-13 00:14:24 -0400920 if (of_get_property(np, "non-removable", NULL))
Shawn Guoabfafc22011-06-30 15:44:44 +0800921 boarddata->cd_type = ESDHC_CD_PERMANENT;
922
923 if (of_get_property(np, "fsl,cd-controller", NULL))
924 boarddata->cd_type = ESDHC_CD_CONTROLLER;
925
926 if (of_get_property(np, "fsl,wp-controller", NULL))
927 boarddata->wp_type = ESDHC_WP_CONTROLLER;
928
929 boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
930 if (gpio_is_valid(boarddata->cd_gpio))
931 boarddata->cd_type = ESDHC_CD_GPIO;
932
933 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
934 if (gpio_is_valid(boarddata->wp_gpio))
935 boarddata->wp_type = ESDHC_WP_GPIO;
936
Sascha Haueraf510792013-01-21 19:02:28 +0800937 of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
938
Lucas Stach0ddf03c2013-06-05 15:13:26 +0200939 of_property_read_u32(np, "max-frequency", &boarddata->f_max);
940
Dong Aishengad932202013-09-13 19:11:35 +0800941 if (of_find_property(np, "no-1-8-v", NULL))
942 boarddata->support_vsel = false;
943 else
944 boarddata->support_vsel = true;
945
Dong Aisheng602519b2013-10-18 19:48:47 +0800946 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
947 boarddata->delay_line = 0;
948
Shawn Guoabfafc22011-06-30 15:44:44 +0800949 return 0;
950}
951#else
952static inline int
953sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
954 struct esdhc_platform_data *boarddata)
955{
956 return -ENODEV;
957}
958#endif
959
Bill Pembertonc3be1ef2012-11-19 13:23:06 -0500960static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200961{
Shawn Guoabfafc22011-06-30 15:44:44 +0800962 const struct of_device_id *of_id =
963 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
Shawn Guo85d65092011-05-27 23:48:12 +0800964 struct sdhci_pltfm_host *pltfm_host;
965 struct sdhci_host *host;
966 struct esdhc_platform_data *boarddata;
Wolfram Sang0c6d49c2011-02-26 14:44:39 +0100967 int err;
Richard Zhue1498602011-03-25 09:18:27 -0400968 struct pltfm_imx_data *imx_data;
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200969
Christian Daudt0e748232013-05-29 13:50:05 -0700970 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
Shawn Guo85d65092011-05-27 23:48:12 +0800971 if (IS_ERR(host))
972 return PTR_ERR(host);
973
974 pltfm_host = sdhci_priv(host);
975
Shawn Guoe3af31c2012-11-26 14:39:43 +0800976 imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
Shawn Guoabfafc22011-06-30 15:44:44 +0800977 if (!imx_data) {
978 err = -ENOMEM;
Shawn Guoe3af31c2012-11-26 14:39:43 +0800979 goto free_sdhci;
Shawn Guoabfafc22011-06-30 15:44:44 +0800980 }
Shawn Guo57ed3312011-06-30 09:24:26 +0800981
Shawn Guof47c4bb2013-10-17 15:19:47 +0800982 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
983 pdev->id_entry->driver_data;
Shawn Guo85d65092011-05-27 23:48:12 +0800984 pltfm_host->priv = imx_data;
985
Sascha Hauer52dac612012-03-07 09:31:34 +0100986 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
987 if (IS_ERR(imx_data->clk_ipg)) {
988 err = PTR_ERR(imx_data->clk_ipg);
Shawn Guoe3af31c2012-11-26 14:39:43 +0800989 goto free_sdhci;
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200990 }
Sascha Hauer52dac612012-03-07 09:31:34 +0100991
992 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
993 if (IS_ERR(imx_data->clk_ahb)) {
994 err = PTR_ERR(imx_data->clk_ahb);
Shawn Guoe3af31c2012-11-26 14:39:43 +0800995 goto free_sdhci;
Sascha Hauer52dac612012-03-07 09:31:34 +0100996 }
997
998 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
999 if (IS_ERR(imx_data->clk_per)) {
1000 err = PTR_ERR(imx_data->clk_per);
Shawn Guoe3af31c2012-11-26 14:39:43 +08001001 goto free_sdhci;
Sascha Hauer52dac612012-03-07 09:31:34 +01001002 }
1003
1004 pltfm_host->clk = imx_data->clk_per;
Dong Aishenga9748622013-12-26 15:23:53 +08001005 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
Sascha Hauer52dac612012-03-07 09:31:34 +01001006 clk_prepare_enable(imx_data->clk_per);
1007 clk_prepare_enable(imx_data->clk_ipg);
1008 clk_prepare_enable(imx_data->clk_ahb);
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001009
Dong Aishengad932202013-09-13 19:11:35 +08001010 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
Dong Aishenge62d8b82012-05-11 14:56:01 +08001011 if (IS_ERR(imx_data->pinctrl)) {
1012 err = PTR_ERR(imx_data->pinctrl);
Shawn Guoe3af31c2012-11-26 14:39:43 +08001013 goto disable_clk;
Dong Aishenge62d8b82012-05-11 14:56:01 +08001014 }
1015
Dong Aishengad932202013-09-13 19:11:35 +08001016 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1017 PINCTRL_STATE_DEFAULT);
1018 if (IS_ERR(imx_data->pins_default)) {
1019 err = PTR_ERR(imx_data->pins_default);
1020 dev_err(mmc_dev(host->mmc), "could not get default state\n");
1021 goto disable_clk;
1022 }
1023
Eric Bénardb89152822012-04-18 02:30:20 +02001024 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
Eric Bénard37865fe2010-10-23 01:57:21 +02001025
Shawn Guof47c4bb2013-10-17 15:19:47 +08001026 if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
Wolfram Sang0c6d49c2011-02-26 14:44:39 +01001027 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
Richard Zhu97e4ba62011-08-11 16:51:46 -04001028 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1029 | SDHCI_QUIRK_BROKEN_ADMA;
Wolfram Sang0c6d49c2011-02-26 14:44:39 +01001030
Shawn Guof750ba92011-11-10 16:39:32 +08001031 /*
1032 * The imx6q ROM code will change the default watermark level setting
1033 * to something insane. Change it back here.
1034 */
Dong Aisheng69ed60e2013-10-18 19:48:49 +08001035 if (esdhc_is_usdhc(imx_data)) {
Shawn Guo60bf6392013-01-15 23:36:53 +08001036 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
Dong Aisheng69ed60e2013-10-18 19:48:49 +08001037 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
Dong Aishenge2997c92013-10-30 22:09:52 +08001038 host->mmc->caps |= MMC_CAP_1_8V_DDR;
Dong Aisheng69ed60e2013-10-18 19:48:49 +08001039 }
Shawn Guof750ba92011-11-10 16:39:32 +08001040
Dong Aisheng6e9fd282013-10-18 19:48:43 +08001041 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1042 sdhci_esdhc_ops.platform_execute_tuning =
1043 esdhc_executing_tuning;
Dong Aisheng8b2bb0ad2013-11-04 16:38:27 +08001044
1045 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1046 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1047 ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1048 host->ioaddr + ESDHC_TUNING_CTRL);
1049
Shawn Guo842afc02011-07-06 22:57:48 +08001050 boarddata = &imx_data->boarddata;
Shawn Guoabfafc22011-06-30 15:44:44 +08001051 if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
1052 if (!host->mmc->parent->platform_data) {
1053 dev_err(mmc_dev(host->mmc), "no board data!\n");
1054 err = -EINVAL;
Shawn Guoe3af31c2012-11-26 14:39:43 +08001055 goto disable_clk;
Shawn Guoabfafc22011-06-30 15:44:44 +08001056 }
1057 imx_data->boarddata = *((struct esdhc_platform_data *)
1058 host->mmc->parent->platform_data);
1059 }
Shawn Guo913413c2011-06-21 22:41:51 +08001060
1061 /* write_protect */
1062 if (boarddata->wp_type == ESDHC_WP_GPIO) {
Shawn Guofbe5fdd2012-12-11 22:32:20 +08001063 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
Wolfram Sang0c6d49c2011-02-26 14:44:39 +01001064 if (err) {
Shawn Guofbe5fdd2012-12-11 22:32:20 +08001065 dev_err(mmc_dev(host->mmc),
1066 "failed to request write-protect gpio!\n");
1067 goto disable_clk;
Wolfram Sang0c6d49c2011-02-26 14:44:39 +01001068 }
Shawn Guofbe5fdd2012-12-11 22:32:20 +08001069 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
Shawn Guo913413c2011-06-21 22:41:51 +08001070 }
Wolfram Sang7e29c302011-02-26 14:44:41 +01001071
Shawn Guo913413c2011-06-21 22:41:51 +08001072 /* card_detect */
Shawn Guo913413c2011-06-21 22:41:51 +08001073 switch (boarddata->cd_type) {
1074 case ESDHC_CD_GPIO:
Laurent Pinchart214fc302013-08-08 12:38:31 +02001075 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
Wolfram Sang7e29c302011-02-26 14:44:41 +01001076 if (err) {
Shawn Guo913413c2011-06-21 22:41:51 +08001077 dev_err(mmc_dev(host->mmc),
Shawn Guofbe5fdd2012-12-11 22:32:20 +08001078 "failed to request card-detect gpio!\n");
Shawn Guoe3af31c2012-11-26 14:39:43 +08001079 goto disable_clk;
Wolfram Sang7e29c302011-02-26 14:44:41 +01001080 }
Shawn Guo913413c2011-06-21 22:41:51 +08001081 /* fall through */
Wolfram Sang7e29c302011-02-26 14:44:41 +01001082
Shawn Guo913413c2011-06-21 22:41:51 +08001083 case ESDHC_CD_CONTROLLER:
1084 /* we have a working card_detect back */
Wolfram Sang7e29c302011-02-26 14:44:41 +01001085 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
Shawn Guo913413c2011-06-21 22:41:51 +08001086 break;
1087
1088 case ESDHC_CD_PERMANENT:
Dong Aishenge5260032013-10-30 22:09:51 +08001089 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
Shawn Guo913413c2011-06-21 22:41:51 +08001090 break;
1091
1092 case ESDHC_CD_NONE:
1093 break;
Wolfram Sang0c6d49c2011-02-26 14:44:39 +01001094 }
Eric Bénard16a790b2010-10-23 01:57:22 +02001095
Sascha Haueraf510792013-01-21 19:02:28 +08001096 switch (boarddata->max_bus_width) {
1097 case 8:
1098 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1099 break;
1100 case 4:
1101 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1102 break;
1103 case 1:
1104 default:
1105 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1106 break;
1107 }
1108
Dong Aishengad932202013-09-13 19:11:35 +08001109 /* sdr50 and sdr104 needs work on 1.8v signal voltage */
Shawn Guo9d61c002013-10-17 15:19:45 +08001110 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) {
Dong Aishengad932202013-09-13 19:11:35 +08001111 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1112 ESDHC_PINCTRL_STATE_100MHZ);
1113 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1114 ESDHC_PINCTRL_STATE_200MHZ);
1115 if (IS_ERR(imx_data->pins_100mhz) ||
1116 IS_ERR(imx_data->pins_200mhz)) {
1117 dev_warn(mmc_dev(host->mmc),
1118 "could not get ultra high speed state, work on normal mode\n");
1119 /* fall back to not support uhs by specify no 1.8v quirk */
1120 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1121 }
1122 } else {
1123 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1124 }
1125
Shawn Guo85d65092011-05-27 23:48:12 +08001126 err = sdhci_add_host(host);
1127 if (err)
Shawn Guoe3af31c2012-11-26 14:39:43 +08001128 goto disable_clk;
Shawn Guo85d65092011-05-27 23:48:12 +08001129
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001130 pm_runtime_set_active(&pdev->dev);
1131 pm_runtime_enable(&pdev->dev);
1132 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1133 pm_runtime_use_autosuspend(&pdev->dev);
1134 pm_suspend_ignore_children(&pdev->dev, 1);
1135
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001136 return 0;
Wolfram Sang7e29c302011-02-26 14:44:41 +01001137
Shawn Guoe3af31c2012-11-26 14:39:43 +08001138disable_clk:
Sascha Hauer52dac612012-03-07 09:31:34 +01001139 clk_disable_unprepare(imx_data->clk_per);
1140 clk_disable_unprepare(imx_data->clk_ipg);
1141 clk_disable_unprepare(imx_data->clk_ahb);
Shawn Guoe3af31c2012-11-26 14:39:43 +08001142free_sdhci:
Shawn Guo85d65092011-05-27 23:48:12 +08001143 sdhci_pltfm_free(pdev);
1144 return err;
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001145}
1146
Bill Pemberton6e0ee712012-11-19 13:26:03 -05001147static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001148{
Shawn Guo85d65092011-05-27 23:48:12 +08001149 struct sdhci_host *host = platform_get_drvdata(pdev);
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001150 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Richard Zhue1498602011-03-25 09:18:27 -04001151 struct pltfm_imx_data *imx_data = pltfm_host->priv;
Shawn Guo85d65092011-05-27 23:48:12 +08001152 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1153
1154 sdhci_remove_host(host, dead);
Wolfram Sang0c6d49c2011-02-26 14:44:39 +01001155
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001156 pm_runtime_dont_use_autosuspend(&pdev->dev);
1157 pm_runtime_disable(&pdev->dev);
1158
Dong Aishenga7f2be92013-12-26 15:23:54 +08001159 if (!IS_ENABLED(CONFIG_PM_RUNTIME)) {
1160 clk_disable_unprepare(imx_data->clk_per);
1161 clk_disable_unprepare(imx_data->clk_ipg);
1162 clk_disable_unprepare(imx_data->clk_ahb);
1163 }
Sascha Hauer52dac612012-03-07 09:31:34 +01001164
Shawn Guo85d65092011-05-27 23:48:12 +08001165 sdhci_pltfm_free(pdev);
1166
1167 return 0;
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001168}
1169
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001170#ifdef CONFIG_PM_RUNTIME
1171static int sdhci_esdhc_runtime_suspend(struct device *dev)
1172{
1173 struct sdhci_host *host = dev_get_drvdata(dev);
1174 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1175 struct pltfm_imx_data *imx_data = pltfm_host->priv;
1176 int ret;
1177
1178 ret = sdhci_runtime_suspend_host(host);
1179
Russell Kingbe138552014-04-25 12:55:56 +01001180 if (!sdhci_sdio_irq_enabled(host)) {
1181 clk_disable_unprepare(imx_data->clk_per);
1182 clk_disable_unprepare(imx_data->clk_ipg);
1183 }
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001184 clk_disable_unprepare(imx_data->clk_ahb);
1185
1186 return ret;
1187}
1188
1189static int sdhci_esdhc_runtime_resume(struct device *dev)
1190{
1191 struct sdhci_host *host = dev_get_drvdata(dev);
1192 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1193 struct pltfm_imx_data *imx_data = pltfm_host->priv;
1194
Russell Kingbe138552014-04-25 12:55:56 +01001195 if (!sdhci_sdio_irq_enabled(host)) {
1196 clk_prepare_enable(imx_data->clk_per);
1197 clk_prepare_enable(imx_data->clk_ipg);
1198 }
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001199 clk_prepare_enable(imx_data->clk_ahb);
1200
1201 return sdhci_runtime_resume_host(host);
1202}
1203#endif
1204
1205static const struct dev_pm_ops sdhci_esdhc_pmops = {
1206 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
1207 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1208 sdhci_esdhc_runtime_resume, NULL)
1209};
1210
Shawn Guo85d65092011-05-27 23:48:12 +08001211static struct platform_driver sdhci_esdhc_imx_driver = {
1212 .driver = {
1213 .name = "sdhci-esdhc-imx",
1214 .owner = THIS_MODULE,
Shawn Guoabfafc22011-06-30 15:44:44 +08001215 .of_match_table = imx_esdhc_dt_ids,
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001216 .pm = &sdhci_esdhc_pmops,
Shawn Guo85d65092011-05-27 23:48:12 +08001217 },
Shawn Guo57ed3312011-06-30 09:24:26 +08001218 .id_table = imx_esdhc_devtype,
Shawn Guo85d65092011-05-27 23:48:12 +08001219 .probe = sdhci_esdhc_imx_probe,
Bill Pemberton0433c142012-11-19 13:20:26 -05001220 .remove = sdhci_esdhc_imx_remove,
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001221};
Shawn Guo85d65092011-05-27 23:48:12 +08001222
Axel Lind1f81a62011-11-26 12:55:43 +08001223module_platform_driver(sdhci_esdhc_imx_driver);
Shawn Guo85d65092011-05-27 23:48:12 +08001224
1225MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1226MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
1227MODULE_LICENSE("GPL v2");