Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Freescale eSDHC i.MX controller driver for the platform bus. |
| 3 | * |
| 4 | * derived from the OF-version. |
| 5 | * |
| 6 | * Copyright (c) 2010 Pengutronix e.K. |
| 7 | * Author: Wolfram Sang <w.sang@pengutronix.de> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/io.h> |
| 15 | #include <linux/delay.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/clk.h> |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 18 | #include <linux/gpio.h> |
Shawn Guo | 66506f7 | 2011-08-15 10:28:18 +0800 | [diff] [blame] | 19 | #include <linux/module.h> |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 20 | #include <linux/slab.h> |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 21 | #include <linux/mmc/host.h> |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 22 | #include <linux/mmc/mmc.h> |
| 23 | #include <linux/mmc/sdio.h> |
Shawn Guo | fbe5fdd | 2012-12-11 22:32:20 +0800 | [diff] [blame] | 24 | #include <linux/mmc/slot-gpio.h> |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 25 | #include <linux/of.h> |
| 26 | #include <linux/of_device.h> |
| 27 | #include <linux/of_gpio.h> |
Dong Aisheng | e62d8b8 | 2012-05-11 14:56:01 +0800 | [diff] [blame] | 28 | #include <linux/pinctrl/consumer.h> |
Arnd Bergmann | 82906b1 | 2012-08-24 15:14:29 +0200 | [diff] [blame] | 29 | #include <linux/platform_data/mmc-esdhc-imx.h> |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 30 | #include <linux/pm_runtime.h> |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 31 | #include "sdhci-pltfm.h" |
| 32 | #include "sdhci-esdhc.h" |
| 33 | |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 34 | #define ESDHC_CTRL_D3CD 0x08 |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 35 | /* VENDOR SPEC register */ |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 36 | #define ESDHC_VENDOR_SPEC 0xc0 |
| 37 | #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 38 | #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 39 | #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 40 | #define ESDHC_WTMK_LVL 0x44 |
| 41 | #define ESDHC_MIX_CTRL 0x48 |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 42 | #define ESDHC_MIX_CTRL_DDREN (1 << 3) |
Shawn Guo | 2a15f98 | 2013-01-21 19:02:26 +0800 | [diff] [blame] | 43 | #define ESDHC_MIX_CTRL_AC23EN (1 << 7) |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 44 | #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) |
| 45 | #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) |
| 46 | #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) |
Shawn Guo | 2a15f98 | 2013-01-21 19:02:26 +0800 | [diff] [blame] | 47 | /* Bits 3 and 6 are not SDHCI standard definitions */ |
| 48 | #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 |
Dong Aisheng | d131a71 | 2013-11-04 16:38:26 +0800 | [diff] [blame] | 49 | /* Tuning bits */ |
| 50 | #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 51 | |
Dong Aisheng | 602519b | 2013-10-18 19:48:47 +0800 | [diff] [blame] | 52 | /* dll control register */ |
| 53 | #define ESDHC_DLL_CTRL 0x60 |
| 54 | #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 |
| 55 | #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 |
| 56 | |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 57 | /* tune control register */ |
| 58 | #define ESDHC_TUNE_CTRL_STATUS 0x68 |
| 59 | #define ESDHC_TUNE_CTRL_STEP 1 |
| 60 | #define ESDHC_TUNE_CTRL_MIN 0 |
| 61 | #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) |
| 62 | |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 63 | #define ESDHC_TUNING_CTRL 0xcc |
| 64 | #define ESDHC_STD_TUNING_EN (1 << 24) |
| 65 | /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ |
| 66 | #define ESDHC_TUNING_START_TAP 0x1 |
| 67 | |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 68 | #define ESDHC_TUNING_BLOCK_PATTERN_LEN 64 |
| 69 | |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 70 | /* pinctrl state */ |
| 71 | #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" |
| 72 | #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" |
| 73 | |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 74 | /* |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 75 | * Our interpretation of the SDHCI_HOST_CONTROL register |
| 76 | */ |
| 77 | #define ESDHC_CTRL_4BITBUS (0x1 << 1) |
| 78 | #define ESDHC_CTRL_8BITBUS (0x2 << 1) |
| 79 | #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) |
| 80 | |
| 81 | /* |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 82 | * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: |
| 83 | * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, |
| 84 | * but bit28 is used as the INT DMA ERR in fsl eSDHC design. |
| 85 | * Define this macro DMA error INT for fsl eSDHC |
| 86 | */ |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 87 | #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 88 | |
| 89 | /* |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 90 | * The CMDTYPE of the CMD register (offset 0xE) should be set to |
| 91 | * "11" when the STOP CMD12 is issued on imx53 to abort one |
| 92 | * open ended multi-blk IO. Otherwise the TC INT wouldn't |
| 93 | * be generated. |
| 94 | * In exact block transfer, the controller doesn't complete the |
| 95 | * operations automatically as required at the end of the |
| 96 | * transfer and remains on hold if the abort command is not sent. |
| 97 | * As a result, the TC flag is not asserted and SW received timeout |
| 98 | * exeception. Bit1 of Vendor Spec registor is used to fix it. |
| 99 | */ |
Shawn Guo | 31fbb30 | 2013-10-17 15:19:44 +0800 | [diff] [blame] | 100 | #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) |
| 101 | /* |
| 102 | * The flag enables the workaround for ESDHC errata ENGcm07207 which |
| 103 | * affects i.MX25 and i.MX35. |
| 104 | */ |
| 105 | #define ESDHC_FLAG_ENGCM07207 BIT(2) |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 106 | /* |
| 107 | * The flag tells that the ESDHC controller is an USDHC block that is |
| 108 | * integrated on the i.MX6 series. |
| 109 | */ |
| 110 | #define ESDHC_FLAG_USDHC BIT(3) |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 111 | /* The IP supports manual tuning process */ |
| 112 | #define ESDHC_FLAG_MAN_TUNING BIT(4) |
| 113 | /* The IP supports standard tuning process */ |
| 114 | #define ESDHC_FLAG_STD_TUNING BIT(5) |
| 115 | /* The IP has SDHCI_CAPABILITIES_1 register */ |
| 116 | #define ESDHC_FLAG_HAVE_CAP1 BIT(6) |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 117 | |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 118 | struct esdhc_soc_data { |
| 119 | u32 flags; |
| 120 | }; |
| 121 | |
| 122 | static struct esdhc_soc_data esdhc_imx25_data = { |
| 123 | .flags = ESDHC_FLAG_ENGCM07207, |
| 124 | }; |
| 125 | |
| 126 | static struct esdhc_soc_data esdhc_imx35_data = { |
| 127 | .flags = ESDHC_FLAG_ENGCM07207, |
| 128 | }; |
| 129 | |
| 130 | static struct esdhc_soc_data esdhc_imx51_data = { |
| 131 | .flags = 0, |
| 132 | }; |
| 133 | |
| 134 | static struct esdhc_soc_data esdhc_imx53_data = { |
| 135 | .flags = ESDHC_FLAG_MULTIBLK_NO_INT, |
| 136 | }; |
| 137 | |
| 138 | static struct esdhc_soc_data usdhc_imx6q_data = { |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 139 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, |
| 140 | }; |
| 141 | |
| 142 | static struct esdhc_soc_data usdhc_imx6sl_data = { |
| 143 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
| 144 | | ESDHC_FLAG_HAVE_CAP1, |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 145 | }; |
| 146 | |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 147 | struct pltfm_imx_data { |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 148 | u32 scratchpad; |
Dong Aisheng | e62d8b8 | 2012-05-11 14:56:01 +0800 | [diff] [blame] | 149 | struct pinctrl *pinctrl; |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 150 | struct pinctrl_state *pins_default; |
| 151 | struct pinctrl_state *pins_100mhz; |
| 152 | struct pinctrl_state *pins_200mhz; |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 153 | const struct esdhc_soc_data *socdata; |
Shawn Guo | 842afc0 | 2011-07-06 22:57:48 +0800 | [diff] [blame] | 154 | struct esdhc_platform_data boarddata; |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 155 | struct clk *clk_ipg; |
| 156 | struct clk *clk_ahb; |
| 157 | struct clk *clk_per; |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 158 | enum { |
| 159 | NO_CMD_PENDING, /* no multiblock command pending*/ |
| 160 | MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ |
| 161 | WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ |
| 162 | } multiblock_status; |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 163 | u32 uhs_mode; |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 164 | u32 is_ddr; |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 165 | }; |
| 166 | |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 167 | static struct platform_device_id imx_esdhc_devtype[] = { |
| 168 | { |
| 169 | .name = "sdhci-esdhc-imx25", |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 170 | .driver_data = (kernel_ulong_t) &esdhc_imx25_data, |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 171 | }, { |
| 172 | .name = "sdhci-esdhc-imx35", |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 173 | .driver_data = (kernel_ulong_t) &esdhc_imx35_data, |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 174 | }, { |
| 175 | .name = "sdhci-esdhc-imx51", |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 176 | .driver_data = (kernel_ulong_t) &esdhc_imx51_data, |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 177 | }, { |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 178 | /* sentinel */ |
| 179 | } |
| 180 | }; |
| 181 | MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); |
| 182 | |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 183 | static const struct of_device_id imx_esdhc_dt_ids[] = { |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 184 | { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, |
| 185 | { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, |
| 186 | { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, |
| 187 | { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 188 | { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 189 | { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 190 | { /* sentinel */ } |
| 191 | }; |
| 192 | MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); |
| 193 | |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 194 | static inline int is_imx25_esdhc(struct pltfm_imx_data *data) |
| 195 | { |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 196 | return data->socdata == &esdhc_imx25_data; |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 197 | } |
| 198 | |
| 199 | static inline int is_imx53_esdhc(struct pltfm_imx_data *data) |
| 200 | { |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 201 | return data->socdata == &esdhc_imx53_data; |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 202 | } |
| 203 | |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 204 | static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) |
| 205 | { |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 206 | return data->socdata == &usdhc_imx6q_data; |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 207 | } |
| 208 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 209 | static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) |
| 210 | { |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 211 | return !!(data->socdata->flags & ESDHC_FLAG_USDHC); |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 212 | } |
| 213 | |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 214 | static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) |
| 215 | { |
| 216 | void __iomem *base = host->ioaddr + (reg & ~0x3); |
| 217 | u32 shift = (reg & 0x3) * 8; |
| 218 | |
| 219 | writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); |
| 220 | } |
| 221 | |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 222 | static u32 esdhc_readl_le(struct sdhci_host *host, int reg) |
| 223 | { |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 224 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 225 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 226 | u32 val = readl(host->ioaddr + reg); |
| 227 | |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 228 | if (unlikely(reg == SDHCI_PRESENT_STATE)) { |
| 229 | u32 fsl_prss = val; |
| 230 | /* save the least 20 bits */ |
| 231 | val = fsl_prss & 0x000FFFFF; |
| 232 | /* move dat[0-3] bits */ |
| 233 | val |= (fsl_prss & 0x0F000000) >> 4; |
| 234 | /* move cmd line bit */ |
| 235 | val |= (fsl_prss & 0x00800000) << 1; |
| 236 | } |
| 237 | |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 238 | if (unlikely(reg == SDHCI_CAPABILITIES)) { |
Dong Aisheng | 6b4fb67 | 2013-10-18 19:48:44 +0800 | [diff] [blame] | 239 | /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ |
| 240 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) |
| 241 | val &= 0xffff0000; |
| 242 | |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 243 | /* In FSL esdhc IC module, only bit20 is used to indicate the |
| 244 | * ADMA2 capability of esdhc, but this bit is messed up on |
| 245 | * some SOCs (e.g. on MX25, MX35 this bit is set, but they |
| 246 | * don't actually support ADMA2). So set the BROKEN_ADMA |
| 247 | * uirk on MX25/35 platforms. |
| 248 | */ |
| 249 | |
| 250 | if (val & SDHCI_CAN_DO_ADMA1) { |
| 251 | val &= ~SDHCI_CAN_DO_ADMA1; |
| 252 | val |= SDHCI_CAN_DO_ADMA2; |
| 253 | } |
| 254 | } |
| 255 | |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 256 | if (unlikely(reg == SDHCI_CAPABILITIES_1)) { |
| 257 | if (esdhc_is_usdhc(imx_data)) { |
| 258 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) |
| 259 | val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; |
| 260 | else |
| 261 | /* imx6q/dl does not have cap_1 register, fake one */ |
| 262 | val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 |
Dong Aisheng | 888824b | 2013-10-18 19:48:48 +0800 | [diff] [blame] | 263 | | SDHCI_SUPPORT_SDR50 |
| 264 | | SDHCI_USE_SDR50_TUNING; |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 265 | } |
| 266 | } |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 267 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 268 | if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 269 | val = 0; |
| 270 | val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; |
| 271 | val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; |
| 272 | val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; |
| 273 | } |
| 274 | |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 275 | if (unlikely(reg == SDHCI_INT_STATUS)) { |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 276 | if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { |
| 277 | val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 278 | val |= SDHCI_INT_ADMA_ERROR; |
| 279 | } |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 280 | |
| 281 | /* |
| 282 | * mask off the interrupt we get in response to the manually |
| 283 | * sent CMD12 |
| 284 | */ |
| 285 | if ((imx_data->multiblock_status == WAIT_FOR_INT) && |
| 286 | ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { |
| 287 | val &= ~SDHCI_INT_RESPONSE; |
| 288 | writel(SDHCI_INT_RESPONSE, host->ioaddr + |
| 289 | SDHCI_INT_STATUS); |
| 290 | imx_data->multiblock_status = NO_CMD_PENDING; |
| 291 | } |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 292 | } |
| 293 | |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 294 | return val; |
| 295 | } |
| 296 | |
| 297 | static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) |
| 298 | { |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 299 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 300 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Tony Lin | 0d58864 | 2011-08-11 16:45:59 -0400 | [diff] [blame] | 301 | u32 data; |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 302 | |
Tony Lin | 0d58864 | 2011-08-11 16:45:59 -0400 | [diff] [blame] | 303 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { |
Tony Lin | 0d58864 | 2011-08-11 16:45:59 -0400 | [diff] [blame] | 304 | if (val & SDHCI_INT_CARD_INT) { |
| 305 | /* |
| 306 | * Clear and then set D3CD bit to avoid missing the |
| 307 | * card interrupt. This is a eSDHC controller problem |
| 308 | * so we need to apply the following workaround: clear |
| 309 | * and set D3CD bit will make eSDHC re-sample the card |
| 310 | * interrupt. In case a card interrupt was lost, |
| 311 | * re-sample it by the following steps. |
| 312 | */ |
| 313 | data = readl(host->ioaddr + SDHCI_HOST_CONTROL); |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 314 | data &= ~ESDHC_CTRL_D3CD; |
Tony Lin | 0d58864 | 2011-08-11 16:45:59 -0400 | [diff] [blame] | 315 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 316 | data |= ESDHC_CTRL_D3CD; |
Tony Lin | 0d58864 | 2011-08-11 16:45:59 -0400 | [diff] [blame] | 317 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
| 318 | } |
| 319 | } |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 320 | |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 321 | if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 322 | && (reg == SDHCI_INT_STATUS) |
| 323 | && (val & SDHCI_INT_DATA_END))) { |
| 324 | u32 v; |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 325 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 326 | v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; |
| 327 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 328 | |
| 329 | if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) |
| 330 | { |
| 331 | /* send a manual CMD12 with RESPTYP=none */ |
| 332 | data = MMC_STOP_TRANSMISSION << 24 | |
| 333 | SDHCI_CMD_ABORTCMD << 16; |
| 334 | writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); |
| 335 | imx_data->multiblock_status = WAIT_FOR_INT; |
| 336 | } |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 337 | } |
| 338 | |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 339 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { |
| 340 | if (val & SDHCI_INT_ADMA_ERROR) { |
| 341 | val &= ~SDHCI_INT_ADMA_ERROR; |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 342 | val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 343 | } |
| 344 | } |
| 345 | |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 346 | writel(val, host->ioaddr + reg); |
| 347 | } |
| 348 | |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 349 | static u16 esdhc_readw_le(struct sdhci_host *host, int reg) |
| 350 | { |
Shawn Guo | ef4d088 | 2013-01-15 23:30:27 +0800 | [diff] [blame] | 351 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 352 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 353 | u16 ret = 0; |
| 354 | u32 val; |
Shawn Guo | ef4d088 | 2013-01-15 23:30:27 +0800 | [diff] [blame] | 355 | |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 356 | if (unlikely(reg == SDHCI_HOST_VERSION)) { |
Shawn Guo | ef4d088 | 2013-01-15 23:30:27 +0800 | [diff] [blame] | 357 | reg ^= 2; |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 358 | if (esdhc_is_usdhc(imx_data)) { |
Shawn Guo | ef4d088 | 2013-01-15 23:30:27 +0800 | [diff] [blame] | 359 | /* |
| 360 | * The usdhc register returns a wrong host version. |
| 361 | * Correct it here. |
| 362 | */ |
| 363 | return SDHCI_SPEC_300; |
| 364 | } |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 365 | } |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 366 | |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 367 | if (unlikely(reg == SDHCI_HOST_CONTROL2)) { |
| 368 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 369 | if (val & ESDHC_VENDOR_SPEC_VSELECT) |
| 370 | ret |= SDHCI_CTRL_VDD_180; |
| 371 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 372 | if (esdhc_is_usdhc(imx_data)) { |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 373 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
| 374 | val = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 375 | else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) |
| 376 | /* the std tuning bits is in ACMD12_ERR for imx6sl */ |
| 377 | val = readl(host->ioaddr + SDHCI_ACMD12_ERR); |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 378 | } |
| 379 | |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 380 | if (val & ESDHC_MIX_CTRL_EXE_TUNE) |
| 381 | ret |= SDHCI_CTRL_EXEC_TUNING; |
| 382 | if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) |
| 383 | ret |= SDHCI_CTRL_TUNED_CLK; |
| 384 | |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 385 | ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK); |
| 386 | ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 387 | |
| 388 | return ret; |
| 389 | } |
| 390 | |
Dong Aisheng | 7dd109e | 2013-10-30 22:09:49 +0800 | [diff] [blame] | 391 | if (unlikely(reg == SDHCI_TRANSFER_MODE)) { |
| 392 | if (esdhc_is_usdhc(imx_data)) { |
| 393 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 394 | ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; |
| 395 | /* Swap AC23 bit */ |
| 396 | if (m & ESDHC_MIX_CTRL_AC23EN) { |
| 397 | ret &= ~ESDHC_MIX_CTRL_AC23EN; |
| 398 | ret |= SDHCI_TRNS_AUTO_CMD23; |
| 399 | } |
| 400 | } else { |
| 401 | ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); |
| 402 | } |
| 403 | |
| 404 | return ret; |
| 405 | } |
| 406 | |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 407 | return readw(host->ioaddr + reg); |
| 408 | } |
| 409 | |
| 410 | static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) |
| 411 | { |
| 412 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 413 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 414 | u32 new_val = 0; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 415 | |
| 416 | switch (reg) { |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 417 | case SDHCI_CLOCK_CONTROL: |
| 418 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 419 | if (val & SDHCI_CLOCK_CARD_EN) |
| 420 | new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; |
| 421 | else |
| 422 | new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; |
| 423 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); |
| 424 | return; |
| 425 | case SDHCI_HOST_CONTROL2: |
| 426 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 427 | if (val & SDHCI_CTRL_VDD_180) |
| 428 | new_val |= ESDHC_VENDOR_SPEC_VSELECT; |
| 429 | else |
| 430 | new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; |
| 431 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); |
| 432 | imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK; |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 433 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { |
| 434 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 435 | if (val & SDHCI_CTRL_TUNED_CLK) |
| 436 | new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; |
| 437 | else |
| 438 | new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; |
| 439 | writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); |
| 440 | } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { |
| 441 | u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); |
| 442 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
Dong Aisheng | 8b2bb0ad | 2013-11-04 16:38:27 +0800 | [diff] [blame] | 443 | if (val & SDHCI_CTRL_TUNED_CLK) { |
| 444 | v |= ESDHC_MIX_CTRL_SMPCLK_SEL; |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 445 | } else { |
Dong Aisheng | 8b2bb0ad | 2013-11-04 16:38:27 +0800 | [diff] [blame] | 446 | v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 447 | m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; |
| 448 | } |
| 449 | |
Dong Aisheng | 8b2bb0ad | 2013-11-04 16:38:27 +0800 | [diff] [blame] | 450 | if (val & SDHCI_CTRL_EXEC_TUNING) { |
| 451 | v |= ESDHC_MIX_CTRL_EXE_TUNE; |
| 452 | m |= ESDHC_MIX_CTRL_FBCLK_SEL; |
| 453 | } else { |
| 454 | v &= ~ESDHC_MIX_CTRL_EXE_TUNE; |
| 455 | } |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 456 | |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 457 | writel(v, host->ioaddr + SDHCI_ACMD12_ERR); |
| 458 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
| 459 | } |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 460 | return; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 461 | case SDHCI_TRANSFER_MODE: |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 462 | if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 463 | && (host->cmd->opcode == SD_IO_RW_EXTENDED) |
| 464 | && (host->cmd->data->blocks > 1) |
| 465 | && (host->cmd->data->flags & MMC_DATA_READ)) { |
| 466 | u32 v; |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 467 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 468 | v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; |
| 469 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 470 | } |
Shawn Guo | 69f5469 | 2013-01-21 19:02:24 +0800 | [diff] [blame] | 471 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 472 | if (esdhc_is_usdhc(imx_data)) { |
Shawn Guo | 69f5469 | 2013-01-21 19:02:24 +0800 | [diff] [blame] | 473 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
Shawn Guo | 2a15f98 | 2013-01-21 19:02:26 +0800 | [diff] [blame] | 474 | /* Swap AC23 bit */ |
| 475 | if (val & SDHCI_TRNS_AUTO_CMD23) { |
| 476 | val &= ~SDHCI_TRNS_AUTO_CMD23; |
| 477 | val |= ESDHC_MIX_CTRL_AC23EN; |
| 478 | } |
| 479 | m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); |
Shawn Guo | 69f5469 | 2013-01-21 19:02:24 +0800 | [diff] [blame] | 480 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
| 481 | } else { |
| 482 | /* |
| 483 | * Postpone this write, we must do it together with a |
| 484 | * command write that is down below. |
| 485 | */ |
| 486 | imx_data->scratchpad = val; |
| 487 | } |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 488 | return; |
| 489 | case SDHCI_COMMAND: |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 490 | if (host->cmd->opcode == MMC_STOP_TRANSMISSION) |
Richard Zhu | 58ac817 | 2011-03-21 13:22:16 +0800 | [diff] [blame] | 491 | val |= SDHCI_CMD_ABORTCMD; |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 492 | |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 493 | if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 494 | (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) |
Lucas Stach | 361b848 | 2013-03-15 09:49:26 +0100 | [diff] [blame] | 495 | imx_data->multiblock_status = MULTIBLK_IN_PROCESS; |
| 496 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 497 | if (esdhc_is_usdhc(imx_data)) |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 498 | writel(val << 16, |
| 499 | host->ioaddr + SDHCI_TRANSFER_MODE); |
Shawn Guo | 69f5469 | 2013-01-21 19:02:24 +0800 | [diff] [blame] | 500 | else |
Shawn Guo | 95a2482 | 2011-09-19 17:32:21 +0800 | [diff] [blame] | 501 | writel(val << 16 | imx_data->scratchpad, |
| 502 | host->ioaddr + SDHCI_TRANSFER_MODE); |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 503 | return; |
| 504 | case SDHCI_BLOCK_SIZE: |
| 505 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); |
| 506 | break; |
| 507 | } |
| 508 | esdhc_clrset_le(host, 0xffff, val, reg); |
| 509 | } |
| 510 | |
| 511 | static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) |
| 512 | { |
Wilson Callan | 9a0985b | 2012-07-19 02:49:16 -0400 | [diff] [blame] | 513 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 514 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 515 | u32 new_val; |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 516 | u32 mask; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 517 | |
| 518 | switch (reg) { |
| 519 | case SDHCI_POWER_CONTROL: |
| 520 | /* |
| 521 | * FSL put some DMA bits here |
| 522 | * If your board has a regulator, code should be here |
| 523 | */ |
| 524 | return; |
| 525 | case SDHCI_HOST_CONTROL: |
Shawn Guo | 6b40d18 | 2013-01-15 23:36:52 +0800 | [diff] [blame] | 526 | /* FSL messed up here, so we need to manually compose it. */ |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 527 | new_val = val & SDHCI_CTRL_LED; |
Masanari Iida | 7122bbb | 2012-08-05 23:25:40 +0900 | [diff] [blame] | 528 | /* ensure the endianness */ |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 529 | new_val |= ESDHC_HOST_CONTROL_LE; |
Wilson Callan | 9a0985b | 2012-07-19 02:49:16 -0400 | [diff] [blame] | 530 | /* bits 8&9 are reserved on mx25 */ |
| 531 | if (!is_imx25_esdhc(imx_data)) { |
| 532 | /* DMA mode bits are shifted */ |
| 533 | new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; |
| 534 | } |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 535 | |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 536 | /* |
| 537 | * Do not touch buswidth bits here. This is done in |
| 538 | * esdhc_pltfm_bus_width. |
Martin Fuzzey | f682574 | 2013-04-15 17:08:35 +0200 | [diff] [blame] | 539 | * Do not touch the D3CD bit either which is used for the |
| 540 | * SDIO interrupt errata workaround. |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 541 | */ |
Martin Fuzzey | f682574 | 2013-04-15 17:08:35 +0200 | [diff] [blame] | 542 | mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 543 | |
| 544 | esdhc_clrset_le(host, mask, new_val, reg); |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 545 | return; |
| 546 | } |
| 547 | esdhc_clrset_le(host, 0xff, val, reg); |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 548 | |
| 549 | /* |
| 550 | * The esdhc has a design violation to SDHC spec which tells |
| 551 | * that software reset should not affect card detection circuit. |
| 552 | * But esdhc clears its SYSCTL register bits [0..2] during the |
| 553 | * software reset. This will stop those clocks that card detection |
| 554 | * circuit relies on. To work around it, we turn the clocks on back |
| 555 | * to keep card detection circuit functional. |
| 556 | */ |
Shawn Guo | 58c8c4f | 2013-01-21 19:02:25 +0800 | [diff] [blame] | 557 | if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 558 | esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); |
Shawn Guo | 58c8c4f | 2013-01-21 19:02:25 +0800 | [diff] [blame] | 559 | /* |
| 560 | * The reset on usdhc fails to clear MIX_CTRL register. |
| 561 | * Do it manually here. |
| 562 | */ |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 563 | if (esdhc_is_usdhc(imx_data)) { |
Dong Aisheng | d131a71 | 2013-11-04 16:38:26 +0800 | [diff] [blame] | 564 | /* the tuning bits should be kept during reset */ |
| 565 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 566 | writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, |
| 567 | host->ioaddr + ESDHC_MIX_CTRL); |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 568 | imx_data->is_ddr = 0; |
| 569 | } |
Shawn Guo | 58c8c4f | 2013-01-21 19:02:25 +0800 | [diff] [blame] | 570 | } |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 571 | } |
| 572 | |
Lucas Stach | 0ddf03c | 2013-06-05 15:13:26 +0200 | [diff] [blame] | 573 | static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) |
| 574 | { |
| 575 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 576 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
| 577 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
| 578 | |
Dong Aisheng | a974862 | 2013-12-26 15:23:53 +0800 | [diff] [blame] | 579 | if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock)) |
Lucas Stach | 0ddf03c | 2013-06-05 15:13:26 +0200 | [diff] [blame] | 580 | return boarddata->f_max; |
| 581 | else |
Dong Aisheng | a974862 | 2013-12-26 15:23:53 +0800 | [diff] [blame] | 582 | return pltfm_host->clock; |
Lucas Stach | 0ddf03c | 2013-06-05 15:13:26 +0200 | [diff] [blame] | 583 | } |
| 584 | |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 585 | static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) |
| 586 | { |
| 587 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 588 | |
Dong Aisheng | a974862 | 2013-12-26 15:23:53 +0800 | [diff] [blame] | 589 | return pltfm_host->clock / 256 / 16; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 590 | } |
| 591 | |
Lucas Stach | 8ba9580 | 2013-06-05 15:13:25 +0200 | [diff] [blame] | 592 | static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, |
| 593 | unsigned int clock) |
| 594 | { |
| 595 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 596 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Dong Aisheng | a974862 | 2013-12-26 15:23:53 +0800 | [diff] [blame] | 597 | unsigned int host_clock = pltfm_host->clock; |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 598 | int pre_div = 2; |
| 599 | int div = 1; |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 600 | u32 temp, val; |
Lucas Stach | 8ba9580 | 2013-06-05 15:13:25 +0200 | [diff] [blame] | 601 | |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 602 | if (clock == 0) { |
Russell King | 1650d0c | 2014-04-25 12:58:50 +0100 | [diff] [blame^] | 603 | host->mmc->actual_clock = 0; |
| 604 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 605 | if (esdhc_is_usdhc(imx_data)) { |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 606 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 607 | writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, |
| 608 | host->ioaddr + ESDHC_VENDOR_SPEC); |
| 609 | } |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 610 | return; |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 611 | } |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 612 | |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 613 | if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) |
Dong Aisheng | 5f7886c | 2013-09-13 19:11:36 +0800 | [diff] [blame] | 614 | pre_div = 1; |
| 615 | |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 616 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |
| 617 | temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
| 618 | | ESDHC_CLOCK_MASK); |
| 619 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); |
| 620 | |
| 621 | while (host_clock / pre_div / 16 > clock && pre_div < 256) |
| 622 | pre_div *= 2; |
| 623 | |
| 624 | while (host_clock / pre_div / div > clock && div < 16) |
| 625 | div++; |
| 626 | |
Dong Aisheng | e76b855 | 2013-09-13 19:11:37 +0800 | [diff] [blame] | 627 | host->mmc->actual_clock = host_clock / pre_div / div; |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 628 | dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", |
Dong Aisheng | e76b855 | 2013-09-13 19:11:37 +0800 | [diff] [blame] | 629 | clock, host->mmc->actual_clock); |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 630 | |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 631 | if (imx_data->is_ddr) |
| 632 | pre_div >>= 2; |
| 633 | else |
| 634 | pre_div >>= 1; |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 635 | div--; |
| 636 | |
| 637 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |
| 638 | temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
| 639 | | (div << ESDHC_DIVIDER_SHIFT) |
| 640 | | (pre_div << ESDHC_PREDIV_SHIFT)); |
| 641 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 642 | |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 643 | if (esdhc_is_usdhc(imx_data)) { |
Dong Aisheng | fed2f6e | 2013-09-13 19:11:33 +0800 | [diff] [blame] | 644 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
| 645 | writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, |
| 646 | host->ioaddr + ESDHC_VENDOR_SPEC); |
| 647 | } |
| 648 | |
Dong Aisheng | d31fc00 | 2013-09-13 19:11:32 +0800 | [diff] [blame] | 649 | mdelay(1); |
Lucas Stach | 8ba9580 | 2013-06-05 15:13:25 +0200 | [diff] [blame] | 650 | } |
| 651 | |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 652 | static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) |
| 653 | { |
Shawn Guo | 842afc0 | 2011-07-06 22:57:48 +0800 | [diff] [blame] | 654 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 655 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
| 656 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 657 | |
| 658 | switch (boarddata->wp_type) { |
| 659 | case ESDHC_WP_GPIO: |
Shawn Guo | fbe5fdd | 2012-12-11 22:32:20 +0800 | [diff] [blame] | 660 | return mmc_gpio_get_ro(host->mmc); |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 661 | case ESDHC_WP_CONTROLLER: |
| 662 | return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & |
| 663 | SDHCI_WRITE_PROTECT); |
| 664 | case ESDHC_WP_NONE: |
| 665 | break; |
| 666 | } |
| 667 | |
| 668 | return -ENOSYS; |
| 669 | } |
| 670 | |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 671 | static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 672 | { |
| 673 | u32 ctrl; |
| 674 | |
| 675 | switch (width) { |
| 676 | case MMC_BUS_WIDTH_8: |
| 677 | ctrl = ESDHC_CTRL_8BITBUS; |
| 678 | break; |
| 679 | case MMC_BUS_WIDTH_4: |
| 680 | ctrl = ESDHC_CTRL_4BITBUS; |
| 681 | break; |
| 682 | default: |
| 683 | ctrl = 0; |
| 684 | break; |
| 685 | } |
| 686 | |
| 687 | esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, |
| 688 | SDHCI_HOST_CONTROL); |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 689 | } |
| 690 | |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 691 | static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) |
| 692 | { |
| 693 | u32 reg; |
| 694 | |
| 695 | /* FIXME: delay a bit for card to be ready for next tuning due to errors */ |
| 696 | mdelay(1); |
| 697 | |
Dong Aisheng | ce090a4 | 2013-11-04 16:38:28 +0800 | [diff] [blame] | 698 | pm_runtime_get_sync(host->mmc->parent); |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 699 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 700 | reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | |
| 701 | ESDHC_MIX_CTRL_FBCLK_SEL; |
| 702 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); |
| 703 | writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); |
| 704 | dev_dbg(mmc_dev(host->mmc), |
| 705 | "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", |
| 706 | val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); |
| 707 | } |
| 708 | |
| 709 | static void esdhc_request_done(struct mmc_request *mrq) |
| 710 | { |
| 711 | complete(&mrq->completion); |
| 712 | } |
| 713 | |
| 714 | static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode) |
| 715 | { |
| 716 | struct mmc_command cmd = {0}; |
Fabio Estevam | a50145f | 2013-10-04 22:59:23 -0300 | [diff] [blame] | 717 | struct mmc_request mrq = {NULL}; |
Dong Aisheng | 0322191 | 2013-09-13 19:11:34 +0800 | [diff] [blame] | 718 | struct mmc_data data = {0}; |
| 719 | struct scatterlist sg; |
| 720 | char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN]; |
| 721 | |
| 722 | cmd.opcode = opcode; |
| 723 | cmd.arg = 0; |
| 724 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; |
| 725 | |
| 726 | data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN; |
| 727 | data.blocks = 1; |
| 728 | data.flags = MMC_DATA_READ; |
| 729 | data.sg = &sg; |
| 730 | data.sg_len = 1; |
| 731 | |
| 732 | sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern)); |
| 733 | |
| 734 | mrq.cmd = &cmd; |
| 735 | mrq.cmd->mrq = &mrq; |
| 736 | mrq.data = &data; |
| 737 | mrq.data->mrq = &mrq; |
| 738 | mrq.cmd->data = mrq.data; |
| 739 | |
| 740 | mrq.done = esdhc_request_done; |
| 741 | init_completion(&(mrq.completion)); |
| 742 | |
| 743 | disable_irq(host->irq); |
| 744 | spin_lock(&host->lock); |
| 745 | host->mrq = &mrq; |
| 746 | |
| 747 | sdhci_send_command(host, mrq.cmd); |
| 748 | |
| 749 | spin_unlock(&host->lock); |
| 750 | enable_irq(host->irq); |
| 751 | |
| 752 | wait_for_completion(&mrq.completion); |
| 753 | |
| 754 | if (cmd.error) |
| 755 | return cmd.error; |
| 756 | if (data.error) |
| 757 | return data.error; |
| 758 | |
| 759 | return 0; |
| 760 | } |
| 761 | |
| 762 | static void esdhc_post_tuning(struct sdhci_host *host) |
| 763 | { |
| 764 | u32 reg; |
| 765 | |
| 766 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 767 | reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; |
| 768 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); |
| 769 | } |
| 770 | |
| 771 | static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) |
| 772 | { |
| 773 | int min, max, avg, ret; |
| 774 | |
| 775 | /* find the mininum delay first which can pass tuning */ |
| 776 | min = ESDHC_TUNE_CTRL_MIN; |
| 777 | while (min < ESDHC_TUNE_CTRL_MAX) { |
| 778 | esdhc_prepare_tuning(host, min); |
| 779 | if (!esdhc_send_tuning_cmd(host, opcode)) |
| 780 | break; |
| 781 | min += ESDHC_TUNE_CTRL_STEP; |
| 782 | } |
| 783 | |
| 784 | /* find the maxinum delay which can not pass tuning */ |
| 785 | max = min + ESDHC_TUNE_CTRL_STEP; |
| 786 | while (max < ESDHC_TUNE_CTRL_MAX) { |
| 787 | esdhc_prepare_tuning(host, max); |
| 788 | if (esdhc_send_tuning_cmd(host, opcode)) { |
| 789 | max -= ESDHC_TUNE_CTRL_STEP; |
| 790 | break; |
| 791 | } |
| 792 | max += ESDHC_TUNE_CTRL_STEP; |
| 793 | } |
| 794 | |
| 795 | /* use average delay to get the best timing */ |
| 796 | avg = (min + max) / 2; |
| 797 | esdhc_prepare_tuning(host, avg); |
| 798 | ret = esdhc_send_tuning_cmd(host, opcode); |
| 799 | esdhc_post_tuning(host); |
| 800 | |
| 801 | dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", |
| 802 | ret ? "failed" : "passed", avg, ret); |
| 803 | |
| 804 | return ret; |
| 805 | } |
| 806 | |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 807 | static int esdhc_change_pinstate(struct sdhci_host *host, |
| 808 | unsigned int uhs) |
| 809 | { |
| 810 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 811 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
| 812 | struct pinctrl_state *pinctrl; |
| 813 | |
| 814 | dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); |
| 815 | |
| 816 | if (IS_ERR(imx_data->pinctrl) || |
| 817 | IS_ERR(imx_data->pins_default) || |
| 818 | IS_ERR(imx_data->pins_100mhz) || |
| 819 | IS_ERR(imx_data->pins_200mhz)) |
| 820 | return -EINVAL; |
| 821 | |
| 822 | switch (uhs) { |
| 823 | case MMC_TIMING_UHS_SDR50: |
| 824 | pinctrl = imx_data->pins_100mhz; |
| 825 | break; |
| 826 | case MMC_TIMING_UHS_SDR104: |
Dong Aisheng | 429a5b4 | 2013-10-30 22:10:42 +0800 | [diff] [blame] | 827 | case MMC_TIMING_MMC_HS200: |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 828 | pinctrl = imx_data->pins_200mhz; |
| 829 | break; |
| 830 | default: |
| 831 | /* back to default state for other legacy timing */ |
| 832 | pinctrl = imx_data->pins_default; |
| 833 | } |
| 834 | |
| 835 | return pinctrl_select_state(imx_data->pinctrl, pinctrl); |
| 836 | } |
| 837 | |
| 838 | static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) |
| 839 | { |
| 840 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 841 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Dong Aisheng | 602519b | 2013-10-18 19:48:47 +0800 | [diff] [blame] | 842 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 843 | |
| 844 | switch (uhs) { |
| 845 | case MMC_TIMING_UHS_SDR12: |
| 846 | imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12; |
| 847 | break; |
| 848 | case MMC_TIMING_UHS_SDR25: |
| 849 | imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25; |
| 850 | break; |
| 851 | case MMC_TIMING_UHS_SDR50: |
| 852 | imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50; |
| 853 | break; |
| 854 | case MMC_TIMING_UHS_SDR104: |
Dong Aisheng | 429a5b4 | 2013-10-30 22:10:42 +0800 | [diff] [blame] | 855 | case MMC_TIMING_MMC_HS200: |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 856 | imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104; |
| 857 | break; |
| 858 | case MMC_TIMING_UHS_DDR50: |
| 859 | imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50; |
Dong Aisheng | de5bdbf | 2013-10-18 19:48:46 +0800 | [diff] [blame] | 860 | writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | |
| 861 | ESDHC_MIX_CTRL_DDREN, |
| 862 | host->ioaddr + ESDHC_MIX_CTRL); |
| 863 | imx_data->is_ddr = 1; |
Dong Aisheng | 602519b | 2013-10-18 19:48:47 +0800 | [diff] [blame] | 864 | if (boarddata->delay_line) { |
| 865 | u32 v; |
| 866 | v = boarddata->delay_line << |
| 867 | ESDHC_DLL_OVERRIDE_VAL_SHIFT | |
| 868 | (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); |
| 869 | if (is_imx53_esdhc(imx_data)) |
| 870 | v <<= 1; |
| 871 | writel(v, host->ioaddr + ESDHC_DLL_CTRL); |
| 872 | } |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 873 | break; |
| 874 | } |
| 875 | |
| 876 | return esdhc_change_pinstate(host, uhs); |
| 877 | } |
| 878 | |
Russell King | 0718e59 | 2014-04-25 12:57:18 +0100 | [diff] [blame] | 879 | static void esdhc_reset(struct sdhci_host *host, u8 mask) |
| 880 | { |
| 881 | sdhci_reset(host, mask); |
| 882 | |
| 883 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 884 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
| 885 | } |
| 886 | |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 887 | static struct sdhci_ops sdhci_esdhc_ops = { |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 888 | .read_l = esdhc_readl_le, |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 889 | .read_w = esdhc_readw_le, |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 890 | .write_l = esdhc_writel_le, |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 891 | .write_w = esdhc_writew_le, |
| 892 | .write_b = esdhc_writeb_le, |
Lucas Stach | 8ba9580 | 2013-06-05 15:13:25 +0200 | [diff] [blame] | 893 | .set_clock = esdhc_pltfm_set_clock, |
Lucas Stach | 0ddf03c | 2013-06-05 15:13:26 +0200 | [diff] [blame] | 894 | .get_max_clock = esdhc_pltfm_get_max_clock, |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 895 | .get_min_clock = esdhc_pltfm_get_min_clock, |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 896 | .get_ro = esdhc_pltfm_get_ro, |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 897 | .set_bus_width = esdhc_pltfm_set_bus_width, |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 898 | .set_uhs_signaling = esdhc_set_uhs_signaling, |
Russell King | 0718e59 | 2014-04-25 12:57:18 +0100 | [diff] [blame] | 899 | .reset = esdhc_reset, |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 900 | }; |
| 901 | |
Lars-Peter Clausen | 1db5eeb | 2013-03-13 19:26:03 +0100 | [diff] [blame] | 902 | static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 903 | .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT |
| 904 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
| 905 | | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 906 | | SDHCI_QUIRK_BROKEN_CARD_DETECTION, |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 907 | .ops = &sdhci_esdhc_ops, |
| 908 | }; |
| 909 | |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 910 | #ifdef CONFIG_OF |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 911 | static int |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 912 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, |
| 913 | struct esdhc_platform_data *boarddata) |
| 914 | { |
| 915 | struct device_node *np = pdev->dev.of_node; |
| 916 | |
| 917 | if (!np) |
| 918 | return -ENODEV; |
| 919 | |
Arnd Bergmann | 7f21779 | 2012-05-13 00:14:24 -0400 | [diff] [blame] | 920 | if (of_get_property(np, "non-removable", NULL)) |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 921 | boarddata->cd_type = ESDHC_CD_PERMANENT; |
| 922 | |
| 923 | if (of_get_property(np, "fsl,cd-controller", NULL)) |
| 924 | boarddata->cd_type = ESDHC_CD_CONTROLLER; |
| 925 | |
| 926 | if (of_get_property(np, "fsl,wp-controller", NULL)) |
| 927 | boarddata->wp_type = ESDHC_WP_CONTROLLER; |
| 928 | |
| 929 | boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); |
| 930 | if (gpio_is_valid(boarddata->cd_gpio)) |
| 931 | boarddata->cd_type = ESDHC_CD_GPIO; |
| 932 | |
| 933 | boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); |
| 934 | if (gpio_is_valid(boarddata->wp_gpio)) |
| 935 | boarddata->wp_type = ESDHC_WP_GPIO; |
| 936 | |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 937 | of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); |
| 938 | |
Lucas Stach | 0ddf03c | 2013-06-05 15:13:26 +0200 | [diff] [blame] | 939 | of_property_read_u32(np, "max-frequency", &boarddata->f_max); |
| 940 | |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 941 | if (of_find_property(np, "no-1-8-v", NULL)) |
| 942 | boarddata->support_vsel = false; |
| 943 | else |
| 944 | boarddata->support_vsel = true; |
| 945 | |
Dong Aisheng | 602519b | 2013-10-18 19:48:47 +0800 | [diff] [blame] | 946 | if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) |
| 947 | boarddata->delay_line = 0; |
| 948 | |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 949 | return 0; |
| 950 | } |
| 951 | #else |
| 952 | static inline int |
| 953 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, |
| 954 | struct esdhc_platform_data *boarddata) |
| 955 | { |
| 956 | return -ENODEV; |
| 957 | } |
| 958 | #endif |
| 959 | |
Bill Pemberton | c3be1ef | 2012-11-19 13:23:06 -0500 | [diff] [blame] | 960 | static int sdhci_esdhc_imx_probe(struct platform_device *pdev) |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 961 | { |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 962 | const struct of_device_id *of_id = |
| 963 | of_match_device(imx_esdhc_dt_ids, &pdev->dev); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 964 | struct sdhci_pltfm_host *pltfm_host; |
| 965 | struct sdhci_host *host; |
| 966 | struct esdhc_platform_data *boarddata; |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 967 | int err; |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 968 | struct pltfm_imx_data *imx_data; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 969 | |
Christian Daudt | 0e74823 | 2013-05-29 13:50:05 -0700 | [diff] [blame] | 970 | host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 971 | if (IS_ERR(host)) |
| 972 | return PTR_ERR(host); |
| 973 | |
| 974 | pltfm_host = sdhci_priv(host); |
| 975 | |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 976 | imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 977 | if (!imx_data) { |
| 978 | err = -ENOMEM; |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 979 | goto free_sdhci; |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 980 | } |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 981 | |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 982 | imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) |
| 983 | pdev->id_entry->driver_data; |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 984 | pltfm_host->priv = imx_data; |
| 985 | |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 986 | imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
| 987 | if (IS_ERR(imx_data->clk_ipg)) { |
| 988 | err = PTR_ERR(imx_data->clk_ipg); |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 989 | goto free_sdhci; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 990 | } |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 991 | |
| 992 | imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); |
| 993 | if (IS_ERR(imx_data->clk_ahb)) { |
| 994 | err = PTR_ERR(imx_data->clk_ahb); |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 995 | goto free_sdhci; |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 996 | } |
| 997 | |
| 998 | imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); |
| 999 | if (IS_ERR(imx_data->clk_per)) { |
| 1000 | err = PTR_ERR(imx_data->clk_per); |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1001 | goto free_sdhci; |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 1002 | } |
| 1003 | |
| 1004 | pltfm_host->clk = imx_data->clk_per; |
Dong Aisheng | a974862 | 2013-12-26 15:23:53 +0800 | [diff] [blame] | 1005 | pltfm_host->clock = clk_get_rate(pltfm_host->clk); |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 1006 | clk_prepare_enable(imx_data->clk_per); |
| 1007 | clk_prepare_enable(imx_data->clk_ipg); |
| 1008 | clk_prepare_enable(imx_data->clk_ahb); |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1009 | |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 1010 | imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); |
Dong Aisheng | e62d8b8 | 2012-05-11 14:56:01 +0800 | [diff] [blame] | 1011 | if (IS_ERR(imx_data->pinctrl)) { |
| 1012 | err = PTR_ERR(imx_data->pinctrl); |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1013 | goto disable_clk; |
Dong Aisheng | e62d8b8 | 2012-05-11 14:56:01 +0800 | [diff] [blame] | 1014 | } |
| 1015 | |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 1016 | imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, |
| 1017 | PINCTRL_STATE_DEFAULT); |
| 1018 | if (IS_ERR(imx_data->pins_default)) { |
| 1019 | err = PTR_ERR(imx_data->pins_default); |
| 1020 | dev_err(mmc_dev(host->mmc), "could not get default state\n"); |
| 1021 | goto disable_clk; |
| 1022 | } |
| 1023 | |
Eric Bénard | b8915282 | 2012-04-18 02:30:20 +0200 | [diff] [blame] | 1024 | host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; |
Eric Bénard | 37865fe | 2010-10-23 01:57:21 +0200 | [diff] [blame] | 1025 | |
Shawn Guo | f47c4bb | 2013-10-17 15:19:47 +0800 | [diff] [blame] | 1026 | if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 1027 | /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ |
Richard Zhu | 97e4ba6 | 2011-08-11 16:51:46 -0400 | [diff] [blame] | 1028 | host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK |
| 1029 | | SDHCI_QUIRK_BROKEN_ADMA; |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 1030 | |
Shawn Guo | f750ba9 | 2011-11-10 16:39:32 +0800 | [diff] [blame] | 1031 | /* |
| 1032 | * The imx6q ROM code will change the default watermark level setting |
| 1033 | * to something insane. Change it back here. |
| 1034 | */ |
Dong Aisheng | 69ed60e | 2013-10-18 19:48:49 +0800 | [diff] [blame] | 1035 | if (esdhc_is_usdhc(imx_data)) { |
Shawn Guo | 60bf639 | 2013-01-15 23:36:53 +0800 | [diff] [blame] | 1036 | writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); |
Dong Aisheng | 69ed60e | 2013-10-18 19:48:49 +0800 | [diff] [blame] | 1037 | host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; |
Dong Aisheng | e2997c9 | 2013-10-30 22:09:52 +0800 | [diff] [blame] | 1038 | host->mmc->caps |= MMC_CAP_1_8V_DDR; |
Dong Aisheng | 69ed60e | 2013-10-18 19:48:49 +0800 | [diff] [blame] | 1039 | } |
Shawn Guo | f750ba9 | 2011-11-10 16:39:32 +0800 | [diff] [blame] | 1040 | |
Dong Aisheng | 6e9fd28 | 2013-10-18 19:48:43 +0800 | [diff] [blame] | 1041 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
| 1042 | sdhci_esdhc_ops.platform_execute_tuning = |
| 1043 | esdhc_executing_tuning; |
Dong Aisheng | 8b2bb0ad | 2013-11-04 16:38:27 +0800 | [diff] [blame] | 1044 | |
| 1045 | if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) |
| 1046 | writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) | |
| 1047 | ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP, |
| 1048 | host->ioaddr + ESDHC_TUNING_CTRL); |
| 1049 | |
Shawn Guo | 842afc0 | 2011-07-06 22:57:48 +0800 | [diff] [blame] | 1050 | boarddata = &imx_data->boarddata; |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 1051 | if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { |
| 1052 | if (!host->mmc->parent->platform_data) { |
| 1053 | dev_err(mmc_dev(host->mmc), "no board data!\n"); |
| 1054 | err = -EINVAL; |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1055 | goto disable_clk; |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 1056 | } |
| 1057 | imx_data->boarddata = *((struct esdhc_platform_data *) |
| 1058 | host->mmc->parent->platform_data); |
| 1059 | } |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 1060 | |
| 1061 | /* write_protect */ |
| 1062 | if (boarddata->wp_type == ESDHC_WP_GPIO) { |
Shawn Guo | fbe5fdd | 2012-12-11 22:32:20 +0800 | [diff] [blame] | 1063 | err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 1064 | if (err) { |
Shawn Guo | fbe5fdd | 2012-12-11 22:32:20 +0800 | [diff] [blame] | 1065 | dev_err(mmc_dev(host->mmc), |
| 1066 | "failed to request write-protect gpio!\n"); |
| 1067 | goto disable_clk; |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 1068 | } |
Shawn Guo | fbe5fdd | 2012-12-11 22:32:20 +0800 | [diff] [blame] | 1069 | host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 1070 | } |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 1071 | |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 1072 | /* card_detect */ |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 1073 | switch (boarddata->cd_type) { |
| 1074 | case ESDHC_CD_GPIO: |
Laurent Pinchart | 214fc30 | 2013-08-08 12:38:31 +0200 | [diff] [blame] | 1075 | err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 1076 | if (err) { |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 1077 | dev_err(mmc_dev(host->mmc), |
Shawn Guo | fbe5fdd | 2012-12-11 22:32:20 +0800 | [diff] [blame] | 1078 | "failed to request card-detect gpio!\n"); |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1079 | goto disable_clk; |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 1080 | } |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 1081 | /* fall through */ |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 1082 | |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 1083 | case ESDHC_CD_CONTROLLER: |
| 1084 | /* we have a working card_detect back */ |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 1085 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 1086 | break; |
| 1087 | |
| 1088 | case ESDHC_CD_PERMANENT: |
Dong Aisheng | e526003 | 2013-10-30 22:09:51 +0800 | [diff] [blame] | 1089 | host->mmc->caps |= MMC_CAP_NONREMOVABLE; |
Shawn Guo | 913413c | 2011-06-21 22:41:51 +0800 | [diff] [blame] | 1090 | break; |
| 1091 | |
| 1092 | case ESDHC_CD_NONE: |
| 1093 | break; |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 1094 | } |
Eric Bénard | 16a790b | 2010-10-23 01:57:22 +0200 | [diff] [blame] | 1095 | |
Sascha Hauer | af51079 | 2013-01-21 19:02:28 +0800 | [diff] [blame] | 1096 | switch (boarddata->max_bus_width) { |
| 1097 | case 8: |
| 1098 | host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; |
| 1099 | break; |
| 1100 | case 4: |
| 1101 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; |
| 1102 | break; |
| 1103 | case 1: |
| 1104 | default: |
| 1105 | host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; |
| 1106 | break; |
| 1107 | } |
| 1108 | |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 1109 | /* sdr50 and sdr104 needs work on 1.8v signal voltage */ |
Shawn Guo | 9d61c00 | 2013-10-17 15:19:45 +0800 | [diff] [blame] | 1110 | if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) { |
Dong Aisheng | ad93220 | 2013-09-13 19:11:35 +0800 | [diff] [blame] | 1111 | imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, |
| 1112 | ESDHC_PINCTRL_STATE_100MHZ); |
| 1113 | imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, |
| 1114 | ESDHC_PINCTRL_STATE_200MHZ); |
| 1115 | if (IS_ERR(imx_data->pins_100mhz) || |
| 1116 | IS_ERR(imx_data->pins_200mhz)) { |
| 1117 | dev_warn(mmc_dev(host->mmc), |
| 1118 | "could not get ultra high speed state, work on normal mode\n"); |
| 1119 | /* fall back to not support uhs by specify no 1.8v quirk */ |
| 1120 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; |
| 1121 | } |
| 1122 | } else { |
| 1123 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; |
| 1124 | } |
| 1125 | |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1126 | err = sdhci_add_host(host); |
| 1127 | if (err) |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1128 | goto disable_clk; |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1129 | |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1130 | pm_runtime_set_active(&pdev->dev); |
| 1131 | pm_runtime_enable(&pdev->dev); |
| 1132 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
| 1133 | pm_runtime_use_autosuspend(&pdev->dev); |
| 1134 | pm_suspend_ignore_children(&pdev->dev, 1); |
| 1135 | |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1136 | return 0; |
Wolfram Sang | 7e29c30 | 2011-02-26 14:44:41 +0100 | [diff] [blame] | 1137 | |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1138 | disable_clk: |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 1139 | clk_disable_unprepare(imx_data->clk_per); |
| 1140 | clk_disable_unprepare(imx_data->clk_ipg); |
| 1141 | clk_disable_unprepare(imx_data->clk_ahb); |
Shawn Guo | e3af31c | 2012-11-26 14:39:43 +0800 | [diff] [blame] | 1142 | free_sdhci: |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1143 | sdhci_pltfm_free(pdev); |
| 1144 | return err; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1145 | } |
| 1146 | |
Bill Pemberton | 6e0ee71 | 2012-11-19 13:26:03 -0500 | [diff] [blame] | 1147 | static int sdhci_esdhc_imx_remove(struct platform_device *pdev) |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1148 | { |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1149 | struct sdhci_host *host = platform_get_drvdata(pdev); |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1150 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
Richard Zhu | e149860 | 2011-03-25 09:18:27 -0400 | [diff] [blame] | 1151 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1152 | int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
| 1153 | |
| 1154 | sdhci_remove_host(host, dead); |
Wolfram Sang | 0c6d49c | 2011-02-26 14:44:39 +0100 | [diff] [blame] | 1155 | |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1156 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
| 1157 | pm_runtime_disable(&pdev->dev); |
| 1158 | |
Dong Aisheng | a7f2be9 | 2013-12-26 15:23:54 +0800 | [diff] [blame] | 1159 | if (!IS_ENABLED(CONFIG_PM_RUNTIME)) { |
| 1160 | clk_disable_unprepare(imx_data->clk_per); |
| 1161 | clk_disable_unprepare(imx_data->clk_ipg); |
| 1162 | clk_disable_unprepare(imx_data->clk_ahb); |
| 1163 | } |
Sascha Hauer | 52dac61 | 2012-03-07 09:31:34 +0100 | [diff] [blame] | 1164 | |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1165 | sdhci_pltfm_free(pdev); |
| 1166 | |
| 1167 | return 0; |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1168 | } |
| 1169 | |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1170 | #ifdef CONFIG_PM_RUNTIME |
| 1171 | static int sdhci_esdhc_runtime_suspend(struct device *dev) |
| 1172 | { |
| 1173 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 1174 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1175 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
| 1176 | int ret; |
| 1177 | |
| 1178 | ret = sdhci_runtime_suspend_host(host); |
| 1179 | |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 1180 | if (!sdhci_sdio_irq_enabled(host)) { |
| 1181 | clk_disable_unprepare(imx_data->clk_per); |
| 1182 | clk_disable_unprepare(imx_data->clk_ipg); |
| 1183 | } |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1184 | clk_disable_unprepare(imx_data->clk_ahb); |
| 1185 | |
| 1186 | return ret; |
| 1187 | } |
| 1188 | |
| 1189 | static int sdhci_esdhc_runtime_resume(struct device *dev) |
| 1190 | { |
| 1191 | struct sdhci_host *host = dev_get_drvdata(dev); |
| 1192 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 1193 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
| 1194 | |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 1195 | if (!sdhci_sdio_irq_enabled(host)) { |
| 1196 | clk_prepare_enable(imx_data->clk_per); |
| 1197 | clk_prepare_enable(imx_data->clk_ipg); |
| 1198 | } |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1199 | clk_prepare_enable(imx_data->clk_ahb); |
| 1200 | |
| 1201 | return sdhci_runtime_resume_host(host); |
| 1202 | } |
| 1203 | #endif |
| 1204 | |
| 1205 | static const struct dev_pm_ops sdhci_esdhc_pmops = { |
| 1206 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) |
| 1207 | SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, |
| 1208 | sdhci_esdhc_runtime_resume, NULL) |
| 1209 | }; |
| 1210 | |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1211 | static struct platform_driver sdhci_esdhc_imx_driver = { |
| 1212 | .driver = { |
| 1213 | .name = "sdhci-esdhc-imx", |
| 1214 | .owner = THIS_MODULE, |
Shawn Guo | abfafc2 | 2011-06-30 15:44:44 +0800 | [diff] [blame] | 1215 | .of_match_table = imx_esdhc_dt_ids, |
Dong Aisheng | 89d7e5c | 2013-11-04 16:38:29 +0800 | [diff] [blame] | 1216 | .pm = &sdhci_esdhc_pmops, |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1217 | }, |
Shawn Guo | 57ed331 | 2011-06-30 09:24:26 +0800 | [diff] [blame] | 1218 | .id_table = imx_esdhc_devtype, |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1219 | .probe = sdhci_esdhc_imx_probe, |
Bill Pemberton | 0433c14 | 2012-11-19 13:20:26 -0500 | [diff] [blame] | 1220 | .remove = sdhci_esdhc_imx_remove, |
Wolfram Sang | 95f25ef | 2010-10-15 12:21:04 +0200 | [diff] [blame] | 1221 | }; |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1222 | |
Axel Lin | d1f81a6 | 2011-11-26 12:55:43 +0800 | [diff] [blame] | 1223 | module_platform_driver(sdhci_esdhc_imx_driver); |
Shawn Guo | 85d6509 | 2011-05-27 23:48:12 +0800 | [diff] [blame] | 1224 | |
| 1225 | MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); |
| 1226 | MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); |
| 1227 | MODULE_LICENSE("GPL v2"); |