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Steve Sakomancc175572008-10-30 21:35:26 -07001/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
Peter Ujfalusic10b82c2008-11-24 13:49:35 +020036#include <sound/tlv.h>
Steve Sakomancc175572008-10-30 21:35:26 -070037
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
Peter Ujfalusidb04e2c2009-01-27 11:29:40 +020045 0x91, /* REG_CODEC_MODE (0x1) */
Steve Sakomancc175572008-10-30 21:35:26 -070046 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
Grazvydas Ignotas5920b452008-12-02 20:48:58 +020049 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
Steve Sakomancc175572008-10-30 21:35:26 -070052 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
Peter Ujfalusif8d05bd2008-11-24 08:25:45 +020091 0x00, /* REG_SOFTVOL_CTL (0x2F) */
Steve Sakomancc175572008-10-30 21:35:26 -070092 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
Peter Ujfalusif3b5d302009-05-25 11:12:12 +0300118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
Steve Sakomancc175572008-10-30 21:35:26 -0700119};
120
Peter Ujfalusi73939582009-01-29 14:57:50 +0200121/* codec private data */
122struct twl4030_priv {
123 unsigned int bypass_state;
124 unsigned int codec_powered;
125 unsigned int codec_muted;
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +0200126
127 struct snd_pcm_substream *master_substream;
128 struct snd_pcm_substream *slave_substream;
Peter Ujfalusi6b87a912009-04-17 15:55:08 +0300129
130 unsigned int configured;
131 unsigned int rate;
132 unsigned int sample_bits;
133 unsigned int channels;
Peter Ujfalusi6943c922009-05-18 16:02:05 +0300134
135 unsigned int sysclk;
136
137 /* Headset output state handling */
138 unsigned int hsl_enabled;
139 unsigned int hsr_enabled;
Peter Ujfalusi73939582009-01-29 14:57:50 +0200140};
141
Steve Sakomancc175572008-10-30 21:35:26 -0700142/*
143 * read twl4030 register cache
144 */
145static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
146 unsigned int reg)
147{
Steve Sakomancc175572008-10-30 21:35:26 -0700148
Ian Molton91432e92009-01-17 17:44:23 +0000149 if (reg >= TWL4030_CACHEREGNUM)
150 return -EIO;
151
Steve Sakomancc175572008-10-30 21:35:26 -0700152 return cache[reg];
153}
154
155/*
156 * write twl4030 register cache
157 */
158static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
159 u8 reg, u8 value)
160{
161 u8 *cache = codec->reg_cache;
162
163 if (reg >= TWL4030_CACHEREGNUM)
164 return;
165 cache[reg] = value;
166}
167
168/*
169 * write to the twl4030 register space
170 */
171static int twl4030_write(struct snd_soc_codec *codec,
172 unsigned int reg, unsigned int value)
173{
174 twl4030_write_reg_cache(codec, reg, value);
Peter Ujfalusif3b5d302009-05-25 11:12:12 +0300175 if (likely(reg < TWL4030_REG_SW_SHADOW))
176 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
177 reg);
178 else
179 return 0;
Steve Sakomancc175572008-10-30 21:35:26 -0700180}
181
Peter Ujfalusidb04e2c2009-01-27 11:29:40 +0200182static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
Steve Sakomancc175572008-10-30 21:35:26 -0700183{
Peter Ujfalusi73939582009-01-29 14:57:50 +0200184 struct twl4030_priv *twl4030 = codec->private_data;
Steve Sakomancc175572008-10-30 21:35:26 -0700185 u8 mode;
186
Peter Ujfalusi73939582009-01-29 14:57:50 +0200187 if (enable == twl4030->codec_powered)
188 return;
189
Steve Sakomancc175572008-10-30 21:35:26 -0700190 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
Peter Ujfalusidb04e2c2009-01-27 11:29:40 +0200191 if (enable)
192 mode |= TWL4030_CODECPDZ;
193 else
194 mode &= ~TWL4030_CODECPDZ;
Steve Sakomancc175572008-10-30 21:35:26 -0700195
Peter Ujfalusidb04e2c2009-01-27 11:29:40 +0200196 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
Peter Ujfalusi73939582009-01-29 14:57:50 +0200197 twl4030->codec_powered = enable;
Steve Sakomancc175572008-10-30 21:35:26 -0700198
199 /* REVISIT: this delay is present in TI sample drivers */
200 /* but there seems to be no TRM requirement for it */
201 udelay(10);
202}
203
204static void twl4030_init_chip(struct snd_soc_codec *codec)
205{
Peter Ujfalusi16a30fb2009-05-29 09:22:37 +0300206 u8 *cache = codec->reg_cache;
Steve Sakomancc175572008-10-30 21:35:26 -0700207 int i;
208
209 /* clear CODECPDZ prior to setting register defaults */
Peter Ujfalusidb04e2c2009-01-27 11:29:40 +0200210 twl4030_codec_enable(codec, 0);
Steve Sakomancc175572008-10-30 21:35:26 -0700211
212 /* set all audio section registers to reasonable defaults */
213 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
Peter Ujfalusi16a30fb2009-05-29 09:22:37 +0300214 twl4030_write(codec, i, cache[i]);
Steve Sakomancc175572008-10-30 21:35:26 -0700215
216}
217
Peter Ujfalusi73939582009-01-29 14:57:50 +0200218static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
219{
220 struct twl4030_priv *twl4030 = codec->private_data;
221 u8 reg_val;
222
223 if (mute == twl4030->codec_muted)
224 return;
225
226 if (mute) {
227 /* Bypass the reg_cache and mute the volumes
228 * Headset mute is done in it's own event handler
229 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
230 */
231 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
232 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
233 reg_val & (~TWL4030_EAR_GAIN),
234 TWL4030_REG_EAR_CTL);
235
236 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
237 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
238 reg_val & (~TWL4030_PREDL_GAIN),
239 TWL4030_REG_PREDL_CTL);
240 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
241 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
242 reg_val & (~TWL4030_PREDR_GAIN),
243 TWL4030_REG_PREDL_CTL);
244
245 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
246 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
247 reg_val & (~TWL4030_PRECKL_GAIN),
248 TWL4030_REG_PRECKL_CTL);
249 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
250 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
Peter Ujfalusic198d812009-05-07 14:32:00 +0300251 reg_val & (~TWL4030_PRECKR_GAIN),
Peter Ujfalusi73939582009-01-29 14:57:50 +0200252 TWL4030_REG_PRECKR_CTL);
253
254 /* Disable PLL */
255 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
256 reg_val &= ~TWL4030_APLL_EN;
257 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
258 } else {
259 /* Restore the volumes
260 * Headset mute is done in it's own event handler
261 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
262 */
263 twl4030_write(codec, TWL4030_REG_EAR_CTL,
264 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
265
266 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
267 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
268 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
269 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
270
271 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
272 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
273 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
274 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
275
276 /* Enable PLL */
277 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
278 reg_val |= TWL4030_APLL_EN;
279 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
280 }
281
282 twl4030->codec_muted = mute;
283}
284
Peter Ujfalusi006f367e2009-01-27 11:29:43 +0200285static void twl4030_power_up(struct snd_soc_codec *codec)
286{
Peter Ujfalusi73939582009-01-29 14:57:50 +0200287 struct twl4030_priv *twl4030 = codec->private_data;
Peter Ujfalusi006f367e2009-01-27 11:29:43 +0200288 u8 anamicl, regmisc1, byte;
289 int i = 0;
290
Peter Ujfalusi73939582009-01-29 14:57:50 +0200291 if (twl4030->codec_powered)
292 return;
293
Peter Ujfalusi006f367e2009-01-27 11:29:43 +0200294 /* set CODECPDZ to turn on codec */
295 twl4030_codec_enable(codec, 1);
296
297 /* initiate offset cancellation */
298 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
299 twl4030_write(codec, TWL4030_REG_ANAMICL,
300 anamicl | TWL4030_CNCL_OFFSET_START);
301
302 /* wait for offset cancellation to complete */
303 do {
304 /* this takes a little while, so don't slam i2c */
305 udelay(2000);
306 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
307 TWL4030_REG_ANAMICL);
308 } while ((i++ < 100) &&
309 ((byte & TWL4030_CNCL_OFFSET_START) ==
310 TWL4030_CNCL_OFFSET_START));
311
312 /* Make sure that the reg_cache has the same value as the HW */
313 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
314
315 /* anti-pop when changing analog gain */
316 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
317 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
318 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
319
320 /* toggle CODECPDZ as per TRM */
321 twl4030_codec_enable(codec, 0);
322 twl4030_codec_enable(codec, 1);
323}
324
Peter Ujfalusi73939582009-01-29 14:57:50 +0200325/*
326 * Unconditional power down
327 */
Peter Ujfalusi006f367e2009-01-27 11:29:43 +0200328static void twl4030_power_down(struct snd_soc_codec *codec)
329{
330 /* power down */
331 twl4030_codec_enable(codec, 0);
332}
333
Peter Ujfalusi5e98a462008-12-09 12:35:47 +0200334/* Earpiece */
Joonyoung Shim1a787e72009-04-22 13:13:34 +0900335static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
336 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
337 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
338 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
339 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
340};
Peter Ujfalusi5e98a462008-12-09 12:35:47 +0200341
Peter Ujfalusi2a6f5c582008-12-09 12:35:48 +0200342/* PreDrive Left */
Joonyoung Shim1a787e72009-04-22 13:13:34 +0900343static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
344 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
345 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
346 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
347 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
348};
Peter Ujfalusi2a6f5c582008-12-09 12:35:48 +0200349
350/* PreDrive Right */
Joonyoung Shim1a787e72009-04-22 13:13:34 +0900351static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
352 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
353 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
354 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
355 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
356};
Peter Ujfalusi2a6f5c582008-12-09 12:35:48 +0200357
Peter Ujfalusidfad21a2008-12-09 12:35:49 +0200358/* Headset Left */
Joonyoung Shim1a787e72009-04-22 13:13:34 +0900359static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
360 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
361 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
362 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
363};
Peter Ujfalusidfad21a2008-12-09 12:35:49 +0200364
365/* Headset Right */
Joonyoung Shim1a787e72009-04-22 13:13:34 +0900366static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
367 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
368 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
369 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
370};
Peter Ujfalusidfad21a2008-12-09 12:35:49 +0200371
Peter Ujfalusi5152d8c2008-12-09 12:35:50 +0200372/* Carkit Left */
Joonyoung Shim1a787e72009-04-22 13:13:34 +0900373static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
374 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
375 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
376 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
377};
Peter Ujfalusi5152d8c2008-12-09 12:35:50 +0200378
379/* Carkit Right */
Joonyoung Shim1a787e72009-04-22 13:13:34 +0900380static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
381 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
382 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
383 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
384};
Peter Ujfalusi5152d8c2008-12-09 12:35:50 +0200385
Peter Ujfalusidf339802008-12-09 12:35:51 +0200386/* Handsfree Left */
387static const char *twl4030_handsfreel_texts[] =
Joonyoung Shim1a787e72009-04-22 13:13:34 +0900388 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
Peter Ujfalusidf339802008-12-09 12:35:51 +0200389
390static const struct soc_enum twl4030_handsfreel_enum =
391 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
392 ARRAY_SIZE(twl4030_handsfreel_texts),
393 twl4030_handsfreel_texts);
394
395static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
396SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
397
Peter Ujfalusi0f89bdc2009-05-25 11:12:13 +0300398/* Handsfree Left virtual mute */
399static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
400 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
401
Peter Ujfalusidf339802008-12-09 12:35:51 +0200402/* Handsfree Right */
403static const char *twl4030_handsfreer_texts[] =
Joonyoung Shim1a787e72009-04-22 13:13:34 +0900404 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
Peter Ujfalusidf339802008-12-09 12:35:51 +0200405
406static const struct soc_enum twl4030_handsfreer_enum =
407 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
408 ARRAY_SIZE(twl4030_handsfreer_texts),
409 twl4030_handsfreer_texts);
410
411static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
412SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
413
Peter Ujfalusi0f89bdc2009-05-25 11:12:13 +0300414/* Handsfree Right virtual mute */
415static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
416 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
417
Peter Ujfalusi376f7832009-05-05 08:55:47 +0300418/* Vibra */
419/* Vibra audio path selection */
420static const char *twl4030_vibra_texts[] =
421 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
422
423static const struct soc_enum twl4030_vibra_enum =
424 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
425 ARRAY_SIZE(twl4030_vibra_texts),
426 twl4030_vibra_texts);
427
428static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
429SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
430
431/* Vibra path selection: local vibrator (PWM) or audio driven */
432static const char *twl4030_vibrapath_texts[] =
433 {"Local vibrator", "Audio"};
434
435static const struct soc_enum twl4030_vibrapath_enum =
436 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
437 ARRAY_SIZE(twl4030_vibrapath_texts),
438 twl4030_vibrapath_texts);
439
440static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
441SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
442
Peter Ujfalusi276c6222008-12-31 10:08:38 +0200443/* Left analog microphone selection */
Joonyoung Shim97b80962009-05-11 20:36:08 +0900444static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
445 SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
446 SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
447 SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
448 SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
449};
Peter Ujfalusi276c6222008-12-31 10:08:38 +0200450
451/* Right analog microphone selection */
Joonyoung Shim97b80962009-05-11 20:36:08 +0900452static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
453 SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
Peter Ujfalusi181da782009-05-19 10:51:03 +0300454 SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
Joonyoung Shim97b80962009-05-11 20:36:08 +0900455};
Peter Ujfalusi276c6222008-12-31 10:08:38 +0200456
457/* TX1 L/R Analog/Digital microphone selection */
458static const char *twl4030_micpathtx1_texts[] =
459 {"Analog", "Digimic0"};
460
461static const struct soc_enum twl4030_micpathtx1_enum =
462 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
463 ARRAY_SIZE(twl4030_micpathtx1_texts),
464 twl4030_micpathtx1_texts);
465
466static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
467SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
468
469/* TX2 L/R Analog/Digital microphone selection */
470static const char *twl4030_micpathtx2_texts[] =
471 {"Analog", "Digimic1"};
472
473static const struct soc_enum twl4030_micpathtx2_enum =
474 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
475 ARRAY_SIZE(twl4030_micpathtx2_texts),
476 twl4030_micpathtx2_texts);
477
478static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
479SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
480
Peter Ujfalusi73939582009-01-29 14:57:50 +0200481/* Analog bypass for AudioR1 */
482static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
483 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
484
485/* Analog bypass for AudioL1 */
486static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
487 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
488
489/* Analog bypass for AudioR2 */
490static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
491 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
492
493/* Analog bypass for AudioL2 */
494static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
495 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
496
Lopez Cruz, Misaelfcd274a2009-04-30 21:47:22 -0500497/* Analog bypass for Voice */
498static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
499 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
500
Peter Ujfalusi6bab83f2009-02-18 14:39:05 +0200501/* Digital bypass gain, 0 mutes the bypass */
502static const unsigned int twl4030_dapm_dbypass_tlv[] = {
503 TLV_DB_RANGE_HEAD(2),
504 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
505 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
506};
507
508/* Digital bypass left (TX1L -> RX2L) */
509static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
510 SOC_DAPM_SINGLE_TLV("Volume",
511 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
512 twl4030_dapm_dbypass_tlv);
513
514/* Digital bypass right (TX1R -> RX2R) */
515static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
516 SOC_DAPM_SINGLE_TLV("Volume",
517 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
518 twl4030_dapm_dbypass_tlv);
519
Lopez Cruz, Misaelee8f6892009-04-30 21:48:08 -0500520/*
521 * Voice Sidetone GAIN volume control:
522 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
523 */
524static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
525
526/* Digital bypass voice: sidetone (VUL -> VDL)*/
527static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
528 SOC_DAPM_SINGLE_TLV("Volume",
529 TWL4030_REG_VSTPGA, 0, 0x29, 0,
530 twl4030_dapm_dbypassv_tlv);
531
Peter Ujfalusi276c6222008-12-31 10:08:38 +0200532static int micpath_event(struct snd_soc_dapm_widget *w,
533 struct snd_kcontrol *kcontrol, int event)
534{
535 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
536 unsigned char adcmicsel, micbias_ctl;
537
538 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
539 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
540 /* Prepare the bits for the given TX path:
541 * shift_l == 0: TX1 microphone path
542 * shift_l == 2: TX2 microphone path */
543 if (e->shift_l) {
544 /* TX2 microphone path */
545 if (adcmicsel & TWL4030_TX2IN_SEL)
546 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
547 else
548 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
549 } else {
550 /* TX1 microphone path */
551 if (adcmicsel & TWL4030_TX1IN_SEL)
552 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
553 else
554 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
555 }
556
557 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
558
559 return 0;
560}
561
Peter Ujfalusi5a2e9a42009-05-25 11:12:11 +0300562static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
Stanley.Miao49d92c72008-12-11 23:28:10 +0800563{
Stanley.Miao49d92c72008-12-11 23:28:10 +0800564 unsigned char hs_ctl;
565
Peter Ujfalusi5a2e9a42009-05-25 11:12:11 +0300566 hs_ctl = twl4030_read_reg_cache(codec, reg);
Stanley.Miao49d92c72008-12-11 23:28:10 +0800567
Peter Ujfalusi5a2e9a42009-05-25 11:12:11 +0300568 if (ramp) {
569 /* HF ramp-up */
570 hs_ctl |= TWL4030_HF_CTL_REF_EN;
571 twl4030_write(codec, reg, hs_ctl);
572 udelay(10);
Stanley.Miao49d92c72008-12-11 23:28:10 +0800573 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
Peter Ujfalusi5a2e9a42009-05-25 11:12:11 +0300574 twl4030_write(codec, reg, hs_ctl);
575 udelay(40);
Stanley.Miao49d92c72008-12-11 23:28:10 +0800576 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
Stanley.Miao49d92c72008-12-11 23:28:10 +0800577 hs_ctl |= TWL4030_HF_CTL_HB_EN;
Peter Ujfalusi5a2e9a42009-05-25 11:12:11 +0300578 twl4030_write(codec, reg, hs_ctl);
Stanley.Miao49d92c72008-12-11 23:28:10 +0800579 } else {
Peter Ujfalusi5a2e9a42009-05-25 11:12:11 +0300580 /* HF ramp-down */
581 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
582 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
583 twl4030_write(codec, reg, hs_ctl);
584 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
585 twl4030_write(codec, reg, hs_ctl);
586 udelay(40);
587 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
588 twl4030_write(codec, reg, hs_ctl);
Stanley.Miao49d92c72008-12-11 23:28:10 +0800589 }
Peter Ujfalusi5a2e9a42009-05-25 11:12:11 +0300590}
Stanley.Miao49d92c72008-12-11 23:28:10 +0800591
Peter Ujfalusi5a2e9a42009-05-25 11:12:11 +0300592static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
593 struct snd_kcontrol *kcontrol, int event)
594{
595 switch (event) {
596 case SND_SOC_DAPM_POST_PMU:
597 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
598 break;
599 case SND_SOC_DAPM_POST_PMD:
600 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
601 break;
602 }
603 return 0;
604}
605
606static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
607 struct snd_kcontrol *kcontrol, int event)
608{
609 switch (event) {
610 case SND_SOC_DAPM_POST_PMU:
611 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
612 break;
613 case SND_SOC_DAPM_POST_PMD:
614 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
615 break;
616 }
Stanley.Miao49d92c72008-12-11 23:28:10 +0800617 return 0;
618}
619
Peter Ujfalusi6943c922009-05-18 16:02:05 +0300620static void headset_ramp(struct snd_soc_codec *codec, int ramp)
Peter Ujfalusiaad749e2009-01-27 11:29:41 +0200621{
622 unsigned char hs_gain, hs_pop;
Peter Ujfalusi6943c922009-05-18 16:02:05 +0300623 struct twl4030_priv *twl4030 = codec->private_data;
624 /* Base values for ramp delay calculation: 2^19 - 2^26 */
625 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
626 8388608, 16777216, 33554432, 67108864};
Peter Ujfalusiaad749e2009-01-27 11:29:41 +0200627
Peter Ujfalusi6943c922009-05-18 16:02:05 +0300628 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
629 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
Peter Ujfalusiaad749e2009-01-27 11:29:41 +0200630
Peter Ujfalusi6943c922009-05-18 16:02:05 +0300631 if (ramp) {
632 /* Headset ramp-up according to the TRM */
Peter Ujfalusiaad749e2009-01-27 11:29:41 +0200633 hs_pop |= TWL4030_VMID_EN;
Peter Ujfalusi6943c922009-05-18 16:02:05 +0300634 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
635 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
Peter Ujfalusiaad749e2009-01-27 11:29:41 +0200636 hs_pop |= TWL4030_RAMP_EN;
Peter Ujfalusi6943c922009-05-18 16:02:05 +0300637 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
638 } else {
639 /* Headset ramp-down _not_ according to
640 * the TRM, but in a way that it is working */
Peter Ujfalusiaad749e2009-01-27 11:29:41 +0200641 hs_pop &= ~TWL4030_RAMP_EN;
Peter Ujfalusi6943c922009-05-18 16:02:05 +0300642 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
643 /* Wait ramp delay time + 1, so the VMID can settle */
644 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
645 twl4030->sysclk) + 1);
Peter Ujfalusiaad749e2009-01-27 11:29:41 +0200646 /* Bypass the reg_cache to mute the headset */
647 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
648 hs_gain & (~0x0f),
649 TWL4030_REG_HS_GAIN_SET);
Peter Ujfalusi6943c922009-05-18 16:02:05 +0300650
Peter Ujfalusiaad749e2009-01-27 11:29:41 +0200651 hs_pop &= ~TWL4030_VMID_EN;
Peter Ujfalusi6943c922009-05-18 16:02:05 +0300652 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
653 }
654}
655
656static int headsetlpga_event(struct snd_soc_dapm_widget *w,
657 struct snd_kcontrol *kcontrol, int event)
658{
659 struct twl4030_priv *twl4030 = w->codec->private_data;
660
661 switch (event) {
662 case SND_SOC_DAPM_POST_PMU:
663 /* Do the ramp-up only once */
664 if (!twl4030->hsr_enabled)
665 headset_ramp(w->codec, 1);
666
667 twl4030->hsl_enabled = 1;
668 break;
669 case SND_SOC_DAPM_POST_PMD:
670 /* Do the ramp-down only if both headsetL/R is disabled */
671 if (!twl4030->hsr_enabled)
672 headset_ramp(w->codec, 0);
673
674 twl4030->hsl_enabled = 0;
675 break;
676 }
677 return 0;
678}
679
680static int headsetrpga_event(struct snd_soc_dapm_widget *w,
681 struct snd_kcontrol *kcontrol, int event)
682{
683 struct twl4030_priv *twl4030 = w->codec->private_data;
684
685 switch (event) {
686 case SND_SOC_DAPM_POST_PMU:
687 /* Do the ramp-up only once */
688 if (!twl4030->hsl_enabled)
689 headset_ramp(w->codec, 1);
690
691 twl4030->hsr_enabled = 1;
692 break;
693 case SND_SOC_DAPM_POST_PMD:
694 /* Do the ramp-down only if both headsetL/R is disabled */
695 if (!twl4030->hsl_enabled)
696 headset_ramp(w->codec, 0);
697
698 twl4030->hsr_enabled = 0;
Peter Ujfalusiaad749e2009-01-27 11:29:41 +0200699 break;
700 }
701 return 0;
702}
703
Peter Ujfalusi73939582009-01-29 14:57:50 +0200704static int bypass_event(struct snd_soc_dapm_widget *w,
705 struct snd_kcontrol *kcontrol, int event)
706{
707 struct soc_mixer_control *m =
708 (struct soc_mixer_control *)w->kcontrols->private_value;
709 struct twl4030_priv *twl4030 = w->codec->private_data;
Lopez Cruz, Misaelfcd274a2009-04-30 21:47:22 -0500710 unsigned char reg, misc;
Peter Ujfalusi73939582009-01-29 14:57:50 +0200711
712 reg = twl4030_read_reg_cache(w->codec, m->reg);
Peter Ujfalusi6bab83f2009-02-18 14:39:05 +0200713
714 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
715 /* Analog bypass */
716 if (reg & (1 << m->shift))
717 twl4030->bypass_state |=
718 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
719 else
720 twl4030->bypass_state &=
721 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
Lopez Cruz, Misaelfcd274a2009-04-30 21:47:22 -0500722 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
723 /* Analog voice bypass */
724 if (reg & (1 << m->shift))
725 twl4030->bypass_state |= (1 << 4);
726 else
727 twl4030->bypass_state &= ~(1 << 4);
Lopez Cruz, Misaelee8f6892009-04-30 21:48:08 -0500728 } else if (m->reg == TWL4030_REG_VSTPGA) {
729 /* Voice digital bypass */
730 if (reg)
731 twl4030->bypass_state |= (1 << 5);
732 else
733 twl4030->bypass_state &= ~(1 << 5);
Peter Ujfalusi6bab83f2009-02-18 14:39:05 +0200734 } else {
735 /* Digital bypass */
736 if (reg & (0x7 << m->shift))
Lopez Cruz, Misaelee8f6892009-04-30 21:48:08 -0500737 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
Peter Ujfalusi6bab83f2009-02-18 14:39:05 +0200738 else
Lopez Cruz, Misaelee8f6892009-04-30 21:48:08 -0500739 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
Peter Ujfalusi6bab83f2009-02-18 14:39:05 +0200740 }
Peter Ujfalusi73939582009-01-29 14:57:50 +0200741
Lopez Cruz, Misaelfcd274a2009-04-30 21:47:22 -0500742 /* Enable master analog loopback mode if any analog switch is enabled*/
743 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
744 if (twl4030->bypass_state & 0x1F)
745 misc |= TWL4030_FMLOOP_EN;
746 else
747 misc &= ~TWL4030_FMLOOP_EN;
748 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
749
Peter Ujfalusi73939582009-01-29 14:57:50 +0200750 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
751 if (twl4030->bypass_state)
752 twl4030_codec_mute(w->codec, 0);
753 else
754 twl4030_codec_mute(w->codec, 1);
755 }
756 return 0;
757}
758
Peter Ujfalusic10b82c2008-11-24 13:49:35 +0200759/*
Peter Ujfalusib0bd53a2008-11-24 13:49:38 +0200760 * Some of the gain controls in TWL (mostly those which are associated with
761 * the outputs) are implemented in an interesting way:
762 * 0x0 : Power down (mute)
763 * 0x1 : 6dB
764 * 0x2 : 0 dB
765 * 0x3 : -6 dB
766 * Inverting not going to help with these.
767 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
768 */
769#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
770 xinvert, tlv_array) \
771{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
772 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
773 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
774 .tlv.p = (tlv_array), \
775 .info = snd_soc_info_volsw, \
776 .get = snd_soc_get_volsw_twl4030, \
777 .put = snd_soc_put_volsw_twl4030, \
778 .private_value = (unsigned long)&(struct soc_mixer_control) \
779 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
780 .max = xmax, .invert = xinvert} }
781#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
782 xinvert, tlv_array) \
783{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
784 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
785 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
786 .tlv.p = (tlv_array), \
787 .info = snd_soc_info_volsw_2r, \
788 .get = snd_soc_get_volsw_r2_twl4030,\
789 .put = snd_soc_put_volsw_r2_twl4030, \
790 .private_value = (unsigned long)&(struct soc_mixer_control) \
791 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
Mark Brown64089b82008-12-08 19:17:58 +0000792 .rshift = xshift, .max = xmax, .invert = xinvert} }
Peter Ujfalusib0bd53a2008-11-24 13:49:38 +0200793#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
794 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
795 xinvert, tlv_array)
796
797static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
798 struct snd_ctl_elem_value *ucontrol)
799{
800 struct soc_mixer_control *mc =
801 (struct soc_mixer_control *)kcontrol->private_value;
802 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
803 unsigned int reg = mc->reg;
804 unsigned int shift = mc->shift;
805 unsigned int rshift = mc->rshift;
806 int max = mc->max;
807 int mask = (1 << fls(max)) - 1;
808
809 ucontrol->value.integer.value[0] =
810 (snd_soc_read(codec, reg) >> shift) & mask;
811 if (ucontrol->value.integer.value[0])
812 ucontrol->value.integer.value[0] =
813 max + 1 - ucontrol->value.integer.value[0];
814
815 if (shift != rshift) {
816 ucontrol->value.integer.value[1] =
817 (snd_soc_read(codec, reg) >> rshift) & mask;
818 if (ucontrol->value.integer.value[1])
819 ucontrol->value.integer.value[1] =
820 max + 1 - ucontrol->value.integer.value[1];
821 }
822
823 return 0;
824}
825
826static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
827 struct snd_ctl_elem_value *ucontrol)
828{
829 struct soc_mixer_control *mc =
830 (struct soc_mixer_control *)kcontrol->private_value;
831 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
832 unsigned int reg = mc->reg;
833 unsigned int shift = mc->shift;
834 unsigned int rshift = mc->rshift;
835 int max = mc->max;
836 int mask = (1 << fls(max)) - 1;
837 unsigned short val, val2, val_mask;
838
839 val = (ucontrol->value.integer.value[0] & mask);
840
841 val_mask = mask << shift;
842 if (val)
843 val = max + 1 - val;
844 val = val << shift;
845 if (shift != rshift) {
846 val2 = (ucontrol->value.integer.value[1] & mask);
847 val_mask |= mask << rshift;
848 if (val2)
849 val2 = max + 1 - val2;
850 val |= val2 << rshift;
851 }
852 return snd_soc_update_bits(codec, reg, val_mask, val);
853}
854
855static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
856 struct snd_ctl_elem_value *ucontrol)
857{
858 struct soc_mixer_control *mc =
859 (struct soc_mixer_control *)kcontrol->private_value;
860 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
861 unsigned int reg = mc->reg;
862 unsigned int reg2 = mc->rreg;
863 unsigned int shift = mc->shift;
864 int max = mc->max;
865 int mask = (1<<fls(max))-1;
866
867 ucontrol->value.integer.value[0] =
868 (snd_soc_read(codec, reg) >> shift) & mask;
869 ucontrol->value.integer.value[1] =
870 (snd_soc_read(codec, reg2) >> shift) & mask;
871
872 if (ucontrol->value.integer.value[0])
873 ucontrol->value.integer.value[0] =
874 max + 1 - ucontrol->value.integer.value[0];
875 if (ucontrol->value.integer.value[1])
876 ucontrol->value.integer.value[1] =
877 max + 1 - ucontrol->value.integer.value[1];
878
879 return 0;
880}
881
882static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
883 struct snd_ctl_elem_value *ucontrol)
884{
885 struct soc_mixer_control *mc =
886 (struct soc_mixer_control *)kcontrol->private_value;
887 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
888 unsigned int reg = mc->reg;
889 unsigned int reg2 = mc->rreg;
890 unsigned int shift = mc->shift;
891 int max = mc->max;
892 int mask = (1 << fls(max)) - 1;
893 int err;
894 unsigned short val, val2, val_mask;
895
896 val_mask = mask << shift;
897 val = (ucontrol->value.integer.value[0] & mask);
898 val2 = (ucontrol->value.integer.value[1] & mask);
899
900 if (val)
901 val = max + 1 - val;
902 if (val2)
903 val2 = max + 1 - val2;
904
905 val = val << shift;
906 val2 = val2 << shift;
907
908 err = snd_soc_update_bits(codec, reg, val_mask, val);
909 if (err < 0)
910 return err;
911
912 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
913 return err;
914}
915
Lopez Cruz, Misaelb74bd402009-05-18 11:52:55 -0500916/* Codec operation modes */
917static const char *twl4030_op_modes_texts[] = {
918 "Option 2 (voice/audio)", "Option 1 (audio)"
919};
920
921static const struct soc_enum twl4030_op_modes_enum =
922 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
923 ARRAY_SIZE(twl4030_op_modes_texts),
924 twl4030_op_modes_texts);
925
926int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
927 struct snd_ctl_elem_value *ucontrol)
928{
929 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
930 struct twl4030_priv *twl4030 = codec->private_data;
931 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
932 unsigned short val;
933 unsigned short mask, bitmask;
934
935 if (twl4030->configured) {
936 printk(KERN_ERR "twl4030 operation mode cannot be "
937 "changed on-the-fly\n");
938 return -EBUSY;
939 }
940
941 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
942 ;
943 if (ucontrol->value.enumerated.item[0] > e->max - 1)
944 return -EINVAL;
945
946 val = ucontrol->value.enumerated.item[0] << e->shift_l;
947 mask = (bitmask - 1) << e->shift_l;
948 if (e->shift_l != e->shift_r) {
949 if (ucontrol->value.enumerated.item[1] > e->max - 1)
950 return -EINVAL;
951 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
952 mask |= (bitmask - 1) << e->shift_r;
953 }
954
955 return snd_soc_update_bits(codec, e->reg, mask, val);
956}
957
Peter Ujfalusib0bd53a2008-11-24 13:49:38 +0200958/*
Peter Ujfalusic10b82c2008-11-24 13:49:35 +0200959 * FGAIN volume control:
960 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
961 */
Peter Ujfalusid889a722008-12-01 10:03:46 +0200962static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
Peter Ujfalusic10b82c2008-11-24 13:49:35 +0200963
Peter Ujfalusi0d33ea02008-11-24 13:49:36 +0200964/*
965 * CGAIN volume control:
966 * 0 dB to 12 dB in 6 dB steps
967 * value 2 and 3 means 12 dB
968 */
Peter Ujfalusid889a722008-12-01 10:03:46 +0200969static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
970
971/*
Joonyoung Shim1a787e72009-04-22 13:13:34 +0900972 * Voice Downlink GAIN volume control:
973 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
974 */
975static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
976
977/*
Peter Ujfalusid889a722008-12-01 10:03:46 +0200978 * Analog playback gain
979 * -24 dB to 12 dB in 2 dB steps
980 */
981static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
Peter Ujfalusi0d33ea02008-11-24 13:49:36 +0200982
Peter Ujfalusi381a22b2008-12-01 10:03:45 +0200983/*
Peter Ujfalusi42902392008-12-01 10:03:47 +0200984 * Gain controls tied to outputs
985 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
986 */
987static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
988
989/*
Joonyoung Shim18cc8d82009-04-28 18:18:05 +0900990 * Gain control for earpiece amplifier
991 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
992 */
993static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
994
995/*
Peter Ujfalusi381a22b2008-12-01 10:03:45 +0200996 * Capture gain after the ADCs
997 * from 0 dB to 31 dB in 1 dB steps
998 */
999static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1000
Grazvydas Ignotas5920b452008-12-02 20:48:58 +02001001/*
1002 * Gain control for input amplifiers
1003 * 0 dB to 30 dB in 6 dB steps
1004 */
1005static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1006
Peter Ujfalusi89492be2009-03-05 12:48:49 +02001007static const char *twl4030_rampdelay_texts[] = {
1008 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1009 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1010 "3495/2581/1748 ms"
1011};
1012
1013static const struct soc_enum twl4030_rampdelay_enum =
1014 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1015 ARRAY_SIZE(twl4030_rampdelay_texts),
1016 twl4030_rampdelay_texts);
1017
Peter Ujfalusi376f7832009-05-05 08:55:47 +03001018/* Vibra H-bridge direction mode */
1019static const char *twl4030_vibradirmode_texts[] = {
1020 "Vibra H-bridge direction", "Audio data MSB",
1021};
1022
1023static const struct soc_enum twl4030_vibradirmode_enum =
1024 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1025 ARRAY_SIZE(twl4030_vibradirmode_texts),
1026 twl4030_vibradirmode_texts);
1027
1028/* Vibra H-bridge direction */
1029static const char *twl4030_vibradir_texts[] = {
1030 "Positive polarity", "Negative polarity",
1031};
1032
1033static const struct soc_enum twl4030_vibradir_enum =
1034 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1035 ARRAY_SIZE(twl4030_vibradir_texts),
1036 twl4030_vibradir_texts);
1037
Steve Sakomancc175572008-10-30 21:35:26 -07001038static const struct snd_kcontrol_new twl4030_snd_controls[] = {
Lopez Cruz, Misaelb74bd402009-05-18 11:52:55 -05001039 /* Codec operation mode control */
1040 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1041 snd_soc_get_enum_double,
1042 snd_soc_put_twl4030_opmode_enum_double),
1043
Peter Ujfalusid889a722008-12-01 10:03:46 +02001044 /* Common playback gain controls */
1045 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1046 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1047 0, 0x3f, 0, digital_fine_tlv),
1048 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1049 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1050 0, 0x3f, 0, digital_fine_tlv),
1051
1052 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1053 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1054 6, 0x2, 0, digital_coarse_tlv),
1055 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1056 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1057 6, 0x2, 0, digital_coarse_tlv),
1058
1059 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1060 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1061 3, 0x12, 1, analog_tlv),
1062 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1063 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1064 3, 0x12, 1, analog_tlv),
Peter Ujfalusi44c55872008-12-09 08:45:44 +02001065 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1066 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1067 1, 1, 0),
1068 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1069 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1070 1, 1, 0),
Peter Ujfalusi381a22b2008-12-01 10:03:45 +02001071
Joonyoung Shim1a787e72009-04-22 13:13:34 +09001072 /* Common voice downlink gain controls */
1073 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1074 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1075
1076 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1077 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1078
1079 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1080 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1081
Peter Ujfalusi42902392008-12-01 10:03:47 +02001082 /* Separate output gain controls */
1083 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1084 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1085 4, 3, 0, output_tvl),
1086
1087 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1088 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1089
1090 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1091 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1092 4, 3, 0, output_tvl),
1093
1094 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
Joonyoung Shim18cc8d82009-04-28 18:18:05 +09001095 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
Peter Ujfalusi42902392008-12-01 10:03:47 +02001096
Peter Ujfalusi381a22b2008-12-01 10:03:45 +02001097 /* Common capture gain controls */
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001098 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
Peter Ujfalusi381a22b2008-12-01 10:03:45 +02001099 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1100 0, 0x1f, 0, digital_capture_tlv),
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001101 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1102 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1103 0, 0x1f, 0, digital_capture_tlv),
Grazvydas Ignotas5920b452008-12-02 20:48:58 +02001104
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001105 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
Grazvydas Ignotas5920b452008-12-02 20:48:58 +02001106 0, 3, 5, 0, input_gain_tlv),
Peter Ujfalusi89492be2009-03-05 12:48:49 +02001107
1108 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
Peter Ujfalusi376f7832009-05-05 08:55:47 +03001109
1110 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1111 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
Steve Sakomancc175572008-10-30 21:35:26 -07001112};
1113
Steve Sakomancc175572008-10-30 21:35:26 -07001114static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001115 /* Left channel inputs */
1116 SND_SOC_DAPM_INPUT("MAINMIC"),
1117 SND_SOC_DAPM_INPUT("HSMIC"),
1118 SND_SOC_DAPM_INPUT("AUXL"),
1119 SND_SOC_DAPM_INPUT("CARKITMIC"),
1120 /* Right channel inputs */
1121 SND_SOC_DAPM_INPUT("SUBMIC"),
1122 SND_SOC_DAPM_INPUT("AUXR"),
1123 /* Digital microphones (Stereo) */
1124 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1125 SND_SOC_DAPM_INPUT("DIGIMIC1"),
Steve Sakomancc175572008-10-30 21:35:26 -07001126
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001127 /* Outputs */
Steve Sakomancc175572008-10-30 21:35:26 -07001128 SND_SOC_DAPM_OUTPUT("OUTL"),
1129 SND_SOC_DAPM_OUTPUT("OUTR"),
Peter Ujfalusi5e98a462008-12-09 12:35:47 +02001130 SND_SOC_DAPM_OUTPUT("EARPIECE"),
Peter Ujfalusi2a6f5c582008-12-09 12:35:48 +02001131 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1132 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
Peter Ujfalusidfad21a2008-12-09 12:35:49 +02001133 SND_SOC_DAPM_OUTPUT("HSOL"),
1134 SND_SOC_DAPM_OUTPUT("HSOR"),
Peter Ujfalusi6a1bee42008-12-10 12:51:46 +02001135 SND_SOC_DAPM_OUTPUT("CARKITL"),
1136 SND_SOC_DAPM_OUTPUT("CARKITR"),
Peter Ujfalusidf339802008-12-09 12:35:51 +02001137 SND_SOC_DAPM_OUTPUT("HFL"),
1138 SND_SOC_DAPM_OUTPUT("HFR"),
Peter Ujfalusi376f7832009-05-05 08:55:47 +03001139 SND_SOC_DAPM_OUTPUT("VIBRA"),
Steve Sakomancc175572008-10-30 21:35:26 -07001140
Peter Ujfalusi53b50472008-12-09 08:45:43 +02001141 /* DACs */
Peter Ujfalusib4852b72009-05-22 15:12:15 +03001142 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
Peter Ujfalusi73939582009-01-29 14:57:50 +02001143 SND_SOC_NOPM, 0, 0),
Peter Ujfalusib4852b72009-05-22 15:12:15 +03001144 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
Peter Ujfalusi73939582009-01-29 14:57:50 +02001145 SND_SOC_NOPM, 0, 0),
Peter Ujfalusib4852b72009-05-22 15:12:15 +03001146 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
Peter Ujfalusi73939582009-01-29 14:57:50 +02001147 SND_SOC_NOPM, 0, 0),
Peter Ujfalusib4852b72009-05-22 15:12:15 +03001148 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
Peter Ujfalusi73939582009-01-29 14:57:50 +02001149 SND_SOC_NOPM, 0, 0),
Joonyoung Shim1a787e72009-04-22 13:13:34 +09001150 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
Lopez Cruz, Misaelfcd274a2009-04-30 21:47:22 -05001151 SND_SOC_NOPM, 0, 0),
Steve Sakomancc175572008-10-30 21:35:26 -07001152
Peter Ujfalusi73939582009-01-29 14:57:50 +02001153 /* Analog bypasses */
1154 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1155 &twl4030_dapm_abypassr1_control, bypass_event,
1156 SND_SOC_DAPM_POST_REG),
1157 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1158 &twl4030_dapm_abypassl1_control,
1159 bypass_event, SND_SOC_DAPM_POST_REG),
1160 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1161 &twl4030_dapm_abypassr2_control,
1162 bypass_event, SND_SOC_DAPM_POST_REG),
1163 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1164 &twl4030_dapm_abypassl2_control,
1165 bypass_event, SND_SOC_DAPM_POST_REG),
Lopez Cruz, Misaelfcd274a2009-04-30 21:47:22 -05001166 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1167 &twl4030_dapm_abypassv_control,
1168 bypass_event, SND_SOC_DAPM_POST_REG),
Peter Ujfalusi73939582009-01-29 14:57:50 +02001169
Peter Ujfalusi6bab83f2009-02-18 14:39:05 +02001170 /* Digital bypasses */
1171 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1172 &twl4030_dapm_dbypassl_control, bypass_event,
1173 SND_SOC_DAPM_POST_REG),
1174 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1175 &twl4030_dapm_dbypassr_control, bypass_event,
1176 SND_SOC_DAPM_POST_REG),
Lopez Cruz, Misaelee8f6892009-04-30 21:48:08 -05001177 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1178 &twl4030_dapm_dbypassv_control, bypass_event,
1179 SND_SOC_DAPM_POST_REG),
Peter Ujfalusi6bab83f2009-02-18 14:39:05 +02001180
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001181 /* Digital mixers, power control for the physical DACs */
1182 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1183 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1184 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1185 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1186 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1187 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1188 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1189 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1190 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1191 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1192
1193 /* Analog mixers, power control for the physical PGAs */
1194 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1195 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1196 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1197 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1198 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1199 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1200 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1201 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1202 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1203 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
Peter Ujfalusi73939582009-01-29 14:57:50 +02001204
Joonyoung Shim1a787e72009-04-22 13:13:34 +09001205 /* Output MIXER controls */
Peter Ujfalusi5e98a462008-12-09 12:35:47 +02001206 /* Earpiece */
Joonyoung Shim1a787e72009-04-22 13:13:34 +09001207 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1208 &twl4030_dapm_earpiece_controls[0],
1209 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
Peter Ujfalusi2a6f5c582008-12-09 12:35:48 +02001210 /* PreDrivL/R */
Joonyoung Shim1a787e72009-04-22 13:13:34 +09001211 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1212 &twl4030_dapm_predrivel_controls[0],
1213 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1214 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1215 &twl4030_dapm_predriver_controls[0],
1216 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
Peter Ujfalusidfad21a2008-12-09 12:35:49 +02001217 /* HeadsetL/R */
Peter Ujfalusi6943c922009-05-18 16:02:05 +03001218 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
Joonyoung Shim1a787e72009-04-22 13:13:34 +09001219 &twl4030_dapm_hsol_controls[0],
Peter Ujfalusi6943c922009-05-18 16:02:05 +03001220 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1221 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1222 0, 0, NULL, 0, headsetlpga_event,
Joonyoung Shim1a787e72009-04-22 13:13:34 +09001223 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1224 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1225 &twl4030_dapm_hsor_controls[0],
1226 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
Peter Ujfalusi6943c922009-05-18 16:02:05 +03001227 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1228 0, 0, NULL, 0, headsetrpga_event,
1229 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
Peter Ujfalusi5152d8c2008-12-09 12:35:50 +02001230 /* CarkitL/R */
Joonyoung Shim1a787e72009-04-22 13:13:34 +09001231 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1232 &twl4030_dapm_carkitl_controls[0],
1233 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1234 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1235 &twl4030_dapm_carkitr_controls[0],
1236 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1237
1238 /* Output MUX controls */
Peter Ujfalusidf339802008-12-09 12:35:51 +02001239 /* HandsfreeL/R */
Peter Ujfalusi5a2e9a42009-05-25 11:12:11 +03001240 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1241 &twl4030_dapm_handsfreel_control),
Peter Ujfalusi0f89bdc2009-05-25 11:12:13 +03001242 SND_SOC_DAPM_SWITCH("HandsfreeL Switch", SND_SOC_NOPM, 0, 0,
1243 &twl4030_dapm_handsfreelmute_control),
Peter Ujfalusi5a2e9a42009-05-25 11:12:11 +03001244 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1245 0, 0, NULL, 0, handsfreelpga_event,
1246 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1247 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1248 &twl4030_dapm_handsfreer_control),
Peter Ujfalusi0f89bdc2009-05-25 11:12:13 +03001249 SND_SOC_DAPM_SWITCH("HandsfreeR Switch", SND_SOC_NOPM, 0, 0,
1250 &twl4030_dapm_handsfreermute_control),
Peter Ujfalusi5a2e9a42009-05-25 11:12:11 +03001251 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1252 0, 0, NULL, 0, handsfreerpga_event,
1253 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
Peter Ujfalusi376f7832009-05-05 08:55:47 +03001254 /* Vibra */
1255 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1256 &twl4030_dapm_vibra_control),
1257 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1258 &twl4030_dapm_vibrapath_control),
Peter Ujfalusi5e98a462008-12-09 12:35:47 +02001259
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001260 /* Introducing four virtual ADC, since TWL4030 have four channel for
1261 capture */
1262 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1263 SND_SOC_NOPM, 0, 0),
1264 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1265 SND_SOC_NOPM, 0, 0),
1266 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1267 SND_SOC_NOPM, 0, 0),
1268 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1269 SND_SOC_NOPM, 0, 0),
1270
1271 /* Analog/Digital mic path selection.
1272 TX1 Left/Right: either analog Left/Right or Digimic0
1273 TX2 Left/Right: either analog Left/Right or Digimic1 */
1274 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1275 &twl4030_dapm_micpathtx1_control, micpath_event,
1276 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1277 SND_SOC_DAPM_POST_REG),
1278 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1279 &twl4030_dapm_micpathtx2_control, micpath_event,
1280 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1281 SND_SOC_DAPM_POST_REG),
1282
Joonyoung Shim97b80962009-05-11 20:36:08 +09001283 /* Analog input mixers for the capture amplifiers */
1284 SND_SOC_DAPM_MIXER("Analog Left Capture Route",
1285 TWL4030_REG_ANAMICL, 4, 0,
1286 &twl4030_dapm_analoglmic_controls[0],
1287 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1288 SND_SOC_DAPM_MIXER("Analog Right Capture Route",
1289 TWL4030_REG_ANAMICR, 4, 0,
1290 &twl4030_dapm_analogrmic_controls[0],
1291 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001292
Peter Ujfalusifb2a2f82009-01-27 11:29:42 +02001293 SND_SOC_DAPM_PGA("ADC Physical Left",
1294 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1295 SND_SOC_DAPM_PGA("ADC Physical Right",
1296 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001297
1298 SND_SOC_DAPM_PGA("Digimic0 Enable",
1299 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1300 SND_SOC_DAPM_PGA("Digimic1 Enable",
1301 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1302
1303 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1304 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1305 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
Peter Ujfalusi73939582009-01-29 14:57:50 +02001306
Steve Sakomancc175572008-10-30 21:35:26 -07001307};
1308
1309static const struct snd_soc_dapm_route intercon[] = {
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001310 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1311 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1312 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1313 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1314 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
Peter Ujfalusi73939582009-01-29 14:57:50 +02001315
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001316 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1317 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1318 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1319 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1320 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
Joonyoung Shim1a787e72009-04-22 13:13:34 +09001321
Peter Ujfalusi5e98a462008-12-09 12:35:47 +02001322 /* Internal playback routings */
1323 /* Earpiece */
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001324 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1325 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1326 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1327 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
Peter Ujfalusi2a6f5c582008-12-09 12:35:48 +02001328 /* PreDrivL */
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001329 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1330 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1331 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1332 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
Peter Ujfalusi2a6f5c582008-12-09 12:35:48 +02001333 /* PreDrivR */
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001334 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1335 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1336 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1337 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
Peter Ujfalusidfad21a2008-12-09 12:35:49 +02001338 /* HeadsetL */
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001339 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1340 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1341 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
Peter Ujfalusi6943c922009-05-18 16:02:05 +03001342 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
Peter Ujfalusidfad21a2008-12-09 12:35:49 +02001343 /* HeadsetR */
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001344 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1345 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1346 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
Peter Ujfalusi6943c922009-05-18 16:02:05 +03001347 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
Peter Ujfalusi5152d8c2008-12-09 12:35:50 +02001348 /* CarkitL */
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001349 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1350 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1351 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
Peter Ujfalusi5152d8c2008-12-09 12:35:50 +02001352 /* CarkitR */
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001353 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1354 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1355 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
Peter Ujfalusidf339802008-12-09 12:35:51 +02001356 /* HandsfreeL */
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001357 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1358 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1359 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1360 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
Peter Ujfalusi0f89bdc2009-05-25 11:12:13 +03001361 {"HandsfreeL Switch", "Switch", "HandsfreeL Mux"},
1362 {"HandsfreeL PGA", NULL, "HandsfreeL Switch"},
Peter Ujfalusidf339802008-12-09 12:35:51 +02001363 /* HandsfreeR */
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001364 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1365 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1366 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1367 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
Peter Ujfalusi0f89bdc2009-05-25 11:12:13 +03001368 {"HandsfreeR Switch", "Switch", "HandsfreeR Mux"},
1369 {"HandsfreeR PGA", NULL, "HandsfreeR Switch"},
Peter Ujfalusi376f7832009-05-05 08:55:47 +03001370 /* Vibra */
1371 {"Vibra Mux", "AudioL1", "DAC Left1"},
1372 {"Vibra Mux", "AudioR1", "DAC Right1"},
1373 {"Vibra Mux", "AudioL2", "DAC Left2"},
1374 {"Vibra Mux", "AudioR2", "DAC Right2"},
Peter Ujfalusi5e98a462008-12-09 12:35:47 +02001375
Steve Sakomancc175572008-10-30 21:35:26 -07001376 /* outputs */
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001377 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1378 {"OUTR", NULL, "Analog R2 Playback Mixer"},
Joonyoung Shim1a787e72009-04-22 13:13:34 +09001379 {"EARPIECE", NULL, "Earpiece Mixer"},
1380 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1381 {"PREDRIVER", NULL, "PredriveR Mixer"},
Peter Ujfalusi6943c922009-05-18 16:02:05 +03001382 {"HSOL", NULL, "HeadsetL PGA"},
1383 {"HSOR", NULL, "HeadsetR PGA"},
Joonyoung Shim1a787e72009-04-22 13:13:34 +09001384 {"CARKITL", NULL, "CarkitL Mixer"},
1385 {"CARKITR", NULL, "CarkitR Mixer"},
Peter Ujfalusi5a2e9a42009-05-25 11:12:11 +03001386 {"HFL", NULL, "HandsfreeL PGA"},
1387 {"HFR", NULL, "HandsfreeR PGA"},
Peter Ujfalusi376f7832009-05-05 08:55:47 +03001388 {"Vibra Route", "Audio", "Vibra Mux"},
1389 {"VIBRA", NULL, "Vibra Route"},
Steve Sakomancc175572008-10-30 21:35:26 -07001390
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001391 /* Capture path */
1392 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1393 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1394 {"Analog Left Capture Route", "AUXL", "AUXL"},
1395 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1396
1397 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1398 {"Analog Right Capture Route", "AUXR", "AUXR"},
1399
Peter Ujfalusifb2a2f82009-01-27 11:29:42 +02001400 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1401 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001402
1403 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1404 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1405
1406 /* TX1 Left capture path */
Peter Ujfalusifb2a2f82009-01-27 11:29:42 +02001407 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001408 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1409 /* TX1 Right capture path */
Peter Ujfalusifb2a2f82009-01-27 11:29:42 +02001410 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001411 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1412 /* TX2 Left capture path */
Peter Ujfalusifb2a2f82009-01-27 11:29:42 +02001413 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001414 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1415 /* TX2 Right capture path */
Peter Ujfalusifb2a2f82009-01-27 11:29:42 +02001416 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
Peter Ujfalusi276c6222008-12-31 10:08:38 +02001417 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1418
1419 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1420 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1421 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1422 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1423
Peter Ujfalusi73939582009-01-29 14:57:50 +02001424 /* Analog bypass routes */
1425 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1426 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1427 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1428 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
Lopez Cruz, Misaelfcd274a2009-04-30 21:47:22 -05001429 {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
Peter Ujfalusi73939582009-01-29 14:57:50 +02001430
1431 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1432 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1433 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1434 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
Lopez Cruz, Misaelfcd274a2009-04-30 21:47:22 -05001435 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
Peter Ujfalusi73939582009-01-29 14:57:50 +02001436
Peter Ujfalusi6bab83f2009-02-18 14:39:05 +02001437 /* Digital bypass routes */
1438 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1439 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
Lopez Cruz, Misaelee8f6892009-04-30 21:48:08 -05001440 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
Peter Ujfalusi6bab83f2009-02-18 14:39:05 +02001441
Peter Ujfalusi4005d392009-05-18 16:02:04 +03001442 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1443 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1444 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
Peter Ujfalusi6bab83f2009-02-18 14:39:05 +02001445
Steve Sakomancc175572008-10-30 21:35:26 -07001446};
1447
1448static int twl4030_add_widgets(struct snd_soc_codec *codec)
1449{
1450 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1451 ARRAY_SIZE(twl4030_dapm_widgets));
1452
1453 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1454
1455 snd_soc_dapm_new_widgets(codec);
1456 return 0;
1457}
1458
Steve Sakomancc175572008-10-30 21:35:26 -07001459static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1460 enum snd_soc_bias_level level)
1461{
Peter Ujfalusi73939582009-01-29 14:57:50 +02001462 struct twl4030_priv *twl4030 = codec->private_data;
1463
Steve Sakomancc175572008-10-30 21:35:26 -07001464 switch (level) {
1465 case SND_SOC_BIAS_ON:
Peter Ujfalusi73939582009-01-29 14:57:50 +02001466 twl4030_codec_mute(codec, 0);
Steve Sakomancc175572008-10-30 21:35:26 -07001467 break;
1468 case SND_SOC_BIAS_PREPARE:
Peter Ujfalusi73939582009-01-29 14:57:50 +02001469 twl4030_power_up(codec);
1470 if (twl4030->bypass_state)
1471 twl4030_codec_mute(codec, 0);
1472 else
1473 twl4030_codec_mute(codec, 1);
Steve Sakomancc175572008-10-30 21:35:26 -07001474 break;
1475 case SND_SOC_BIAS_STANDBY:
Peter Ujfalusi73939582009-01-29 14:57:50 +02001476 twl4030_power_up(codec);
1477 if (twl4030->bypass_state)
1478 twl4030_codec_mute(codec, 0);
1479 else
1480 twl4030_codec_mute(codec, 1);
Steve Sakomancc175572008-10-30 21:35:26 -07001481 break;
1482 case SND_SOC_BIAS_OFF:
1483 twl4030_power_down(codec);
1484 break;
1485 }
1486 codec->bias_level = level;
1487
1488 return 0;
1489}
1490
Peter Ujfalusi6b87a912009-04-17 15:55:08 +03001491static void twl4030_constraints(struct twl4030_priv *twl4030,
1492 struct snd_pcm_substream *mst_substream)
1493{
1494 struct snd_pcm_substream *slv_substream;
1495
1496 /* Pick the stream, which need to be constrained */
1497 if (mst_substream == twl4030->master_substream)
1498 slv_substream = twl4030->slave_substream;
1499 else if (mst_substream == twl4030->slave_substream)
1500 slv_substream = twl4030->master_substream;
1501 else /* This should not happen.. */
1502 return;
1503
1504 /* Set the constraints according to the already configured stream */
1505 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1506 SNDRV_PCM_HW_PARAM_RATE,
1507 twl4030->rate,
1508 twl4030->rate);
1509
1510 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1511 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1512 twl4030->sample_bits,
1513 twl4030->sample_bits);
1514
1515 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1516 SNDRV_PCM_HW_PARAM_CHANNELS,
1517 twl4030->channels,
1518 twl4030->channels);
1519}
1520
Peter Ujfalusi8a1f9362009-04-23 14:36:49 +03001521/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1522 * capture has to be enabled/disabled. */
1523static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1524 int enable)
1525{
1526 u8 reg, mask;
1527
1528 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1529
1530 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1531 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1532 else
1533 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1534
1535 if (enable)
1536 reg |= mask;
1537 else
1538 reg &= ~mask;
1539
1540 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1541}
1542
Peter Ujfalusid6648da2009-04-07 09:14:00 +03001543static int twl4030_startup(struct snd_pcm_substream *substream,
1544 struct snd_soc_dai *dai)
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +02001545{
1546 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1547 struct snd_soc_device *socdev = rtd->socdev;
Peter Ujfalusid6648da2009-04-07 09:14:00 +03001548 struct snd_soc_codec *codec = socdev->card->codec;
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +02001549 struct twl4030_priv *twl4030 = codec->private_data;
1550
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +02001551 if (twl4030->master_substream) {
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +02001552 twl4030->slave_substream = substream;
Peter Ujfalusi6b87a912009-04-17 15:55:08 +03001553 /* The DAI has one configuration for playback and capture, so
1554 * if the DAI has been already configured then constrain this
1555 * substream to match it. */
1556 if (twl4030->configured)
1557 twl4030_constraints(twl4030, twl4030->master_substream);
1558 } else {
Peter Ujfalusi8a1f9362009-04-23 14:36:49 +03001559 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1560 TWL4030_OPTION_1)) {
1561 /* In option2 4 channel is not supported, set the
1562 * constraint for the first stream for channels, the
1563 * second stream will 'inherit' this cosntraint */
1564 snd_pcm_hw_constraint_minmax(substream->runtime,
1565 SNDRV_PCM_HW_PARAM_CHANNELS,
1566 2, 2);
1567 }
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +02001568 twl4030->master_substream = substream;
Peter Ujfalusi6b87a912009-04-17 15:55:08 +03001569 }
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +02001570
1571 return 0;
1572}
1573
Peter Ujfalusid6648da2009-04-07 09:14:00 +03001574static void twl4030_shutdown(struct snd_pcm_substream *substream,
1575 struct snd_soc_dai *dai)
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +02001576{
1577 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1578 struct snd_soc_device *socdev = rtd->socdev;
Peter Ujfalusid6648da2009-04-07 09:14:00 +03001579 struct snd_soc_codec *codec = socdev->card->codec;
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +02001580 struct twl4030_priv *twl4030 = codec->private_data;
1581
1582 if (twl4030->master_substream == substream)
1583 twl4030->master_substream = twl4030->slave_substream;
1584
1585 twl4030->slave_substream = NULL;
Peter Ujfalusi6b87a912009-04-17 15:55:08 +03001586
1587 /* If all streams are closed, or the remaining stream has not yet
1588 * been configured than set the DAI as not configured. */
1589 if (!twl4030->master_substream)
1590 twl4030->configured = 0;
1591 else if (!twl4030->master_substream->runtime->channels)
1592 twl4030->configured = 0;
Peter Ujfalusi8a1f9362009-04-23 14:36:49 +03001593
1594 /* If the closing substream had 4 channel, do the necessary cleanup */
1595 if (substream->runtime->channels == 4)
1596 twl4030_tdm_enable(codec, substream->stream, 0);
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +02001597}
1598
Steve Sakomancc175572008-10-30 21:35:26 -07001599static int twl4030_hw_params(struct snd_pcm_substream *substream,
Mark Browndee89c42008-11-18 22:11:38 +00001600 struct snd_pcm_hw_params *params,
1601 struct snd_soc_dai *dai)
Steve Sakomancc175572008-10-30 21:35:26 -07001602{
1603 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1604 struct snd_soc_device *socdev = rtd->socdev;
Mark Brown6627a652009-01-23 22:55:23 +00001605 struct snd_soc_codec *codec = socdev->card->codec;
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +02001606 struct twl4030_priv *twl4030 = codec->private_data;
Steve Sakomancc175572008-10-30 21:35:26 -07001607 u8 mode, old_mode, format, old_format;
1608
Peter Ujfalusi8a1f9362009-04-23 14:36:49 +03001609 /* If the substream has 4 channel, do the necessary setup */
1610 if (params_channels(params) == 4) {
1611 /* Safety check: are we in the correct operating mode? */
1612 if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1613 TWL4030_OPTION_1))
1614 twl4030_tdm_enable(codec, substream->stream, 1);
1615 else
1616 return -EINVAL;
1617 }
1618
Peter Ujfalusi6b87a912009-04-17 15:55:08 +03001619 if (twl4030->configured)
1620 /* Ignoring hw_params for already configured DAI */
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +02001621 return 0;
1622
Steve Sakomancc175572008-10-30 21:35:26 -07001623 /* bit rate */
1624 old_mode = twl4030_read_reg_cache(codec,
1625 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1626 mode = old_mode & ~TWL4030_APLL_RATE;
1627
1628 switch (params_rate(params)) {
1629 case 8000:
1630 mode |= TWL4030_APLL_RATE_8000;
1631 break;
1632 case 11025:
1633 mode |= TWL4030_APLL_RATE_11025;
1634 break;
1635 case 12000:
1636 mode |= TWL4030_APLL_RATE_12000;
1637 break;
1638 case 16000:
1639 mode |= TWL4030_APLL_RATE_16000;
1640 break;
1641 case 22050:
1642 mode |= TWL4030_APLL_RATE_22050;
1643 break;
1644 case 24000:
1645 mode |= TWL4030_APLL_RATE_24000;
1646 break;
1647 case 32000:
1648 mode |= TWL4030_APLL_RATE_32000;
1649 break;
1650 case 44100:
1651 mode |= TWL4030_APLL_RATE_44100;
1652 break;
1653 case 48000:
1654 mode |= TWL4030_APLL_RATE_48000;
1655 break;
Peter Ujfalusi103f2112009-04-03 14:39:05 +03001656 case 96000:
1657 mode |= TWL4030_APLL_RATE_96000;
1658 break;
Steve Sakomancc175572008-10-30 21:35:26 -07001659 default:
1660 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1661 params_rate(params));
1662 return -EINVAL;
1663 }
1664
1665 if (mode != old_mode) {
1666 /* change rate and set CODECPDZ */
Peter Ujfalusi73939582009-01-29 14:57:50 +02001667 twl4030_codec_enable(codec, 0);
Steve Sakomancc175572008-10-30 21:35:26 -07001668 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
Peter Ujfalusidb04e2c2009-01-27 11:29:40 +02001669 twl4030_codec_enable(codec, 1);
Steve Sakomancc175572008-10-30 21:35:26 -07001670 }
1671
1672 /* sample size */
1673 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1674 format = old_format;
1675 format &= ~TWL4030_DATA_WIDTH;
1676 switch (params_format(params)) {
1677 case SNDRV_PCM_FORMAT_S16_LE:
1678 format |= TWL4030_DATA_WIDTH_16S_16W;
1679 break;
1680 case SNDRV_PCM_FORMAT_S24_LE:
1681 format |= TWL4030_DATA_WIDTH_32S_24W;
1682 break;
1683 default:
1684 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1685 params_format(params));
1686 return -EINVAL;
1687 }
1688
1689 if (format != old_format) {
1690
1691 /* clear CODECPDZ before changing format (codec requirement) */
Peter Ujfalusidb04e2c2009-01-27 11:29:40 +02001692 twl4030_codec_enable(codec, 0);
Steve Sakomancc175572008-10-30 21:35:26 -07001693
1694 /* change format */
1695 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1696
1697 /* set CODECPDZ afterwards */
Peter Ujfalusidb04e2c2009-01-27 11:29:40 +02001698 twl4030_codec_enable(codec, 1);
Steve Sakomancc175572008-10-30 21:35:26 -07001699 }
Peter Ujfalusi6b87a912009-04-17 15:55:08 +03001700
1701 /* Store the important parameters for the DAI configuration and set
1702 * the DAI as configured */
1703 twl4030->configured = 1;
1704 twl4030->rate = params_rate(params);
1705 twl4030->sample_bits = hw_param_interval(params,
1706 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1707 twl4030->channels = params_channels(params);
1708
1709 /* If both playback and capture streams are open, and one of them
1710 * is setting the hw parameters right now (since we are here), set
1711 * constraints to the other stream to match the current one. */
1712 if (twl4030->slave_substream)
1713 twl4030_constraints(twl4030, substream);
1714
Steve Sakomancc175572008-10-30 21:35:26 -07001715 return 0;
1716}
1717
1718static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1719 int clk_id, unsigned int freq, int dir)
1720{
1721 struct snd_soc_codec *codec = codec_dai->codec;
Peter Ujfalusi6943c922009-05-18 16:02:05 +03001722 struct twl4030_priv *twl4030 = codec->private_data;
Steve Sakomancc175572008-10-30 21:35:26 -07001723 u8 infreq;
1724
1725 switch (freq) {
1726 case 19200000:
1727 infreq = TWL4030_APLL_INFREQ_19200KHZ;
Peter Ujfalusi6943c922009-05-18 16:02:05 +03001728 twl4030->sysclk = 19200;
Steve Sakomancc175572008-10-30 21:35:26 -07001729 break;
1730 case 26000000:
1731 infreq = TWL4030_APLL_INFREQ_26000KHZ;
Peter Ujfalusi6943c922009-05-18 16:02:05 +03001732 twl4030->sysclk = 26000;
Steve Sakomancc175572008-10-30 21:35:26 -07001733 break;
1734 case 38400000:
1735 infreq = TWL4030_APLL_INFREQ_38400KHZ;
Peter Ujfalusi6943c922009-05-18 16:02:05 +03001736 twl4030->sysclk = 38400;
Steve Sakomancc175572008-10-30 21:35:26 -07001737 break;
1738 default:
1739 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1740 freq);
1741 return -EINVAL;
1742 }
1743
1744 infreq |= TWL4030_APLL_EN;
1745 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1746
1747 return 0;
1748}
1749
1750static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1751 unsigned int fmt)
1752{
1753 struct snd_soc_codec *codec = codec_dai->codec;
1754 u8 old_format, format;
1755
1756 /* get format */
1757 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1758 format = old_format;
1759
1760 /* set master/slave audio interface */
1761 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1762 case SND_SOC_DAIFMT_CBM_CFM:
1763 format &= ~(TWL4030_AIF_SLAVE_EN);
Grazvydas Ignotase18c94d2008-11-05 23:51:05 +02001764 format &= ~(TWL4030_CLK256FS_EN);
Steve Sakomancc175572008-10-30 21:35:26 -07001765 break;
1766 case SND_SOC_DAIFMT_CBS_CFS:
Steve Sakomancc175572008-10-30 21:35:26 -07001767 format |= TWL4030_AIF_SLAVE_EN;
Grazvydas Ignotase18c94d2008-11-05 23:51:05 +02001768 format |= TWL4030_CLK256FS_EN;
Steve Sakomancc175572008-10-30 21:35:26 -07001769 break;
1770 default:
1771 return -EINVAL;
1772 }
1773
1774 /* interface format */
1775 format &= ~TWL4030_AIF_FORMAT;
1776 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1777 case SND_SOC_DAIFMT_I2S:
1778 format |= TWL4030_AIF_FORMAT_CODEC;
1779 break;
Peter Ujfalusi8a1f9362009-04-23 14:36:49 +03001780 case SND_SOC_DAIFMT_DSP_A:
1781 format |= TWL4030_AIF_FORMAT_TDM;
1782 break;
Steve Sakomancc175572008-10-30 21:35:26 -07001783 default:
1784 return -EINVAL;
1785 }
1786
1787 if (format != old_format) {
1788
1789 /* clear CODECPDZ before changing format (codec requirement) */
Peter Ujfalusidb04e2c2009-01-27 11:29:40 +02001790 twl4030_codec_enable(codec, 0);
Steve Sakomancc175572008-10-30 21:35:26 -07001791
1792 /* change format */
1793 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1794
1795 /* set CODECPDZ afterwards */
Peter Ujfalusidb04e2c2009-01-27 11:29:40 +02001796 twl4030_codec_enable(codec, 1);
Steve Sakomancc175572008-10-30 21:35:26 -07001797 }
1798
1799 return 0;
1800}
1801
Misael Lopez Cruzb7a755a2009-05-17 20:02:31 -05001802/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1803 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1804static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1805 int enable)
1806{
1807 u8 reg, mask;
1808
1809 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1810
1811 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1812 mask = TWL4030_ARXL1_VRX_EN;
1813 else
1814 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1815
1816 if (enable)
1817 reg |= mask;
1818 else
1819 reg &= ~mask;
1820
1821 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1822}
1823
Joonyoung Shim7154b3e2009-04-20 19:21:35 +09001824static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1825 struct snd_soc_dai *dai)
1826{
1827 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1828 struct snd_soc_device *socdev = rtd->socdev;
1829 struct snd_soc_codec *codec = socdev->card->codec;
1830 u8 infreq;
1831 u8 mode;
1832
1833 /* If the system master clock is not 26MHz, the voice PCM interface is
1834 * not avilable.
1835 */
1836 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1837 & TWL4030_APLL_INFREQ;
1838
1839 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1840 printk(KERN_ERR "TWL4030 voice startup: "
1841 "MCLK is not 26MHz, call set_sysclk() on init\n");
1842 return -EINVAL;
1843 }
1844
1845 /* If the codec mode is not option2, the voice PCM interface is not
1846 * avilable.
1847 */
1848 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1849 & TWL4030_OPT_MODE;
1850
1851 if (mode != TWL4030_OPTION_2) {
1852 printk(KERN_ERR "TWL4030 voice startup: "
1853 "the codec mode is not option2\n");
1854 return -EINVAL;
1855 }
1856
1857 return 0;
1858}
1859
Misael Lopez Cruzb7a755a2009-05-17 20:02:31 -05001860static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1861 struct snd_soc_dai *dai)
1862{
1863 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1864 struct snd_soc_device *socdev = rtd->socdev;
1865 struct snd_soc_codec *codec = socdev->card->codec;
1866
1867 /* Enable voice digital filters */
1868 twl4030_voice_enable(codec, substream->stream, 0);
1869}
1870
Joonyoung Shim7154b3e2009-04-20 19:21:35 +09001871static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1872 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1873{
1874 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1875 struct snd_soc_device *socdev = rtd->socdev;
1876 struct snd_soc_codec *codec = socdev->card->codec;
1877 u8 old_mode, mode;
1878
Misael Lopez Cruzb7a755a2009-05-17 20:02:31 -05001879 /* Enable voice digital filters */
1880 twl4030_voice_enable(codec, substream->stream, 1);
1881
Joonyoung Shim7154b3e2009-04-20 19:21:35 +09001882 /* bit rate */
1883 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1884 & ~(TWL4030_CODECPDZ);
1885 mode = old_mode;
1886
1887 switch (params_rate(params)) {
1888 case 8000:
1889 mode &= ~(TWL4030_SEL_16K);
1890 break;
1891 case 16000:
1892 mode |= TWL4030_SEL_16K;
1893 break;
1894 default:
1895 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1896 params_rate(params));
1897 return -EINVAL;
1898 }
1899
1900 if (mode != old_mode) {
1901 /* change rate and set CODECPDZ */
1902 twl4030_codec_enable(codec, 0);
1903 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1904 twl4030_codec_enable(codec, 1);
1905 }
1906
1907 return 0;
1908}
1909
1910static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1911 int clk_id, unsigned int freq, int dir)
1912{
1913 struct snd_soc_codec *codec = codec_dai->codec;
1914 u8 infreq;
1915
1916 switch (freq) {
1917 case 26000000:
1918 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1919 break;
1920 default:
1921 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1922 freq);
1923 return -EINVAL;
1924 }
1925
1926 infreq |= TWL4030_APLL_EN;
1927 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1928
1929 return 0;
1930}
1931
1932static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1933 unsigned int fmt)
1934{
1935 struct snd_soc_codec *codec = codec_dai->codec;
1936 u8 old_format, format;
1937
1938 /* get format */
1939 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1940 format = old_format;
1941
1942 /* set master/slave audio interface */
1943 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1944 case SND_SOC_DAIFMT_CBS_CFM:
1945 format &= ~(TWL4030_VIF_SLAVE_EN);
1946 break;
1947 case SND_SOC_DAIFMT_CBS_CFS:
1948 format |= TWL4030_VIF_SLAVE_EN;
1949 break;
1950 default:
1951 return -EINVAL;
1952 }
1953
1954 /* clock inversion */
1955 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1956 case SND_SOC_DAIFMT_IB_NF:
1957 format &= ~(TWL4030_VIF_FORMAT);
1958 break;
1959 case SND_SOC_DAIFMT_NB_IF:
1960 format |= TWL4030_VIF_FORMAT;
1961 break;
1962 default:
1963 return -EINVAL;
1964 }
1965
1966 if (format != old_format) {
1967 /* change format and set CODECPDZ */
1968 twl4030_codec_enable(codec, 0);
1969 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1970 twl4030_codec_enable(codec, 1);
1971 }
1972
1973 return 0;
1974}
1975
Jarkko Nikulabbba9442008-11-12 17:05:41 +02001976#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
Steve Sakomancc175572008-10-30 21:35:26 -07001977#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1978
Joonyoung Shim10d9e3d2009-03-16 21:23:35 +09001979static struct snd_soc_dai_ops twl4030_dai_ops = {
Peter Ujfalusi7220b9f2009-03-27 10:39:08 +02001980 .startup = twl4030_startup,
1981 .shutdown = twl4030_shutdown,
Joonyoung Shim10d9e3d2009-03-16 21:23:35 +09001982 .hw_params = twl4030_hw_params,
1983 .set_sysclk = twl4030_set_dai_sysclk,
1984 .set_fmt = twl4030_set_dai_fmt,
1985};
1986
Joonyoung Shim7154b3e2009-04-20 19:21:35 +09001987static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
1988 .startup = twl4030_voice_startup,
Misael Lopez Cruzb7a755a2009-05-17 20:02:31 -05001989 .shutdown = twl4030_voice_shutdown,
Joonyoung Shim7154b3e2009-04-20 19:21:35 +09001990 .hw_params = twl4030_voice_hw_params,
1991 .set_sysclk = twl4030_voice_set_dai_sysclk,
1992 .set_fmt = twl4030_voice_set_dai_fmt,
1993};
1994
1995struct snd_soc_dai twl4030_dai[] = {
1996{
Steve Sakomancc175572008-10-30 21:35:26 -07001997 .name = "twl4030",
1998 .playback = {
Peter Ujfalusib4852b72009-05-22 15:12:15 +03001999 .stream_name = "HiFi Playback",
Steve Sakomancc175572008-10-30 21:35:26 -07002000 .channels_min = 2,
Peter Ujfalusi8a1f9362009-04-23 14:36:49 +03002001 .channels_max = 4,
Peter Ujfalusi31ad0f32009-03-27 10:39:07 +02002002 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
Steve Sakomancc175572008-10-30 21:35:26 -07002003 .formats = TWL4030_FORMATS,},
2004 .capture = {
2005 .stream_name = "Capture",
2006 .channels_min = 2,
Peter Ujfalusi8a1f9362009-04-23 14:36:49 +03002007 .channels_max = 4,
Steve Sakomancc175572008-10-30 21:35:26 -07002008 .rates = TWL4030_RATES,
2009 .formats = TWL4030_FORMATS,},
Joonyoung Shim10d9e3d2009-03-16 21:23:35 +09002010 .ops = &twl4030_dai_ops,
Joonyoung Shim7154b3e2009-04-20 19:21:35 +09002011},
2012{
2013 .name = "twl4030 Voice",
2014 .playback = {
Peter Ujfalusib4852b72009-05-22 15:12:15 +03002015 .stream_name = "Voice Playback",
Joonyoung Shim7154b3e2009-04-20 19:21:35 +09002016 .channels_min = 1,
2017 .channels_max = 1,
2018 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2019 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2020 .capture = {
2021 .stream_name = "Capture",
2022 .channels_min = 1,
2023 .channels_max = 2,
2024 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2025 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2026 .ops = &twl4030_dai_voice_ops,
2027},
Steve Sakomancc175572008-10-30 21:35:26 -07002028};
2029EXPORT_SYMBOL_GPL(twl4030_dai);
2030
2031static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
2032{
2033 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
Mark Brown6627a652009-01-23 22:55:23 +00002034 struct snd_soc_codec *codec = socdev->card->codec;
Steve Sakomancc175572008-10-30 21:35:26 -07002035
2036 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2037
2038 return 0;
2039}
2040
2041static int twl4030_resume(struct platform_device *pdev)
2042{
2043 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
Mark Brown6627a652009-01-23 22:55:23 +00002044 struct snd_soc_codec *codec = socdev->card->codec;
Steve Sakomancc175572008-10-30 21:35:26 -07002045
2046 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2047 twl4030_set_bias_level(codec, codec->suspend_bias_level);
2048 return 0;
2049}
2050
2051/*
2052 * initialize the driver
2053 * register the mixer and dsp interfaces with the kernel
2054 */
2055
2056static int twl4030_init(struct snd_soc_device *socdev)
2057{
Mark Brown6627a652009-01-23 22:55:23 +00002058 struct snd_soc_codec *codec = socdev->card->codec;
Peter Ujfalusi9da28c72009-05-22 10:13:15 +03002059 struct twl4030_setup_data *setup = socdev->codec_data;
2060 struct twl4030_priv *twl4030 = codec->private_data;
Steve Sakomancc175572008-10-30 21:35:26 -07002061 int ret = 0;
2062
2063 printk(KERN_INFO "TWL4030 Audio Codec init \n");
2064
2065 codec->name = "twl4030";
2066 codec->owner = THIS_MODULE;
2067 codec->read = twl4030_read_reg_cache;
2068 codec->write = twl4030_write;
2069 codec->set_bias_level = twl4030_set_bias_level;
Joonyoung Shim7154b3e2009-04-20 19:21:35 +09002070 codec->dai = twl4030_dai;
2071 codec->num_dai = ARRAY_SIZE(twl4030_dai),
Steve Sakomancc175572008-10-30 21:35:26 -07002072 codec->reg_cache_size = sizeof(twl4030_reg);
2073 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2074 GFP_KERNEL);
2075 if (codec->reg_cache == NULL)
2076 return -ENOMEM;
2077
Peter Ujfalusi9da28c72009-05-22 10:13:15 +03002078 /* Configuration for headset ramp delay from setup data */
2079 if (setup) {
2080 unsigned char hs_pop;
2081
2082 if (setup->sysclk)
2083 twl4030->sysclk = setup->sysclk;
2084 else
2085 twl4030->sysclk = 26000;
2086
2087 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2088 hs_pop &= ~TWL4030_RAMP_DELAY;
2089 hs_pop |= (setup->ramp_delay_value << 2);
2090 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2091 } else {
2092 twl4030->sysclk = 26000;
2093 }
2094
Steve Sakomancc175572008-10-30 21:35:26 -07002095 /* register pcms */
2096 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2097 if (ret < 0) {
2098 printk(KERN_ERR "twl4030: failed to create pcms\n");
2099 goto pcm_err;
2100 }
2101
2102 twl4030_init_chip(codec);
2103
2104 /* power on device */
2105 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2106
Ian Molton3e8e1952009-01-09 00:23:21 +00002107 snd_soc_add_controls(codec, twl4030_snd_controls,
2108 ARRAY_SIZE(twl4030_snd_controls));
Steve Sakomancc175572008-10-30 21:35:26 -07002109 twl4030_add_widgets(codec);
2110
Mark Brown968a6022008-11-28 11:49:07 +00002111 ret = snd_soc_init_card(socdev);
Steve Sakomancc175572008-10-30 21:35:26 -07002112 if (ret < 0) {
2113 printk(KERN_ERR "twl4030: failed to register card\n");
2114 goto card_err;
2115 }
2116
2117 return ret;
2118
2119card_err:
2120 snd_soc_free_pcms(socdev);
2121 snd_soc_dapm_free(socdev);
2122pcm_err:
2123 kfree(codec->reg_cache);
2124 return ret;
2125}
2126
2127static struct snd_soc_device *twl4030_socdev;
2128
2129static int twl4030_probe(struct platform_device *pdev)
2130{
2131 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2132 struct snd_soc_codec *codec;
Peter Ujfalusi73939582009-01-29 14:57:50 +02002133 struct twl4030_priv *twl4030;
Steve Sakomancc175572008-10-30 21:35:26 -07002134
2135 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
2136 if (codec == NULL)
2137 return -ENOMEM;
2138
Peter Ujfalusi73939582009-01-29 14:57:50 +02002139 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2140 if (twl4030 == NULL) {
2141 kfree(codec);
2142 return -ENOMEM;
2143 }
2144
2145 codec->private_data = twl4030;
Mark Brown6627a652009-01-23 22:55:23 +00002146 socdev->card->codec = codec;
Steve Sakomancc175572008-10-30 21:35:26 -07002147 mutex_init(&codec->mutex);
2148 INIT_LIST_HEAD(&codec->dapm_widgets);
2149 INIT_LIST_HEAD(&codec->dapm_paths);
2150
2151 twl4030_socdev = socdev;
2152 twl4030_init(socdev);
2153
2154 return 0;
2155}
2156
2157static int twl4030_remove(struct platform_device *pdev)
2158{
2159 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
Mark Brown6627a652009-01-23 22:55:23 +00002160 struct snd_soc_codec *codec = socdev->card->codec;
Steve Sakomancc175572008-10-30 21:35:26 -07002161
2162 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
Peter Ujfalusi73939582009-01-29 14:57:50 +02002163 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
Peter Ujfalusic6d1662b2009-01-08 15:52:43 +02002164 snd_soc_free_pcms(socdev);
2165 snd_soc_dapm_free(socdev);
Peter Ujfalusi73939582009-01-29 14:57:50 +02002166 kfree(codec->private_data);
Steve Sakomancc175572008-10-30 21:35:26 -07002167 kfree(codec);
2168
2169 return 0;
2170}
2171
2172struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2173 .probe = twl4030_probe,
2174 .remove = twl4030_remove,
2175 .suspend = twl4030_suspend,
2176 .resume = twl4030_resume,
2177};
2178EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2179
Takashi Iwai24e07db2008-12-10 07:40:24 +01002180static int __init twl4030_modinit(void)
Mark Brown64089b82008-12-08 19:17:58 +00002181{
Joonyoung Shim7154b3e2009-04-20 19:21:35 +09002182 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
Mark Brown64089b82008-12-08 19:17:58 +00002183}
Takashi Iwai24e07db2008-12-10 07:40:24 +01002184module_init(twl4030_modinit);
Mark Brown64089b82008-12-08 19:17:58 +00002185
2186static void __exit twl4030_exit(void)
2187{
Joonyoung Shim7154b3e2009-04-20 19:21:35 +09002188 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
Mark Brown64089b82008-12-08 19:17:58 +00002189}
2190module_exit(twl4030_exit);
2191
Steve Sakomancc175572008-10-30 21:35:26 -07002192MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2193MODULE_AUTHOR("Steve Sakoman");
2194MODULE_LICENSE("GPL");