blob: 22e227f87e4c19fd3dd9499c45ec25b2a7d7f6d1 [file] [log] [blame]
Stephen Warrena7db2c12011-10-25 02:01:28 +00001/dts-v1/;
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -06003#include "tegra20.dtsi"
Stephen Warrena7db2c12011-10-25 02:01:28 +00004
5/ {
6 model = "Compulab TrimSlice board";
7 compatible = "compulab,trimslice", "nvidia,tegra20";
8
Stephen Warrenf9eb26a2012-05-11 16:17:47 -06009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +000011 };
12
Thierry Redingdced3e32012-09-20 10:39:20 +020013 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070021 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
22 GPIO_ACTIVE_HIGH>;
Thierry Redingdced3e32012-09-20 10:39:20 +020023 };
24 };
25
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060026 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060027 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>;
29
30 state_default: pinmux {
31 ata {
32 nvidia,pins = "ata";
33 nvidia,function = "ide";
34 };
35 atb {
36 nvidia,pins = "atb", "gma";
37 nvidia,function = "sdio4";
38 };
39 atc {
40 nvidia,pins = "atc", "gmb";
41 nvidia,function = "nand";
42 };
43 atd {
44 nvidia,pins = "atd", "ate", "gme", "pta";
45 nvidia,function = "gmi";
46 };
47 cdev1 {
48 nvidia,pins = "cdev1";
49 nvidia,function = "plla_out";
50 };
51 cdev2 {
52 nvidia,pins = "cdev2";
53 nvidia,function = "pllp_out4";
54 };
55 crtp {
56 nvidia,pins = "crtp";
57 nvidia,function = "crt";
58 };
59 csus {
60 nvidia,pins = "csus";
61 nvidia,function = "vi_sensor_clk";
62 };
63 dap1 {
64 nvidia,pins = "dap1";
65 nvidia,function = "dap1";
66 };
67 dap2 {
68 nvidia,pins = "dap2";
69 nvidia,function = "dap2";
70 };
71 dap3 {
72 nvidia,pins = "dap3";
73 nvidia,function = "dap3";
74 };
75 dap4 {
76 nvidia,pins = "dap4";
77 nvidia,function = "dap4";
78 };
79 ddc {
80 nvidia,pins = "ddc";
81 nvidia,function = "i2c2";
82 };
83 dta {
84 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
85 nvidia,function = "vi";
86 };
87 dtf {
88 nvidia,pins = "dtf";
89 nvidia,function = "i2c3";
90 };
91 gmc {
92 nvidia,pins = "gmc", "gmd";
93 nvidia,function = "sflash";
94 };
95 gpu {
96 nvidia,pins = "gpu";
97 nvidia,function = "uarta";
98 };
99 gpu7 {
100 nvidia,pins = "gpu7";
101 nvidia,function = "rtck";
102 };
103 gpv {
104 nvidia,pins = "gpv", "slxa", "slxk";
105 nvidia,function = "pcie";
106 };
107 hdint {
108 nvidia,pins = "hdint";
109 nvidia,function = "hdmi";
110 };
111 i2cp {
112 nvidia,pins = "i2cp";
113 nvidia,function = "i2cp";
114 };
115 irrx {
116 nvidia,pins = "irrx", "irtx";
117 nvidia,function = "uartb";
118 };
119 kbca {
120 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
121 "kbce", "kbcf";
122 nvidia,function = "kbc";
123 };
124 lcsn {
125 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
126 "ld3", "ld4", "ld5", "ld6", "ld7",
127 "ld8", "ld9", "ld10", "ld11", "ld12",
128 "ld13", "ld14", "ld15", "ld16", "ld17",
129 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
130 "lhs", "lm0", "lm1", "lpp", "lpw0",
131 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
132 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
133 "lvs";
134 nvidia,function = "displaya";
135 };
136 owc {
137 nvidia,pins = "owc", "uac";
138 nvidia,function = "rsvd2";
139 };
140 pmc {
141 nvidia,pins = "pmc";
142 nvidia,function = "pwr_on";
143 };
144 rm {
145 nvidia,pins = "rm";
146 nvidia,function = "i2c1";
147 };
148 sdb {
149 nvidia,pins = "sdb", "sdc", "sdd";
150 nvidia,function = "pwm";
151 };
152 sdio1 {
153 nvidia,pins = "sdio1";
154 nvidia,function = "sdio1";
155 };
156 slxc {
157 nvidia,pins = "slxc", "slxd";
158 nvidia,function = "sdio3";
159 };
160 spdi {
161 nvidia,pins = "spdi", "spdo";
162 nvidia,function = "spdif";
163 };
164 spia {
165 nvidia,pins = "spia", "spib", "spic";
166 nvidia,function = "spi2";
167 };
168 spid {
169 nvidia,pins = "spid", "spie", "spif";
170 nvidia,function = "spi1";
171 };
172 spig {
173 nvidia,pins = "spig", "spih";
174 nvidia,function = "spi2_alt";
175 };
176 uaa {
177 nvidia,pins = "uaa", "uab", "uda";
178 nvidia,function = "ulpi";
179 };
180 uad {
181 nvidia,pins = "uad";
182 nvidia,function = "irda";
183 };
184 uca {
185 nvidia,pins = "uca", "ucb";
186 nvidia,function = "uartc";
187 };
188 conf_ata {
189 nvidia,pins = "ata", "atc", "atd", "ate",
190 "crtp", "dap2", "dap3", "dap4", "dta",
191 "dtb", "dtc", "dtd", "dte", "gmb",
192 "gme", "i2cp", "pta", "slxc", "slxd",
193 "spdi", "spdo", "uda";
194 nvidia,pull = <0>;
195 nvidia,tristate = <1>;
196 };
197 conf_atb {
Stephen Warren563da212012-04-13 16:35:20 -0600198 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
199 "gma", "gmc", "gmd", "gpu", "gpu7",
200 "gpv", "sdio1", "slxa", "slxk", "uac";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600201 nvidia,pull = <0>;
202 nvidia,tristate = <0>;
203 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600204 conf_ck32 {
205 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
206 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
207 nvidia,pull = <0>;
208 };
Stephen Warren563da212012-04-13 16:35:20 -0600209 conf_csus {
210 nvidia,pins = "csus", "spia", "spib",
211 "spid", "spif";
212 nvidia,pull = <1>;
213 nvidia,tristate = <1>;
214 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600215 conf_ddc {
216 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
217 nvidia,pull = <2>;
218 nvidia,tristate = <0>;
219 };
220 conf_hdint {
221 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
222 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
223 "lvp0", "pmc";
224 nvidia,tristate = <1>;
225 };
226 conf_irrx {
227 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
228 "kbcc", "kbcd", "kbce", "kbcf", "owc",
229 "spic", "spie", "spig", "spih", "uaa",
230 "uab", "uad", "uca", "ucb";
231 nvidia,pull = <2>;
232 nvidia,tristate = <1>;
233 };
234 conf_lc {
235 nvidia,pins = "lc", "ls";
236 nvidia,pull = <2>;
237 };
238 conf_ld0 {
239 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
240 "ld5", "ld6", "ld7", "ld8", "ld9",
241 "ld10", "ld11", "ld12", "ld13", "ld14",
242 "ld15", "ld16", "ld17", "ldi", "lhp0",
243 "lhp1", "lhp2", "lhs", "lm0", "lpp",
244 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
245 "lvs", "sdb";
246 nvidia,tristate = <0>;
247 };
248 conf_ld17_0 {
249 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
250 "ld23_22";
251 nvidia,pull = <1>;
252 };
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700253 conf_spif {
254 nvidia,pins = "spif";
255 nvidia,pull = <1>;
256 nvidia,tristate = <0>;
257 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600258 };
259 };
260
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600261 i2s@70002800 {
262 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600263 };
264
265 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600266 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600267 };
268
Thierry Redingdced3e32012-09-20 10:39:20 +0200269 dvi_ddc: i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600270 status = "okay";
Thierry Redingdced3e32012-09-20 10:39:20 +0200271 clock-frequency = <100000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000272 };
273
Stephen Warrenfea221e2012-11-12 12:51:22 -0700274 spi@7000c380 {
275 status = "okay";
276 spi-max-frequency = <48000000>;
277 spi-flash@0 {
278 compatible = "winbond,w25q80bl";
279 reg = <0>;
280 spi-max-frequency = <48000000>;
281 };
282 };
283
Thierry Redingdced3e32012-09-20 10:39:20 +0200284 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600285 status = "okay";
Thierry Redingdced3e32012-09-20 10:39:20 +0200286 clock-frequency = <100000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000287 };
288
289 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600290 status = "okay";
Stephen Warrena7db2c12011-10-25 02:01:28 +0000291 clock-frequency = <400000>;
Stephen Warren081cc0a2012-04-27 09:22:44 -0600292
Stephen Warren22bfe102012-04-27 13:24:03 -0600293 codec: codec@1a {
294 compatible = "ti,tlv320aic23";
295 reg = <0x1a>;
296 };
297
Stephen Warren081cc0a2012-04-27 09:22:44 -0600298 rtc@56 {
299 compatible = "emmicro,em3027";
300 reg = <0x56>;
301 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000302 };
303
Joseph Loa44a0192013-04-03 19:31:52 +0800304 pmc {
Joseph Lo47d2d632013-08-12 17:40:07 +0800305 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800306 nvidia,cpu-pwr-good-time = <5000>;
307 nvidia,cpu-pwr-off-time = <5000>;
308 nvidia,core-pwr-good-time = <3845 3845>;
309 nvidia,core-pwr-off-time = <3875>;
310 nvidia,sys-clock-req-active-high;
311 };
312
Thierry Reding1798efd2013-08-09 16:49:23 +0200313 pcie-controller {
314 status = "okay";
315 pex-clk-supply = <&pci_clk_reg>;
316 vdd-supply = <&pci_vdd_reg>;
317
318 pci@1,0 {
319 status = "okay";
320 };
321 };
322
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600323 usb@c5000000 {
324 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700325 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700326 };
327
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530328 usb-phy@c5000000 {
329 status = "okay";
330 vbus-supply = <&vbus_reg>;
331 };
332
Stephen Warrenc04abb32012-05-11 17:03:26 -0600333 usb@c5004000 {
Stephen Warrena6a3dd12012-07-25 14:02:43 -0600334 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700335 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
336 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530337 };
338
339 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530340 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700341 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
342 GPIO_ACTIVE_LOW>;
Stephen Warren31c1ec92011-11-21 14:44:10 -0700343 };
344
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600345 usb@c5008000 {
346 status = "okay";
Stephen Warren1292c122011-11-21 14:44:11 -0700347 };
348
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530349 usb-phy@c5008000 {
350 status = "okay";
351 };
352
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600353 sdhci@c8000000 {
354 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200355 bus-width = <4>;
Stephen Warren1292c122011-11-21 14:44:11 -0700356 };
357
Stephen Warrena7db2c12011-10-25 02:01:28 +0000358 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600359 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700360 cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
361 wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200362 bus-width = <4>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000363 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600364
Joseph Lo7021d122013-04-03 19:31:27 +0800365 clocks {
366 compatible = "simple-bus";
367 #address-cells = <1>;
368 #size-cells = <0>;
369
370 clk32k_in: clock {
371 compatible = "fixed-clock";
372 reg=<0>;
373 #clock-cells = <0>;
374 clock-frequency = <32768>;
375 };
376 };
377
Joseph Lo5741a252013-04-03 19:31:48 +0800378 gpio-keys {
379 compatible = "gpio-keys";
380
381 power {
382 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700383 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
Joseph Lo5741a252013-04-03 19:31:48 +0800384 linux,code = <116>; /* KEY_POWER */
385 gpio-key,wakeup;
386 };
387 };
388
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700389 poweroff {
390 compatible = "gpio-poweroff";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700391 gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
Stephen Warrenbff1ea72012-12-06 14:23:52 -0700392 };
393
Thierry Redingdced3e32012-09-20 10:39:20 +0200394 regulators {
395 compatible = "simple-bus";
396 #address-cells = <1>;
397 #size-cells = <0>;
398
399 hdmi_vdd_reg: regulator@0 {
400 compatible = "regulator-fixed";
401 reg = <0>;
402 regulator-name = "avdd_hdmi";
403 regulator-min-microvolt = <3300000>;
404 regulator-max-microvolt = <3300000>;
405 regulator-always-on;
406 };
407
408 hdmi_pll_reg: regulator@1 {
409 compatible = "regulator-fixed";
410 reg = <1>;
411 regulator-name = "avdd_hdmi_pll";
412 regulator-min-microvolt = <1800000>;
413 regulator-max-microvolt = <1800000>;
414 regulator-always-on;
415 };
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530416
417 vbus_reg: regulator@2 {
418 compatible = "regulator-fixed";
419 reg = <2>;
420 regulator-name = "usb1_vbus";
421 regulator-min-microvolt = <5000000>;
422 regulator-max-microvolt = <5000000>;
Stephen Warren9f310de2013-07-01 15:07:05 -0600423 enable-active-high;
Stephen Warren23f95ef2013-08-01 12:26:01 -0600424 gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530425 };
Thierry Reding1798efd2013-08-09 16:49:23 +0200426
427 pci_clk_reg: regulator@3 {
428 compatible = "regulator-fixed";
429 reg = <3>;
430 regulator-name = "pci_clk";
431 regulator-min-microvolt = <3300000>;
432 regulator-max-microvolt = <3300000>;
433 regulator-always-on;
434 };
435
436 pci_vdd_reg: regulator@4 {
437 compatible = "regulator-fixed";
438 reg = <4>;
439 regulator-name = "pci_vdd";
440 regulator-min-microvolt = <1050000>;
441 regulator-max-microvolt = <1050000>;
442 regulator-always-on;
443 };
Thierry Redingdced3e32012-09-20 10:39:20 +0200444 };
445
Stephen Warrenc04abb32012-05-11 17:03:26 -0600446 sound {
447 compatible = "nvidia,tegra-audio-trimslice";
448 nvidia,i2s-controller = <&tegra_i2s1>;
449 nvidia,audio-codec = <&codec>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600450
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300451 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
452 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
453 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600454 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600455 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000456};