| Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Maxime Ripard |
| 3 | * |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 5 | * |
| 6 | * The code contained herein is licensed under the GNU General Public |
| 7 | * License. You may obtain a copy of the GNU General Public License |
| 8 | * Version 2 or later at the following locations: |
| 9 | * |
| 10 | * http://www.opensource.org/licenses/gpl-license.html |
| 11 | * http://www.gnu.org/copyleft/gpl.html |
| 12 | */ |
| 13 | |
| 14 | /include/ "skeleton.dtsi" |
| 15 | |
| 16 | / { |
| 17 | interrupt-parent = <&gic>; |
| 18 | |
| 19 | cpus { |
| 20 | #address-cells = <1>; |
| 21 | #size-cells = <0>; |
| 22 | |
| 23 | cpu@0 { |
| 24 | compatible = "arm,cortex-a7"; |
| 25 | device_type = "cpu"; |
| 26 | reg = <0>; |
| 27 | }; |
| 28 | |
| 29 | cpu@1 { |
| 30 | compatible = "arm,cortex-a7"; |
| 31 | device_type = "cpu"; |
| 32 | reg = <1>; |
| 33 | }; |
| 34 | }; |
| 35 | |
| 36 | memory { |
| 37 | reg = <0x40000000 0x80000000>; |
| 38 | }; |
| 39 | |
| 40 | clocks { |
| 41 | #address-cells = <1>; |
| 42 | #size-cells = <1>; |
| 43 | ranges; |
| 44 | |
| 45 | osc24M: osc24M@01c20050 { |
| 46 | #clock-cells = <0>; |
| 47 | compatible = "fixed-clock"; |
| 48 | clock-frequency = <24000000>; |
| 49 | }; |
| 50 | |
| 51 | osc32k: osc32k { |
| 52 | #clock-cells = <0>; |
| 53 | compatible = "fixed-clock"; |
| 54 | clock-frequency = <32768>; |
| 55 | }; |
| 56 | }; |
| 57 | |
| 58 | soc@01c00000 { |
| 59 | compatible = "simple-bus"; |
| 60 | #address-cells = <1>; |
| 61 | #size-cells = <1>; |
| 62 | ranges; |
| 63 | |
| Maxime Ripard | 17eac03 | 2013-07-24 23:46:11 +0200 | [diff] [blame^] | 64 | pio: pinctrl@01c20800 { |
| 65 | compatible = "allwinner,sun7i-a20-pinctrl"; |
| 66 | reg = <0x01c20800 0x400>; |
| 67 | interrupts = <0 28 1>; |
| 68 | clocks = <&osc24M>; |
| 69 | gpio-controller; |
| 70 | interrupt-controller; |
| 71 | #address-cells = <1>; |
| 72 | #size-cells = <0>; |
| 73 | #gpio-cells = <3>; |
| 74 | }; |
| 75 | |
| Maxime Ripard | 4790ecf | 2013-07-17 10:07:10 +0200 | [diff] [blame] | 76 | timer@01c20c00 { |
| 77 | compatible = "allwinner,sun4i-timer"; |
| 78 | reg = <0x01c20c00 0x90>; |
| 79 | interrupts = <0 22 1>, |
| 80 | <0 23 1>, |
| 81 | <0 24 1>, |
| 82 | <0 25 1>, |
| 83 | <0 67 1>, |
| 84 | <0 68 1>; |
| 85 | clocks = <&osc24M>; |
| 86 | }; |
| 87 | |
| 88 | wdt: watchdog@01c20c90 { |
| 89 | compatible = "allwinner,sun4i-wdt"; |
| 90 | reg = <0x01c20c90 0x10>; |
| 91 | }; |
| 92 | |
| 93 | uart0: serial@01c28000 { |
| 94 | compatible = "snps,dw-apb-uart"; |
| 95 | reg = <0x01c28000 0x400>; |
| 96 | interrupts = <0 1 1>; |
| 97 | reg-shift = <2>; |
| 98 | reg-io-width = <4>; |
| 99 | clocks = <&osc24M>; |
| 100 | status = "disabled"; |
| 101 | }; |
| 102 | |
| 103 | uart1: serial@01c28400 { |
| 104 | compatible = "snps,dw-apb-uart"; |
| 105 | reg = <0x01c28400 0x400>; |
| 106 | interrupts = <0 2 1>; |
| 107 | reg-shift = <2>; |
| 108 | reg-io-width = <4>; |
| 109 | clocks = <&osc24M>; |
| 110 | status = "disabled"; |
| 111 | }; |
| 112 | |
| 113 | uart2: serial@01c28800 { |
| 114 | compatible = "snps,dw-apb-uart"; |
| 115 | reg = <0x01c28800 0x400>; |
| 116 | interrupts = <0 3 1>; |
| 117 | reg-shift = <2>; |
| 118 | reg-io-width = <4>; |
| 119 | clocks = <&osc24M>; |
| 120 | status = "disabled"; |
| 121 | }; |
| 122 | |
| 123 | uart3: serial@01c28c00 { |
| 124 | compatible = "snps,dw-apb-uart"; |
| 125 | reg = <0x01c28c00 0x400>; |
| 126 | interrupts = <0 4 1>; |
| 127 | reg-shift = <2>; |
| 128 | reg-io-width = <4>; |
| 129 | clocks = <&osc24M>; |
| 130 | status = "disabled"; |
| 131 | }; |
| 132 | |
| 133 | uart4: serial@01c29000 { |
| 134 | compatible = "snps,dw-apb-uart"; |
| 135 | reg = <0x01c29000 0x400>; |
| 136 | interrupts = <0 17 1>; |
| 137 | reg-shift = <2>; |
| 138 | reg-io-width = <4>; |
| 139 | clocks = <&osc24M>; |
| 140 | status = "disabled"; |
| 141 | }; |
| 142 | |
| 143 | uart5: serial@01c29400 { |
| 144 | compatible = "snps,dw-apb-uart"; |
| 145 | reg = <0x01c29400 0x400>; |
| 146 | interrupts = <0 18 1>; |
| 147 | reg-shift = <2>; |
| 148 | reg-io-width = <4>; |
| 149 | clocks = <&osc24M>; |
| 150 | status = "disabled"; |
| 151 | }; |
| 152 | |
| 153 | uart6: serial@01c29800 { |
| 154 | compatible = "snps,dw-apb-uart"; |
| 155 | reg = <0x01c29800 0x400>; |
| 156 | interrupts = <0 19 1>; |
| 157 | reg-shift = <2>; |
| 158 | reg-io-width = <4>; |
| 159 | clocks = <&osc24M>; |
| 160 | status = "disabled"; |
| 161 | }; |
| 162 | |
| 163 | uart7: serial@01c29c00 { |
| 164 | compatible = "snps,dw-apb-uart"; |
| 165 | reg = <0x01c29c00 0x400>; |
| 166 | interrupts = <0 20 1>; |
| 167 | reg-shift = <2>; |
| 168 | reg-io-width = <4>; |
| 169 | clocks = <&osc24M>; |
| 170 | status = "disabled"; |
| 171 | }; |
| 172 | |
| 173 | gic: interrupt-controller@01c81000 { |
| 174 | compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; |
| 175 | reg = <0x01c81000 0x1000>, |
| 176 | <0x01c82000 0x1000>, |
| 177 | <0x01c84000 0x2000>, |
| 178 | <0x01c86000 0x2000>; |
| 179 | interrupt-controller; |
| 180 | #interrupt-cells = <3>; |
| 181 | interrupts = <1 9 0xf04>; |
| 182 | }; |
| 183 | }; |
| 184 | }; |