Blame - drivers/irqchip/Kconfig - kernel/msm-4.19

blob: 4631685dfe43fc33cb1a97d9361eda2e91afae98 [file] [log] [blame]

Thomas Petazzoni	f6e916b	2012-11-20 23:00:52 +0100	[diff] [blame]	1	config IRQCHIP
				2	def_bool y
				3	depends on OF_IRQ
				4
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	5	config ARM_GIC
				6	bool
				7	select IRQ_DOMAIN
				8	select MULTI_IRQ_HANDLER
				9
				10	config GIC_NON_BANKED
				11	bool
				12
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	13	config ARM_GIC_V3
				14	bool
				15	select IRQ_DOMAIN
				16	select MULTI_IRQ_HANDLER
Marc Zyngier	443acc4	2014-11-24 14:35:09 +0000	[diff] [blame]	17	select IRQ_DOMAIN_HIERARCHY
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	18
Uwe Kleine-König	292ec08	2013-06-26 09:18:48 +0200	[diff] [blame]	19	config ARM_NVIC
				20	bool
				21	select IRQ_DOMAIN
				22	select GENERIC_IRQ_CHIP
				23
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	24	config ARM_VIC
				25	bool
				26	select IRQ_DOMAIN
				27	select MULTI_IRQ_HANDLER
				28
				29	config ARM_VIC_NR
				30	int
				31	default 4 if ARCH_S5PV210
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	32	default 2
				33	depends on ARM_VIC
				34	help
				35	The maximum number of VICs available in the system, for
				36	power management.
				37
Boris BREZILLON	b1479eb	2014-07-10 19:14:18 +0200	[diff] [blame]	38	config ATMEL_AIC_IRQ
				39	bool
				40	select GENERIC_IRQ_CHIP
				41	select IRQ_DOMAIN
				42	select MULTI_IRQ_HANDLER
				43	select SPARSE_IRQ
				44
				45	config ATMEL_AIC5_IRQ
				46	bool
				47	select GENERIC_IRQ_CHIP
				48	select IRQ_DOMAIN
				49	select MULTI_IRQ_HANDLER
				50	select SPARSE_IRQ
				51
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	52	config BRCMSTB_L2_IRQ
				53	bool
				54	depends on ARM
				55	select GENERIC_IRQ_CHIP
				56	select IRQ_DOMAIN
				57
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	58	config DW_APB_ICTL
				59	bool
				60	select IRQ_DOMAIN
				61
James Hogan	b6ef916	2013-04-22 15:43:50 +0100	[diff] [blame]	62	config IMGPDC_IRQ
				63	bool
				64	select GENERIC_IRQ_CHIP
				65	select IRQ_DOMAIN
				66
Alexander Shiyan	afc98d9	2014-02-02 12:07:46 +0400	[diff] [blame]	67	config CLPS711X_IRQCHIP
				68	bool
				69	depends on ARCH_CLPS711X
				70	select IRQ_DOMAIN
				71	select MULTI_IRQ_HANDLER
				72	select SPARSE_IRQ
				73	default y
				74
Stefan Kristiansson	4db8e6d	2014-05-26 23:31:42 +0300	[diff] [blame]	75	config OR1K_PIC
				76	bool
				77	select IRQ_DOMAIN
				78
Felipe Balbi	8598066	2014-09-15 16:15:02 -0500	[diff] [blame]	79	config OMAP_IRQCHIP
				80	bool
				81	select GENERIC_IRQ_CHIP
				82	select IRQ_DOMAIN
				83
Sebastian Hesselbarth	9dbd90f	2013-06-06 18:27:09 +0200	[diff] [blame]	84	config ORION_IRQCHIP
				85	bool
				86	select IRQ_DOMAIN
				87	select MULTI_IRQ_HANDLER
				88
Magnus Damm	4435804	2013-02-18 23:28:34 +0900	[diff] [blame]	89	config RENESAS_INTC_IRQPIN
				90	bool
				91	select IRQ_DOMAIN
				92
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	93	config RENESAS_IRQC
				94	bool
				95	select IRQ_DOMAIN
				96
Christian Ruppert	b06eb01	2013-06-25 18:29:57 +0200	[diff] [blame]	97	config TB10X_IRQC
				98	bool
				99	select IRQ_DOMAIN
				100	select GENERIC_IRQ_CHIP
				101
Linus Walleij	2389d50	2012-10-31 22:04:31 +0100	[diff] [blame]	102	config VERSATILE_FPGA_IRQ
				103	bool
				104	select IRQ_DOMAIN
				105
				106	config VERSATILE_FPGA_IRQ_NR
				107	int
				108	default 4
				109	depends on VERSATILE_FPGA_IRQ
Max Filippov	26a8e96	2013-12-01 12:04:57 +0400	[diff] [blame]	110
				111	config XTENSA_MX
				112	bool
				113	select IRQ_DOMAIN
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	114
				115	config IRQ_CROSSBAR
				116	bool
				117	help
Masanari Iida	f54619f	2014-09-18 12:09:42 +0900	[diff] [blame]	118	Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	119	The primary irqchip invokes the crossbar's callback which inturn allocates
				120	a free irq and configures the IP. Thus the peripheral interrupts are
				121	routed to one of the free irqchip interrupt lines.
Grygorii Strashko	89323f8	2014-07-23 17:40:30 +0300	[diff] [blame]	122
				123	config KEYSTONE_IRQ
				124	tristate "Keystone 2 IRQ controller IP"
				125	depends on ARCH_KEYSTONE
				126	help
				127	Support for Texas Instruments Keystone 2 IRQ controller IP which
				128	is part of the Keystone 2 IPC mechanism