Byungho Min | c9b870e | 2009-06-23 21:40:03 +0900 | [diff] [blame] | 1 | /* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h |
| 2 | * |
| 3 | * Copyright 2009 Samsung Electronics Co. |
| 4 | * Byungho Min <bhmin@samsung.com> |
| 5 | * |
| 6 | * S5PC100 - pwm clock and timer support |
| 7 | * |
| 8 | * Based on mach-s3c6400/include/mach/pwm-clock.h |
| 9 | */ |
| 10 | |
| 11 | /** |
| 12 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk |
| 13 | * @tcfg: The timer TCFG1 register bits shifted down to 0. |
| 14 | * |
| 15 | * Return true if the given configuration from TCFG1 is a TCLK instead |
| 16 | * any of the TDIV clocks. |
| 17 | */ |
| 18 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) |
| 19 | { |
| 20 | return tcfg >= S3C64XX_TCFG1_MUX_TCLK; |
| 21 | } |
| 22 | |
| 23 | /** |
| 24 | * tcfg_to_divisor() - convert tcfg1 setting to a divisor |
| 25 | * @tcfg1: The tcfg1 setting, shifted down. |
| 26 | * |
| 27 | * Get the divisor value for the given tcfg1 setting. We assume the |
| 28 | * caller has already checked to see if this is not a TCLK source. |
| 29 | */ |
| 30 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) |
| 31 | { |
| 32 | return 1 << tcfg1; |
| 33 | } |
| 34 | |
| 35 | /** |
| 36 | * pwm_tdiv_has_div1() - does the tdiv setting have a /1 |
| 37 | * |
| 38 | * Return true if we have a /1 in the tdiv setting. |
| 39 | */ |
| 40 | static inline unsigned int pwm_tdiv_has_div1(void) |
| 41 | { |
| 42 | return 1; |
| 43 | } |
| 44 | |
| 45 | /** |
| 46 | * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. |
| 47 | * @div: The divisor to calculate the bit information for. |
| 48 | * |
| 49 | * Turn a divisor into the necessary bit field for TCFG1. |
| 50 | */ |
| 51 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) |
| 52 | { |
| 53 | return ilog2(div); |
| 54 | } |
| 55 | |
| 56 | #define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK |