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Carlo Caionecfb61a42014-05-01 14:29:27 +02001/*
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +08002 * MFD core driver for the X-Powers' Power Management ICs
Carlo Caionecfb61a42014-05-01 14:29:27 +02003 *
Jacob Panaf7e9062014-10-06 21:17:14 -07004 * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
5 * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
6 * as well as configurable GPIOs.
Carlo Caionecfb61a42014-05-01 14:29:27 +02007 *
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +08008 * This file contains the interface independent core functions.
9 *
Chen-Yu Tsaie7402352016-02-12 10:02:41 +080010 * Copyright (C) 2014 Carlo Caione
11 *
Carlo Caionecfb61a42014-05-01 14:29:27 +020012 * Author: Carlo Caione <carlo@caione.org>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/err.h>
Hans de Goede179dc632016-06-05 15:50:48 +020020#include <linux/delay.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020021#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <linux/regmap.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020026#include <linux/regulator/consumer.h>
27#include <linux/mfd/axp20x.h>
28#include <linux/mfd/core.h>
29#include <linux/of_device.h>
Jacob Panaf7e9062014-10-06 21:17:14 -070030#include <linux/acpi.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020031
32#define AXP20X_OFF 0x80
33
Krzysztof Kozlowskic31e8582015-03-24 11:21:17 +010034static const char * const axp20x_model_names[] = {
Michal Suchanekd8d79f82015-07-11 14:59:56 +020035 "AXP152",
Jacob Panaf7e9062014-10-06 21:17:14 -070036 "AXP202",
37 "AXP209",
Boris BREZILLONf05be582015-04-10 12:09:01 +080038 "AXP221",
Chen-Yu Tsai02071f02016-02-12 10:02:44 +080039 "AXP223",
Jacob Panaf7e9062014-10-06 21:17:14 -070040 "AXP288",
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +080041 "AXP806",
Chen-Yu Tsai20147f02016-03-29 17:22:26 +080042 "AXP809",
Jacob Panaf7e9062014-10-06 21:17:14 -070043};
44
Michal Suchanekd8d79f82015-07-11 14:59:56 +020045static const struct regmap_range axp152_writeable_ranges[] = {
46 regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
47 regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
48};
49
50static const struct regmap_range axp152_volatile_ranges[] = {
51 regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
52 regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
53 regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
54};
55
56static const struct regmap_access_table axp152_writeable_table = {
57 .yes_ranges = axp152_writeable_ranges,
58 .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
59};
60
61static const struct regmap_access_table axp152_volatile_table = {
62 .yes_ranges = axp152_volatile_ranges,
63 .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
64};
65
Carlo Caionecfb61a42014-05-01 14:29:27 +020066static const struct regmap_range axp20x_writeable_ranges[] = {
67 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
68 regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
Bruno Prémont553ed4b2015-08-08 17:58:40 +020069 regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
Carlo Caionecfb61a42014-05-01 14:29:27 +020070};
71
72static const struct regmap_range axp20x_volatile_ranges[] = {
Bruno Prémont553ed4b2015-08-08 17:58:40 +020073 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
74 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
Carlo Caionecfb61a42014-05-01 14:29:27 +020075 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
Bruno Prémont553ed4b2015-08-08 17:58:40 +020076 regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
77 regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
78 regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
Carlo Caionecfb61a42014-05-01 14:29:27 +020079};
80
81static const struct regmap_access_table axp20x_writeable_table = {
82 .yes_ranges = axp20x_writeable_ranges,
83 .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
84};
85
86static const struct regmap_access_table axp20x_volatile_table = {
87 .yes_ranges = axp20x_volatile_ranges,
88 .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
89};
90
Chen-Yu Tsai20147f02016-03-29 17:22:26 +080091/* AXP22x ranges are shared with the AXP809, as they cover the same range */
Boris BREZILLONf05be582015-04-10 12:09:01 +080092static const struct regmap_range axp22x_writeable_ranges[] = {
93 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
94 regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
95};
96
97static const struct regmap_range axp22x_volatile_ranges[] = {
Hans de Goede15093252016-05-14 19:51:28 +020098 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_PWR_OP_MODE),
Boris BREZILLONf05be582015-04-10 12:09:01 +080099 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
Hans de Goede15093252016-05-14 19:51:28 +0200100 regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE),
Icenowy Zheng3f895862016-07-01 17:29:23 +0800101 regmap_reg_range(AXP22X_PMIC_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
Hans de Goede15093252016-05-14 19:51:28 +0200102 regmap_reg_range(AXP20X_FG_RES, AXP20X_FG_RES),
Boris BREZILLONf05be582015-04-10 12:09:01 +0800103};
104
105static const struct regmap_access_table axp22x_writeable_table = {
106 .yes_ranges = axp22x_writeable_ranges,
107 .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
108};
109
110static const struct regmap_access_table axp22x_volatile_table = {
111 .yes_ranges = axp22x_volatile_ranges,
112 .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
113};
114
Jacob Panaf7e9062014-10-06 21:17:14 -0700115static const struct regmap_range axp288_writeable_ranges[] = {
116 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
117 regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
118};
119
120static const struct regmap_range axp288_volatile_ranges[] = {
121 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
122};
123
124static const struct regmap_access_table axp288_writeable_table = {
125 .yes_ranges = axp288_writeable_ranges,
126 .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
127};
128
129static const struct regmap_access_table axp288_volatile_table = {
130 .yes_ranges = axp288_volatile_ranges,
131 .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
132};
133
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800134static const struct regmap_range axp806_writeable_ranges[] = {
135 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_DATACACHE(3)),
136 regmap_reg_range(AXP806_PWR_OUT_CTRL1, AXP806_CLDO3_V_CTRL),
137 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ2_EN),
138 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
Chen-Yu Tsai34d90302016-11-11 11:29:52 +0800139 regmap_reg_range(AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT),
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800140};
141
142static const struct regmap_range axp806_volatile_ranges[] = {
143 regmap_reg_range(AXP20X_IRQ1_STATE, AXP20X_IRQ2_STATE),
144};
145
146static const struct regmap_access_table axp806_writeable_table = {
147 .yes_ranges = axp806_writeable_ranges,
148 .n_yes_ranges = ARRAY_SIZE(axp806_writeable_ranges),
149};
150
151static const struct regmap_access_table axp806_volatile_table = {
152 .yes_ranges = axp806_volatile_ranges,
153 .n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges),
154};
155
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200156static struct resource axp152_pek_resources[] = {
157 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
158 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
159};
160
Michael Haascd7cf272016-05-06 07:19:49 +0200161static struct resource axp20x_ac_power_supply_resources[] = {
162 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"),
163 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"),
164 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
165};
166
Carlo Caionecfb61a42014-05-01 14:29:27 +0200167static struct resource axp20x_pek_resources[] = {
168 {
169 .name = "PEK_DBR",
170 .start = AXP20X_IRQ_PEK_RIS_EDGE,
171 .end = AXP20X_IRQ_PEK_RIS_EDGE,
172 .flags = IORESOURCE_IRQ,
173 }, {
174 .name = "PEK_DBF",
175 .start = AXP20X_IRQ_PEK_FAL_EDGE,
176 .end = AXP20X_IRQ_PEK_FAL_EDGE,
177 .flags = IORESOURCE_IRQ,
178 },
179};
180
Hans de Goede8de4efd2015-08-08 17:58:41 +0200181static struct resource axp20x_usb_power_supply_resources[] = {
182 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
183 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
184 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
185 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
186};
187
Hans de Goedeecd98cc2016-06-02 19:18:55 +0200188static struct resource axp22x_usb_power_supply_resources[] = {
189 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
190 DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
191};
192
Boris BREZILLONf05be582015-04-10 12:09:01 +0800193static struct resource axp22x_pek_resources[] = {
194 {
195 .name = "PEK_DBR",
196 .start = AXP22X_IRQ_PEK_RIS_EDGE,
197 .end = AXP22X_IRQ_PEK_RIS_EDGE,
198 .flags = IORESOURCE_IRQ,
199 }, {
200 .name = "PEK_DBF",
201 .start = AXP22X_IRQ_PEK_FAL_EDGE,
202 .end = AXP22X_IRQ_PEK_FAL_EDGE,
203 .flags = IORESOURCE_IRQ,
204 },
205};
206
Borun Fue56e5ad2015-10-14 16:16:26 +0800207static struct resource axp288_power_button_resources[] = {
208 {
209 .name = "PEK_DBR",
210 .start = AXP288_IRQ_POKN,
211 .end = AXP288_IRQ_POKN,
212 .flags = IORESOURCE_IRQ,
213 },
214 {
215 .name = "PEK_DBF",
216 .start = AXP288_IRQ_POKP,
217 .end = AXP288_IRQ_POKP,
218 .flags = IORESOURCE_IRQ,
219 },
220};
221
Todd Brandtd63878742015-02-02 15:41:41 -0800222static struct resource axp288_fuel_gauge_resources[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700223 {
224 .start = AXP288_IRQ_QWBTU,
225 .end = AXP288_IRQ_QWBTU,
226 .flags = IORESOURCE_IRQ,
227 },
228 {
229 .start = AXP288_IRQ_WBTU,
230 .end = AXP288_IRQ_WBTU,
231 .flags = IORESOURCE_IRQ,
232 },
233 {
234 .start = AXP288_IRQ_QWBTO,
235 .end = AXP288_IRQ_QWBTO,
236 .flags = IORESOURCE_IRQ,
237 },
238 {
239 .start = AXP288_IRQ_WBTO,
240 .end = AXP288_IRQ_WBTO,
241 .flags = IORESOURCE_IRQ,
242 },
243 {
244 .start = AXP288_IRQ_WL2,
245 .end = AXP288_IRQ_WL2,
246 .flags = IORESOURCE_IRQ,
247 },
248 {
249 .start = AXP288_IRQ_WL1,
250 .end = AXP288_IRQ_WL1,
251 .flags = IORESOURCE_IRQ,
252 },
253};
254
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800255static struct resource axp809_pek_resources[] = {
256 {
257 .name = "PEK_DBR",
258 .start = AXP809_IRQ_PEK_RIS_EDGE,
259 .end = AXP809_IRQ_PEK_RIS_EDGE,
260 .flags = IORESOURCE_IRQ,
261 }, {
262 .name = "PEK_DBF",
263 .start = AXP809_IRQ_PEK_FAL_EDGE,
264 .end = AXP809_IRQ_PEK_FAL_EDGE,
265 .flags = IORESOURCE_IRQ,
266 },
267};
268
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200269static const struct regmap_config axp152_regmap_config = {
270 .reg_bits = 8,
271 .val_bits = 8,
272 .wr_table = &axp152_writeable_table,
273 .volatile_table = &axp152_volatile_table,
274 .max_register = AXP152_PWM1_DUTY_CYCLE,
275 .cache_type = REGCACHE_RBTREE,
276};
277
Carlo Caionecfb61a42014-05-01 14:29:27 +0200278static const struct regmap_config axp20x_regmap_config = {
279 .reg_bits = 8,
280 .val_bits = 8,
281 .wr_table = &axp20x_writeable_table,
282 .volatile_table = &axp20x_volatile_table,
Bruno Prémont553ed4b2015-08-08 17:58:40 +0200283 .max_register = AXP20X_OCV(AXP20X_OCV_MAX),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200284 .cache_type = REGCACHE_RBTREE,
285};
286
Boris BREZILLONf05be582015-04-10 12:09:01 +0800287static const struct regmap_config axp22x_regmap_config = {
288 .reg_bits = 8,
289 .val_bits = 8,
290 .wr_table = &axp22x_writeable_table,
291 .volatile_table = &axp22x_volatile_table,
292 .max_register = AXP22X_BATLOW_THRES1,
293 .cache_type = REGCACHE_RBTREE,
294};
295
Jacob Panaf7e9062014-10-06 21:17:14 -0700296static const struct regmap_config axp288_regmap_config = {
297 .reg_bits = 8,
298 .val_bits = 8,
299 .wr_table = &axp288_writeable_table,
300 .volatile_table = &axp288_volatile_table,
301 .max_register = AXP288_FG_TUNE5,
302 .cache_type = REGCACHE_RBTREE,
303};
304
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800305static const struct regmap_config axp806_regmap_config = {
306 .reg_bits = 8,
307 .val_bits = 8,
308 .wr_table = &axp806_writeable_table,
309 .volatile_table = &axp806_volatile_table,
Chen-Yu Tsai34d90302016-11-11 11:29:52 +0800310 .max_register = AXP806_REG_ADDR_EXT,
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800311 .cache_type = REGCACHE_RBTREE,
312};
313
Jacob Panaf7e9062014-10-06 21:17:14 -0700314#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
315 [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
Carlo Caionecfb61a42014-05-01 14:29:27 +0200316
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200317static const struct regmap_irq axp152_regmap_irqs[] = {
318 INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
319 INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
320 INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
321 INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
322 INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
323 INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
324 INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
325 INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
326 INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
327 INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
328 INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
329 INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
330 INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
331 INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
332 INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
333 INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
334 INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
335};
336
Carlo Caionecfb61a42014-05-01 14:29:27 +0200337static const struct regmap_irq axp20x_regmap_irqs[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700338 INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
339 INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
340 INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
341 INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
342 INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
343 INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
344 INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
345 INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
346 INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
347 INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
348 INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
349 INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
350 INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
351 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
352 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
353 INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
354 INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
355 INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
356 INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
357 INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
358 INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
359 INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
360 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
361 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
362 INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
363 INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
364 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
365 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
366 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
367 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
368 INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
369 INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
370 INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
371 INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
372 INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
373 INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
374 INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
375};
376
Boris BREZILLONf05be582015-04-10 12:09:01 +0800377static const struct regmap_irq axp22x_regmap_irqs[] = {
378 INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
379 INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
380 INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
381 INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
382 INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
383 INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
384 INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
385 INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
386 INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
387 INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
388 INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
389 INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
390 INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
391 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
392 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
393 INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
394 INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
395 INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
396 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
397 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
398 INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
399 INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
400 INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
401 INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
402 INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
403};
404
Jacob Panaf7e9062014-10-06 21:17:14 -0700405/* some IRQs are compatible with axp20x models */
406static const struct regmap_irq axp288_regmap_irqs[] = {
Jacob Panff3bbc52014-11-11 11:30:09 -0800407 INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
408 INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
409 INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
Hans de Goede8b44e672016-12-14 14:52:06 +0100410 INIT_REGMAP_IRQ(AXP288, FALLING_ALT, 0, 5),
411 INIT_REGMAP_IRQ(AXP288, RISING_ALT, 0, 6),
412 INIT_REGMAP_IRQ(AXP288, OV_ALT, 0, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700413
Jacob Panff3bbc52014-11-11 11:30:09 -0800414 INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
415 INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
Jacob Panaf7e9062014-10-06 21:17:14 -0700416 INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
417 INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
Jacob Panff3bbc52014-11-11 11:30:09 -0800418 INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
419 INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700420
421 INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
422 INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
423 INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
Jacob Panff3bbc52014-11-11 11:30:09 -0800424 INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
Jacob Panaf7e9062014-10-06 21:17:14 -0700425 INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
426 INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
427 INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
428 INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
429
430 INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
431 INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
432 INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
433 INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
434
435 INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
436 INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
437 INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
438 INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
439 INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
440 INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
441 INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
Jacob Panff3bbc52014-11-11 11:30:09 -0800442 INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700443
444 INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
445 INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200446};
447
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800448static const struct regmap_irq axp806_regmap_irqs[] = {
449 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV1, 0, 0),
450 INIT_REGMAP_IRQ(AXP806, DIE_TEMP_HIGH_LV2, 0, 1),
451 INIT_REGMAP_IRQ(AXP806, DCDCA_V_LOW, 0, 3),
452 INIT_REGMAP_IRQ(AXP806, DCDCB_V_LOW, 0, 4),
453 INIT_REGMAP_IRQ(AXP806, DCDCC_V_LOW, 0, 5),
454 INIT_REGMAP_IRQ(AXP806, DCDCD_V_LOW, 0, 6),
455 INIT_REGMAP_IRQ(AXP806, DCDCE_V_LOW, 0, 7),
456 INIT_REGMAP_IRQ(AXP806, PWROK_LONG, 1, 0),
457 INIT_REGMAP_IRQ(AXP806, PWROK_SHORT, 1, 1),
458 INIT_REGMAP_IRQ(AXP806, WAKEUP, 1, 4),
459 INIT_REGMAP_IRQ(AXP806, PWROK_FALL, 1, 5),
460 INIT_REGMAP_IRQ(AXP806, PWROK_RISE, 1, 6),
461};
462
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800463static const struct regmap_irq axp809_regmap_irqs[] = {
464 INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7),
465 INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6),
466 INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5),
467 INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4),
468 INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3),
469 INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2),
470 INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1),
471 INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7),
472 INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6),
473 INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5),
474 INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4),
475 INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3),
476 INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2),
477 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7),
478 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6),
479 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5),
480 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4),
481 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3),
482 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2),
483 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1),
484 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0),
485 INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7),
486 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1),
487 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0),
488 INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7),
489 INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6),
490 INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5),
491 INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4),
492 INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3),
493 INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2),
494 INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1),
495 INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
496};
497
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200498static const struct regmap_irq_chip axp152_regmap_irq_chip = {
499 .name = "axp152_irq_chip",
500 .status_base = AXP152_IRQ1_STATE,
501 .ack_base = AXP152_IRQ1_STATE,
502 .mask_base = AXP152_IRQ1_EN,
503 .mask_invert = true,
504 .init_ack_masked = true,
505 .irqs = axp152_regmap_irqs,
506 .num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
507 .num_regs = 3,
508};
509
Carlo Caionecfb61a42014-05-01 14:29:27 +0200510static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
511 .name = "axp20x_irq_chip",
512 .status_base = AXP20X_IRQ1_STATE,
513 .ack_base = AXP20X_IRQ1_STATE,
514 .mask_base = AXP20X_IRQ1_EN,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200515 .mask_invert = true,
516 .init_ack_masked = true,
Jacob Panaf7e9062014-10-06 21:17:14 -0700517 .irqs = axp20x_regmap_irqs,
518 .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
519 .num_regs = 5,
520
521};
522
Boris BREZILLONf05be582015-04-10 12:09:01 +0800523static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
524 .name = "axp22x_irq_chip",
525 .status_base = AXP20X_IRQ1_STATE,
526 .ack_base = AXP20X_IRQ1_STATE,
527 .mask_base = AXP20X_IRQ1_EN,
528 .mask_invert = true,
529 .init_ack_masked = true,
530 .irqs = axp22x_regmap_irqs,
531 .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
532 .num_regs = 5,
533};
534
Jacob Panaf7e9062014-10-06 21:17:14 -0700535static const struct regmap_irq_chip axp288_regmap_irq_chip = {
536 .name = "axp288_irq_chip",
537 .status_base = AXP20X_IRQ1_STATE,
538 .ack_base = AXP20X_IRQ1_STATE,
539 .mask_base = AXP20X_IRQ1_EN,
540 .mask_invert = true,
541 .init_ack_masked = true,
542 .irqs = axp288_regmap_irqs,
543 .num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
544 .num_regs = 6,
545
Carlo Caionecfb61a42014-05-01 14:29:27 +0200546};
547
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800548static const struct regmap_irq_chip axp806_regmap_irq_chip = {
549 .name = "axp806",
550 .status_base = AXP20X_IRQ1_STATE,
551 .ack_base = AXP20X_IRQ1_STATE,
552 .mask_base = AXP20X_IRQ1_EN,
553 .mask_invert = true,
554 .init_ack_masked = true,
555 .irqs = axp806_regmap_irqs,
556 .num_irqs = ARRAY_SIZE(axp806_regmap_irqs),
557 .num_regs = 2,
558};
559
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800560static const struct regmap_irq_chip axp809_regmap_irq_chip = {
561 .name = "axp809",
562 .status_base = AXP20X_IRQ1_STATE,
563 .ack_base = AXP20X_IRQ1_STATE,
564 .mask_base = AXP20X_IRQ1_EN,
565 .mask_invert = true,
566 .init_ack_masked = true,
567 .irqs = axp809_regmap_irqs,
568 .num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
569 .num_regs = 5,
570};
571
Carlo Caionecfb61a42014-05-01 14:29:27 +0200572static struct mfd_cell axp20x_cells[] = {
573 {
Maxime Ripardb419c162016-07-20 16:11:37 +0200574 .name = "axp20x-gpio",
575 .of_compatible = "x-powers,axp209-gpio",
576 }, {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200577 .name = "axp20x-pek",
578 .num_resources = ARRAY_SIZE(axp20x_pek_resources),
579 .resources = axp20x_pek_resources,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200580 }, {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200581 .name = "axp20x-regulator",
582 }, {
Michael Haascd7cf272016-05-06 07:19:49 +0200583 .name = "axp20x-ac-power-supply",
584 .of_compatible = "x-powers,axp202-ac-power-supply",
585 .num_resources = ARRAY_SIZE(axp20x_ac_power_supply_resources),
586 .resources = axp20x_ac_power_supply_resources,
587 }, {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200588 .name = "axp20x-usb-power-supply",
589 .of_compatible = "x-powers,axp202-usb-power-supply",
590 .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources),
591 .resources = axp20x_usb_power_supply_resources,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200592 },
593};
594
Boris BREZILLONf05be582015-04-10 12:09:01 +0800595static struct mfd_cell axp22x_cells[] = {
596 {
597 .name = "axp20x-pek",
598 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
599 .resources = axp22x_pek_resources,
Chen-Yu Tsai6d4fa892015-04-10 12:09:06 +0800600 }, {
601 .name = "axp20x-regulator",
Hans de Goedeecd98cc2016-06-02 19:18:55 +0200602 }, {
603 .name = "axp20x-usb-power-supply",
604 .of_compatible = "x-powers,axp221-usb-power-supply",
605 .num_resources = ARRAY_SIZE(axp22x_usb_power_supply_resources),
606 .resources = axp22x_usb_power_supply_resources,
Boris BREZILLONf05be582015-04-10 12:09:01 +0800607 },
608};
609
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200610static struct mfd_cell axp152_cells[] = {
611 {
612 .name = "axp20x-pek",
613 .num_resources = ARRAY_SIZE(axp152_pek_resources),
614 .resources = axp152_pek_resources,
615 },
616};
617
Jacob Panaf7e9062014-10-06 21:17:14 -0700618static struct resource axp288_adc_resources[] = {
619 {
620 .name = "GPADC",
621 .start = AXP288_IRQ_GPADC,
622 .end = AXP288_IRQ_GPADC,
623 .flags = IORESOURCE_IRQ,
624 },
625};
626
Ramakrishna Pallalabdb01f72015-04-03 00:49:47 +0530627static struct resource axp288_extcon_resources[] = {
628 {
629 .start = AXP288_IRQ_VBUS_FALL,
630 .end = AXP288_IRQ_VBUS_FALL,
631 .flags = IORESOURCE_IRQ,
632 },
633 {
634 .start = AXP288_IRQ_VBUS_RISE,
635 .end = AXP288_IRQ_VBUS_RISE,
636 .flags = IORESOURCE_IRQ,
637 },
638 {
639 .start = AXP288_IRQ_MV_CHNG,
640 .end = AXP288_IRQ_MV_CHNG,
641 .flags = IORESOURCE_IRQ,
642 },
643 {
644 .start = AXP288_IRQ_BC_USB_CHNG,
645 .end = AXP288_IRQ_BC_USB_CHNG,
646 .flags = IORESOURCE_IRQ,
647 },
648};
649
Jacob Panaf7e9062014-10-06 21:17:14 -0700650static struct resource axp288_charger_resources[] = {
651 {
652 .start = AXP288_IRQ_OV,
653 .end = AXP288_IRQ_OV,
654 .flags = IORESOURCE_IRQ,
655 },
656 {
657 .start = AXP288_IRQ_DONE,
658 .end = AXP288_IRQ_DONE,
659 .flags = IORESOURCE_IRQ,
660 },
661 {
662 .start = AXP288_IRQ_CHARGING,
663 .end = AXP288_IRQ_CHARGING,
664 .flags = IORESOURCE_IRQ,
665 },
666 {
667 .start = AXP288_IRQ_SAFE_QUIT,
668 .end = AXP288_IRQ_SAFE_QUIT,
669 .flags = IORESOURCE_IRQ,
670 },
671 {
672 .start = AXP288_IRQ_SAFE_ENTER,
673 .end = AXP288_IRQ_SAFE_ENTER,
674 .flags = IORESOURCE_IRQ,
675 },
676 {
677 .start = AXP288_IRQ_QCBTU,
678 .end = AXP288_IRQ_QCBTU,
679 .flags = IORESOURCE_IRQ,
680 },
681 {
682 .start = AXP288_IRQ_CBTU,
683 .end = AXP288_IRQ_CBTU,
684 .flags = IORESOURCE_IRQ,
685 },
686 {
687 .start = AXP288_IRQ_QCBTO,
688 .end = AXP288_IRQ_QCBTO,
689 .flags = IORESOURCE_IRQ,
690 },
691 {
692 .start = AXP288_IRQ_CBTO,
693 .end = AXP288_IRQ_CBTO,
694 .flags = IORESOURCE_IRQ,
695 },
696};
697
698static struct mfd_cell axp288_cells[] = {
699 {
700 .name = "axp288_adc",
701 .num_resources = ARRAY_SIZE(axp288_adc_resources),
702 .resources = axp288_adc_resources,
703 },
704 {
Ramakrishna Pallalabdb01f72015-04-03 00:49:47 +0530705 .name = "axp288_extcon",
706 .num_resources = ARRAY_SIZE(axp288_extcon_resources),
707 .resources = axp288_extcon_resources,
708 },
709 {
Jacob Panaf7e9062014-10-06 21:17:14 -0700710 .name = "axp288_charger",
711 .num_resources = ARRAY_SIZE(axp288_charger_resources),
712 .resources = axp288_charger_resources,
713 },
714 {
Todd Brandtd63878742015-02-02 15:41:41 -0800715 .name = "axp288_fuel_gauge",
716 .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
717 .resources = axp288_fuel_gauge_resources,
Jacob Panaf7e9062014-10-06 21:17:14 -0700718 },
Aaron Lud8139f62014-11-24 17:24:47 +0800719 {
Borun Fue56e5ad2015-10-14 16:16:26 +0800720 .name = "axp20x-pek",
721 .num_resources = ARRAY_SIZE(axp288_power_button_resources),
722 .resources = axp288_power_button_resources,
723 },
724 {
Aaron Lud8139f62014-11-24 17:24:47 +0800725 .name = "axp288_pmic_acpi",
726 },
Jacob Panaf7e9062014-10-06 21:17:14 -0700727};
728
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800729static struct mfd_cell axp806_cells[] = {
730 {
731 .id = 2,
732 .name = "axp20x-regulator",
733 },
734};
735
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800736static struct mfd_cell axp809_cells[] = {
737 {
738 .name = "axp20x-pek",
739 .num_resources = ARRAY_SIZE(axp809_pek_resources),
740 .resources = axp809_pek_resources,
741 }, {
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800742 .id = 1,
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800743 .name = "axp20x-regulator",
744 },
745};
746
Carlo Caionecfb61a42014-05-01 14:29:27 +0200747static struct axp20x_dev *axp20x_pm_power_off;
748static void axp20x_power_off(void)
749{
Jacob Panaf7e9062014-10-06 21:17:14 -0700750 if (axp20x_pm_power_off->variant == AXP288_ID)
751 return;
752
Carlo Caionecfb61a42014-05-01 14:29:27 +0200753 regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL,
754 AXP20X_OFF);
Hans de Goede179dc632016-06-05 15:50:48 +0200755
756 /* Give capacitors etc. time to drain to avoid kernel panic msg. */
757 msleep(500);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200758}
759
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800760int axp20x_match_device(struct axp20x_dev *axp20x)
Jacob Panaf7e9062014-10-06 21:17:14 -0700761{
Chen-Yu Tsaie47a3cf2016-02-12 10:02:39 +0800762 struct device *dev = axp20x->dev;
Jacob Panaf7e9062014-10-06 21:17:14 -0700763 const struct acpi_device_id *acpi_id;
764 const struct of_device_id *of_id;
765
766 if (dev->of_node) {
Chen-Yu Tsaiaf7acc32016-02-12 10:02:40 +0800767 of_id = of_match_device(dev->driver->of_match_table, dev);
Jacob Panaf7e9062014-10-06 21:17:14 -0700768 if (!of_id) {
769 dev_err(dev, "Unable to match OF ID\n");
770 return -ENODEV;
771 }
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800772 axp20x->variant = (long)of_id->data;
Jacob Panaf7e9062014-10-06 21:17:14 -0700773 } else {
774 acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
775 if (!acpi_id || !acpi_id->driver_data) {
776 dev_err(dev, "Unable to match ACPI ID and data\n");
777 return -ENODEV;
778 }
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800779 axp20x->variant = (long)acpi_id->driver_data;
Jacob Panaf7e9062014-10-06 21:17:14 -0700780 }
781
782 switch (axp20x->variant) {
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200783 case AXP152_ID:
784 axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
785 axp20x->cells = axp152_cells;
786 axp20x->regmap_cfg = &axp152_regmap_config;
787 axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
788 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700789 case AXP202_ID:
790 case AXP209_ID:
791 axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
792 axp20x->cells = axp20x_cells;
793 axp20x->regmap_cfg = &axp20x_regmap_config;
794 axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
795 break;
Boris BREZILLONf05be582015-04-10 12:09:01 +0800796 case AXP221_ID:
Chen-Yu Tsai02071f02016-02-12 10:02:44 +0800797 case AXP223_ID:
Boris BREZILLONf05be582015-04-10 12:09:01 +0800798 axp20x->nr_cells = ARRAY_SIZE(axp22x_cells);
799 axp20x->cells = axp22x_cells;
800 axp20x->regmap_cfg = &axp22x_regmap_config;
801 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
802 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700803 case AXP288_ID:
804 axp20x->cells = axp288_cells;
805 axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
806 axp20x->regmap_cfg = &axp288_regmap_config;
807 axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
Hans de Goede0a5454c2016-12-14 14:52:05 +0100808 axp20x->irq_flags = IRQF_TRIGGER_LOW;
Jacob Panaf7e9062014-10-06 21:17:14 -0700809 break;
Chen-Yu Tsai8824ee82016-08-27 15:55:38 +0800810 case AXP806_ID:
811 axp20x->nr_cells = ARRAY_SIZE(axp806_cells);
812 axp20x->cells = axp806_cells;
813 axp20x->regmap_cfg = &axp806_regmap_config;
814 axp20x->regmap_irq_chip = &axp806_regmap_irq_chip;
815 break;
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800816 case AXP809_ID:
817 axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
818 axp20x->cells = axp809_cells;
819 axp20x->regmap_cfg = &axp22x_regmap_config;
820 axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
821 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700822 default:
823 dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
824 return -EINVAL;
825 }
826 dev_info(dev, "AXP20x variant %s found\n",
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800827 axp20x_model_names[axp20x->variant]);
Jacob Panaf7e9062014-10-06 21:17:14 -0700828
829 return 0;
830}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800831EXPORT_SYMBOL(axp20x_match_device);
Jacob Panaf7e9062014-10-06 21:17:14 -0700832
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800833int axp20x_device_probe(struct axp20x_dev *axp20x)
Carlo Caionecfb61a42014-05-01 14:29:27 +0200834{
Carlo Caionecfb61a42014-05-01 14:29:27 +0200835 int ret;
836
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800837 ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
Hans de Goede0a5454c2016-12-14 14:52:05 +0100838 IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
839 -1, axp20x->regmap_irq_chip, &axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200840 if (ret) {
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800841 dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200842 return ret;
843 }
844
Jacob Panaf7e9062014-10-06 21:17:14 -0700845 ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800846 axp20x->nr_cells, NULL, 0, NULL);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200847
848 if (ret) {
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800849 dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
850 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200851 return ret;
852 }
853
854 if (!pm_power_off) {
855 axp20x_pm_power_off = axp20x;
856 pm_power_off = axp20x_power_off;
857 }
858
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800859 dev_info(axp20x->dev, "AXP20X driver loaded\n");
Carlo Caionecfb61a42014-05-01 14:29:27 +0200860
861 return 0;
862}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800863EXPORT_SYMBOL(axp20x_device_probe);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200864
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800865int axp20x_device_remove(struct axp20x_dev *axp20x)
Carlo Caionecfb61a42014-05-01 14:29:27 +0200866{
Carlo Caionecfb61a42014-05-01 14:29:27 +0200867 if (axp20x == axp20x_pm_power_off) {
868 axp20x_pm_power_off = NULL;
869 pm_power_off = NULL;
870 }
871
872 mfd_remove_devices(axp20x->dev);
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800873 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200874
875 return 0;
876}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800877EXPORT_SYMBOL(axp20x_device_remove);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200878
879MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
880MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
881MODULE_LICENSE("GPL");