Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Allwinner SoCs Reset Controller driver |
| 3 | * |
| 4 | * Copyright 2013 Maxime Ripard |
| 5 | * |
| 6 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/io.h> |
Paul Gortmaker | c4742ed | 2016-06-13 14:03:36 -0400 | [diff] [blame] | 16 | #include <linux/init.h> |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 17 | #include <linux/of.h> |
| 18 | #include <linux/of_address.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/reset-controller.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/types.h> |
| 24 | |
| 25 | struct sunxi_reset_data { |
| 26 | spinlock_t lock; |
| 27 | void __iomem *membase; |
| 28 | struct reset_controller_dev rcdev; |
| 29 | }; |
| 30 | |
| 31 | static int sunxi_reset_assert(struct reset_controller_dev *rcdev, |
| 32 | unsigned long id) |
| 33 | { |
| 34 | struct sunxi_reset_data *data = container_of(rcdev, |
| 35 | struct sunxi_reset_data, |
| 36 | rcdev); |
Andre Przywara | 11282a4 | 2017-03-06 01:35:56 +0000 | [diff] [blame] | 37 | int reg_width = sizeof(u32); |
| 38 | int bank = id / (reg_width * BITS_PER_BYTE); |
| 39 | int offset = id % (reg_width * BITS_PER_BYTE); |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 40 | unsigned long flags; |
| 41 | u32 reg; |
| 42 | |
| 43 | spin_lock_irqsave(&data->lock, flags); |
| 44 | |
Andre Przywara | 11282a4 | 2017-03-06 01:35:56 +0000 | [diff] [blame] | 45 | reg = readl(data->membase + (bank * reg_width)); |
| 46 | writel(reg & ~BIT(offset), data->membase + (bank * reg_width)); |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 47 | |
| 48 | spin_unlock_irqrestore(&data->lock, flags); |
| 49 | |
| 50 | return 0; |
| 51 | } |
| 52 | |
| 53 | static int sunxi_reset_deassert(struct reset_controller_dev *rcdev, |
| 54 | unsigned long id) |
| 55 | { |
| 56 | struct sunxi_reset_data *data = container_of(rcdev, |
| 57 | struct sunxi_reset_data, |
| 58 | rcdev); |
Andre Przywara | 11282a4 | 2017-03-06 01:35:56 +0000 | [diff] [blame] | 59 | int reg_width = sizeof(u32); |
| 60 | int bank = id / (reg_width * BITS_PER_BYTE); |
| 61 | int offset = id % (reg_width * BITS_PER_BYTE); |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 62 | unsigned long flags; |
| 63 | u32 reg; |
| 64 | |
| 65 | spin_lock_irqsave(&data->lock, flags); |
| 66 | |
Andre Przywara | 11282a4 | 2017-03-06 01:35:56 +0000 | [diff] [blame] | 67 | reg = readl(data->membase + (bank * reg_width)); |
| 68 | writel(reg | BIT(offset), data->membase + (bank * reg_width)); |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 69 | |
| 70 | spin_unlock_irqrestore(&data->lock, flags); |
| 71 | |
| 72 | return 0; |
| 73 | } |
| 74 | |
Philipp Zabel | 01501d5 | 2016-01-17 15:14:32 +0100 | [diff] [blame] | 75 | static const struct reset_control_ops sunxi_reset_ops = { |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 76 | .assert = sunxi_reset_assert, |
| 77 | .deassert = sunxi_reset_deassert, |
| 78 | }; |
| 79 | |
| 80 | static int sunxi_reset_init(struct device_node *np) |
| 81 | { |
| 82 | struct sunxi_reset_data *data; |
| 83 | struct resource res; |
| 84 | resource_size_t size; |
| 85 | int ret; |
| 86 | |
| 87 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
| 88 | if (!data) |
| 89 | return -ENOMEM; |
| 90 | |
| 91 | ret = of_address_to_resource(np, 0, &res); |
| 92 | if (ret) |
| 93 | goto err_alloc; |
| 94 | |
| 95 | size = resource_size(&res); |
| 96 | if (!request_mem_region(res.start, size, np->name)) { |
| 97 | ret = -EBUSY; |
| 98 | goto err_alloc; |
| 99 | } |
| 100 | |
| 101 | data->membase = ioremap(res.start, size); |
| 102 | if (!data->membase) { |
| 103 | ret = -ENOMEM; |
| 104 | goto err_alloc; |
| 105 | } |
| 106 | |
Tyler Baker | 41544f9 | 2015-01-12 07:54:46 -0800 | [diff] [blame] | 107 | spin_lock_init(&data->lock); |
| 108 | |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 109 | data->rcdev.owner = THIS_MODULE; |
| 110 | data->rcdev.nr_resets = size * 32; |
| 111 | data->rcdev.ops = &sunxi_reset_ops; |
| 112 | data->rcdev.of_node = np; |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 113 | |
Masahiro Yamada | d1f15aa | 2015-11-05 14:54:56 +0900 | [diff] [blame] | 114 | return reset_controller_register(&data->rcdev); |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 115 | |
| 116 | err_alloc: |
| 117 | kfree(data); |
| 118 | return ret; |
| 119 | }; |
| 120 | |
| 121 | /* |
| 122 | * These are the reset controller we need to initialize early on in |
| 123 | * our system, before we can even think of using a regular device |
| 124 | * driver for it. |
| 125 | */ |
Philipp Zabel | fddad17 | 2015-10-29 09:59:34 +0100 | [diff] [blame] | 126 | static const struct of_device_id sunxi_early_reset_dt_ids[] __initconst = { |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 127 | { .compatible = "allwinner,sun6i-a31-ahb1-reset", }, |
| 128 | { /* sentinel */ }, |
| 129 | }; |
| 130 | |
| 131 | void __init sun6i_reset_init(void) |
| 132 | { |
| 133 | struct device_node *np; |
| 134 | |
| 135 | for_each_matching_node(np, sunxi_early_reset_dt_ids) |
| 136 | sunxi_reset_init(np); |
| 137 | } |
| 138 | |
| 139 | /* |
| 140 | * And these are the controllers we can register through the regular |
| 141 | * device model. |
| 142 | */ |
| 143 | static const struct of_device_id sunxi_reset_dt_ids[] = { |
| 144 | { .compatible = "allwinner,sun6i-a31-clock-reset", }, |
| 145 | { /* sentinel */ }, |
| 146 | }; |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 147 | |
| 148 | static int sunxi_reset_probe(struct platform_device *pdev) |
| 149 | { |
Boris BREZILLON | cd90f0c | 2014-05-14 14:38:16 +0200 | [diff] [blame] | 150 | struct sunxi_reset_data *data; |
| 151 | struct resource *res; |
| 152 | |
| 153 | data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); |
| 154 | if (!data) |
| 155 | return -ENOMEM; |
| 156 | |
| 157 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 158 | data->membase = devm_ioremap_resource(&pdev->dev, res); |
| 159 | if (IS_ERR(data->membase)) |
| 160 | return PTR_ERR(data->membase); |
| 161 | |
Tyler Baker | 41544f9 | 2015-01-12 07:54:46 -0800 | [diff] [blame] | 162 | spin_lock_init(&data->lock); |
| 163 | |
Boris BREZILLON | cd90f0c | 2014-05-14 14:38:16 +0200 | [diff] [blame] | 164 | data->rcdev.owner = THIS_MODULE; |
| 165 | data->rcdev.nr_resets = resource_size(res) * 32; |
| 166 | data->rcdev.ops = &sunxi_reset_ops; |
| 167 | data->rcdev.of_node = pdev->dev.of_node; |
| 168 | |
Masahiro Yamada | 2f38a88 | 2016-05-01 19:37:01 +0900 | [diff] [blame] | 169 | return devm_reset_controller_register(&pdev->dev, &data->rcdev); |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | static struct platform_driver sunxi_reset_driver = { |
| 173 | .probe = sunxi_reset_probe, |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 174 | .driver = { |
| 175 | .name = "sunxi-reset", |
Maxime Ripard | 8f1ae77 | 2013-09-24 11:07:43 +0300 | [diff] [blame] | 176 | .of_match_table = sunxi_reset_dt_ids, |
| 177 | }, |
| 178 | }; |
Paul Gortmaker | c4742ed | 2016-06-13 14:03:36 -0400 | [diff] [blame] | 179 | builtin_platform_driver(sunxi_reset_driver); |