| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /******************************************************************************* |
| 2 | |
| 3 | |
| 4 | Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms of the GNU General Public License as published by the Free |
| 8 | Software Foundation; either version 2 of the License, or (at your option) |
| 9 | any later version. |
| 10 | |
| 11 | This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | more details. |
| 15 | |
| 16 | You should have received a copy of the GNU General Public License along with |
| 17 | this program; if not, write to the Free Software Foundation, Inc., 59 |
| 18 | Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 19 | |
| 20 | The full GNU General Public License is included in this distribution in the |
| 21 | file called LICENSE. |
| 22 | |
| 23 | Contact Information: |
| 24 | Linux NICS <linux.nics@intel.com> |
| 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 26 | |
| 27 | *******************************************************************************/ |
| 28 | |
| 29 | /* glue for the OS independent part of ixgb |
| 30 | * includes register access macros |
| 31 | */ |
| 32 | |
| 33 | #ifndef _IXGB_OSDEP_H_ |
| 34 | #define _IXGB_OSDEP_H_ |
| 35 | |
| 36 | #include <linux/types.h> |
| 37 | #include <linux/pci.h> |
| 38 | #include <linux/delay.h> |
| 39 | #include <asm/io.h> |
| 40 | #include <linux/interrupt.h> |
| 41 | #include <linux/sched.h> |
| 42 | |
| 43 | #ifndef msec_delay |
| 44 | #define msec_delay(x) do { if(in_interrupt()) { \ |
| 45 | /* Don't mdelay in interrupt context! */ \ |
| 46 | BUG(); \ |
| 47 | } else { \ |
| 48 | set_current_state(TASK_UNINTERRUPTIBLE); \ |
| 49 | schedule_timeout((x * HZ)/1000 + 2); \ |
| 50 | } } while(0) |
| 51 | #endif |
| 52 | |
| 53 | #define PCI_COMMAND_REGISTER PCI_COMMAND |
| 54 | #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE |
| 55 | |
| 56 | typedef enum { |
| 57 | #undef FALSE |
| 58 | FALSE = 0, |
| 59 | #undef TRUE |
| 60 | TRUE = 1 |
| 61 | } boolean_t; |
| 62 | |
| 63 | #undef ASSERT |
| 64 | #define ASSERT(x) if(!(x)) BUG() |
| 65 | #define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B) |
| 66 | |
| 67 | #ifdef DBG |
| 68 | #define DEBUGOUT(S) printk(KERN_DEBUG S "\n") |
| 69 | #define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A) |
| 70 | #else |
| 71 | #define DEBUGOUT(S) |
| 72 | #define DEBUGOUT1(S, A...) |
| 73 | #endif |
| 74 | |
| 75 | #define DEBUGFUNC(F) DEBUGOUT(F) |
| 76 | #define DEBUGOUT2 DEBUGOUT1 |
| 77 | #define DEBUGOUT3 DEBUGOUT2 |
| 78 | #define DEBUGOUT7 DEBUGOUT3 |
| 79 | |
| 80 | #define IXGB_WRITE_REG(a, reg, value) ( \ |
| 81 | writel((value), ((a)->hw_addr + IXGB_##reg))) |
| 82 | |
| 83 | #define IXGB_READ_REG(a, reg) ( \ |
| 84 | readl((a)->hw_addr + IXGB_##reg)) |
| 85 | |
| 86 | #define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \ |
| 87 | writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2)))) |
| 88 | |
| 89 | #define IXGB_READ_REG_ARRAY(a, reg, offset) ( \ |
| 90 | readl((a)->hw_addr + IXGB_##reg + ((offset) << 2))) |
| 91 | |
| 92 | #define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS) |
| 93 | |
| 94 | #define IXGB_MEMCPY memcpy |
| 95 | |
| 96 | #endif /* _IXGB_OSDEP_H_ */ |