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gerrit-public.fairphone.software / kernel / msm-4.19 / 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 / . / drivers / video / i810 / i810.h
blob: fe3b757947563ec23b8e347bb958c6ca4a0e8262 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame^]1/*-*- linux-c -*-
2 * linux/drivers/video/i810.h -- Intel 810 General Definitions/Declarations
3 *
4 * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
5 * All Rights Reserved
6 *
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive for
10 * more details.
11 */
12
13#ifndef __I810_H__
14#define __I810_H__
15
16#include <linux/list.h>
17#include <linux/agp_backend.h>
18#include <linux/fb.h>
19#include <video/vga.h>
20
21/* Fence */
22#define TILEWALK_X (0 << 12)
23#define TILEWALK_Y (1 << 12)
24
25/* Raster ops */
26#define COLOR_COPY_ROP 0xF0
27#define PAT_COPY_ROP 0xCC
28#define CLEAR_ROP 0x00
29#define WHITE_ROP 0xFF
30#define INVERT_ROP 0x55
31#define XOR_ROP 0x5A
32
33/* 2D Engine definitions */
34#define SOLIDPATTERN 0x80000000
35#define NONSOLID 0x00000000
36#define BPP8 (0 << 24)
37#define BPP16 (1 << 24)
38#define BPP24 (2 << 24)
39
40#define PIXCONF8 (2 << 16)
41#define PIXCONF15 (4 << 16)
42#define PIXCONF16 (5 << 16)
43#define PIXCONF24 (6 << 16)
44#define PIXCONF32 (7 << 16)
45
46#define DYN_COLOR_EN (1 << 26)
47#define DYN_COLOR_DIS (0 << 26)
48#define INCREMENT 0x00000000
49#define DECREMENT (0x01 << 30)
50#define ARB_ON 0x00000001
51#define ARB_OFF 0x00000000
52#define SYNC_FLIP 0x00000000
53#define ASYNC_FLIP 0x00000040
54#define OPTYPE_MASK 0xE0000000
55#define PARSER_MASK 0x001F8000
56#define D2_MASK 0x001FC000 /* 2D mask */
57
58/* Instruction type */
59/* There are more but pertains to 3D */
60#define PARSER 0x00000000
61#define BLIT (0x02 << 29)
62#define RENDER (0x03 << 29)
63
64/* Parser */
65#define NOP 0x00 /* No operation, padding */
66#define BP_INT (0x01 << 23) /* Breakpoint interrupt */
67#define USR_INT (0x02 << 23) /* User interrupt */
68#define WAIT_FOR_EVNT (0x03 << 23) /* Wait for event */
69#define FLUSH (0x04 << 23)
70#define CONTEXT_SEL (0x05 << 23)
71#define REPORT_HEAD (0x07 << 23)
72#define ARB_ON_OFF (0x08 << 23)
73#define OVERLAY_FLIP (0x11 << 23)
74#define LOAD_SCAN_INC (0x12 << 23)
75#define LOAD_SCAN_EX (0x13 << 23)
76#define FRONT_BUFFER (0x14 << 23)
77#define DEST_BUFFER (0x15 << 23)
78#define Z_BUFFER (0x16 << 23)
79
80#define STORE_DWORD_IMM (0x20 << 23)
81#define STORE_DWORD_IDX (0x21 << 23)
82#define BATCH_BUFFER (0x30 << 23)
83
84/* Blit */
85#define SETUP_BLIT 0x00
86#define SETUP_MONO_PATTERN_SL_BLT (0x10 << 22)
87#define PIXEL_BLT (0x20 << 22)
88#define SCANLINE_BLT (0x21 << 22)
89#define TEXT_BLT (0x22 << 22)
90#define TEXT_IMM_BLT (0x30 << 22)
91#define COLOR_BLT (0x40 << 22)
92#define MONO_PAT_BLIT (0x42 << 22)
93#define SOURCE_COPY_BLIT (0x43 << 22)
94#define MONO_SOURCE_COPY_BLIT (0x44 << 22)
95#define SOURCE_COPY_IMMEDIATE (0x60 << 22)
96#define MONO_SOURCE_COPY_IMMEDIATE (0x61 << 22)
97
98#define VERSION_MAJOR 0
99#define VERSION_MINOR 9
100#define VERSION_TEENIE 0
101#define BRANCH_VERSION ""
102
103
104/* mvo: intel i815 */
105#ifndef PCI_DEVICE_ID_INTEL_82815_100
106 #define PCI_DEVICE_ID_INTEL_82815_100 0x1102
107#endif
108#ifndef PCI_DEVICE_ID_INTEL_82815_NOAGP
109 #define PCI_DEVICE_ID_INTEL_82815_NOAGP 0x1112
110#endif
111#ifndef PCI_DEVICE_ID_INTEL_82815_FULL_CTRL
112 #define PCI_DEVICE_ID_INTEL_82815_FULL_CTRL 0x1130
113#endif
114
115/* General Defines */
116#define I810_PAGESIZE 4096
117#define MAX_DMA_SIZE (1024 * 4096)
118#define SAREA_SIZE 4096
119#define PCI_I810_MISCC 0x72
120#define MMIO_SIZE (512*1024)
121#define GTT_SIZE (16*1024)
122#define RINGBUFFER_SIZE (64*1024)
123#define CURSOR_SIZE 4096
124#define OFF 0
125#define ON 1
126#define MAX_KEY 256
127#define WAIT_COUNT 10000000
128#define IRING_PAD 8
129#define FONTDATAMAX 8192
130/* Masks (AND ops) and OR's */
131#define FB_START_MASK (0x3f << (32 - 6))
132#define MMIO_ADDR_MASK (0x1FFF << (32 - 13))
133#define FREQ_MASK 0x1EF
134#define SCR_OFF 0x20
135#define DRAM_ON 0x08
136#define DRAM_OFF 0xE7
137#define PG_ENABLE_MASK 0x01
138#define RING_SIZE_MASK (RINGBUFFER_SIZE - 1);
139
140/* defines for restoring registers partially */
141#define ADDR_MAP_MASK (0x07 << 5)
142#define DISP_CTRL ~0
143#define PIXCONF_0 (0x64 << 8)
144#define PIXCONF_2 (0xF3 << 24)
145#define PIXCONF_1 (0xF0 << 16)
146#define MN_MASK 0x3FF03FF
147#define P_OR (0x7 << 4)
148#define DAC_BIT (1 << 16)
149#define INTERLACE_BIT (1 << 7)
150#define IER_MASK (3 << 13)
151#define IMR_MASK (3 << 13)
152
153/* Power Management */
154#define DPMS_MASK 0xF0000
155#define POWERON 0x00000
156#define STANDBY 0x20000
157#define SUSPEND 0x80000
158#define POWERDOWN 0xA0000
159#define EMR_MASK ~0x3F
160#define FW_BLC_MASK ~(0x3F|(7 << 8)|(0x3F << 12)|(7 << 20))
161
162/* Ringbuffer */
163#define RBUFFER_START_MASK 0xFFFFF000
164#define RBUFFER_SIZE_MASK 0x001FF000
165#define RBUFFER_HEAD_MASK 0x001FFFFC
166#define RBUFFER_TAIL_MASK 0x001FFFF8
167
168/* Video Timings */
169#define REF_FREQ 24000000
170#define TARGET_N_MAX 30
171
172#define MAX_PIXELCLOCK 230000000
173#define MIN_PIXELCLOCK 15000000
174#define VFMAX 60
175#define VFMIN 60
176#define HFMAX 30000
177#define HFMIN 29000
178
179/* Cursor */
180#define CURSOR_ENABLE_MASK 0x1000
181#define CURSOR_MODE_64_TRANS 4
182#define CURSOR_MODE_64_XOR 5
183#define CURSOR_MODE_64_3C 6
184#define COORD_INACTIVE 0
185#define COORD_ACTIVE (1 << 4)
186#define EXTENDED_PALETTE 1
187
188/* AGP Memory Types*/
189#define AGP_NORMAL_MEMORY 0
190#define AGP_DCACHE_MEMORY 1
191#define AGP_PHYSICAL_MEMORY 2
192
193/* Allocated resource Flags */
194#define FRAMEBUFFER_REQ 1
195#define MMIO_REQ 2
196#define PCI_DEVICE_ENABLED 4
197#define HAS_FONTCACHE 8
198
199/* driver flags */
200#define HAS_MTRR 1
201#define HAS_ACCELERATION 2
202#define ALWAYS_SYNC 4
203#define LOCKUP 8
204#define USE_HWCUR 16
205
206struct gtt_data {
207 struct agp_memory *i810_fb_memory;
208 struct agp_memory *i810_cursor_memory;
209};
210
211struct mode_registers {
212 u32 pixclock, M, N, P;
213 u8 cr00, cr01, cr02, cr03;
214 u8 cr04, cr05, cr06, cr07;
215 u8 cr09, cr10, cr11, cr12;
216 u8 cr13, cr15, cr16, cr30;
217 u8 cr31, cr32, cr33, cr35, cr39;
218 u32 bpp8_100, bpp16_100;
219 u32 bpp24_100, bpp8_133;
220 u32 bpp16_133, bpp24_133;
221 u8 msr;
222};
223
224struct heap_data {
225 unsigned long physical;
226 __u8 __iomem *virtual;
227 u32 offset;
228 u32 size;
229};
230
231struct state_registers {
232 u32 dclk_1d, dclk_2d, dclk_0ds;
233 u32 pixconf, fw_blc, pgtbl_ctl;
234 u32 fence0, hws_pga, dplystas;
235 u16 bltcntl, hwstam, ier, iir, imr;
236 u8 cr00, cr01, cr02, cr03, cr04;
237 u8 cr05, cr06, cr07, cr08, cr09;
238 u8 cr10, cr11, cr12, cr13, cr14;
239 u8 cr15, cr16, cr17, cr80, gr10;
240 u8 cr30, cr31, cr32, cr33, cr35;
241 u8 cr39, cr41, cr70, sr01, msr;
242};
243
244struct i810fb_par {
245 struct mode_registers regs;
246 struct state_registers hw_state;
247 struct gtt_data i810_gtt;
248 struct fb_ops i810fb_ops;
249 struct pci_dev *dev;
250 struct heap_data aperture;
251 struct heap_data fb;
252 struct heap_data iring;
253 struct heap_data cursor_heap;
254 struct vgastate state;
255 atomic_t use_count;
256 u32 pseudo_palette[17];
257 unsigned long mmio_start_phys;
258 u8 __iomem *mmio_start_virtual;
259 u32 pitch;
260 u32 pixconf;
261 u32 watermark;
262 u32 mem_freq;
263 u32 res_flags;
264 u32 dev_flags;
265 u32 cur_tail;
266 u32 depth;
267 u32 blit_bpp;
268 u32 ovract;
269 u32 cur_state;
270 int mtrr_reg;
271 u16 bltcntl;
272 u8 interlace;
273};
274
275/*
276 * Register I/O
277 */
278#define i810_readb(where, mmio) readb(mmio + where)
279#define i810_readw(where, mmio) readw(mmio + where)
280#define i810_readl(where, mmio) readl(mmio + where)
281#define i810_writeb(where, mmio, val) writeb(val, mmio + where)
282#define i810_writew(where, mmio, val) writew(val, mmio + where)
283#define i810_writel(where, mmio, val) writel(val, mmio + where)
284
285#endif /* __I810_H__ */