Cyril Chemparathy | d92c796 | 2010-05-18 12:51:20 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Texas Instruments TNETV107X GPIO Controller |
| 3 | * |
| 4 | * Copyright (C) 2010 Texas Instruments |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation version 2. |
| 9 | * |
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 11 | * kind, whether express or implied; without even the implied warranty |
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/gpio.h> |
Philip Avinash | f1a4c52 | 2013-08-18 10:49:03 +0530 | [diff] [blame] | 18 | #include <linux/platform_data/gpio-davinci.h> |
Cyril Chemparathy | d92c796 | 2010-05-18 12:51:20 -0400 | [diff] [blame] | 19 | |
| 20 | #include <mach/common.h> |
| 21 | #include <mach/tnetv107x.h> |
| 22 | |
| 23 | struct tnetv107x_gpio_regs { |
| 24 | u32 idver; |
| 25 | u32 data_in[3]; |
| 26 | u32 data_out[3]; |
| 27 | u32 direction[3]; |
| 28 | u32 enable[3]; |
| 29 | }; |
| 30 | |
| 31 | #define gpio_reg_index(gpio) ((gpio) >> 5) |
| 32 | #define gpio_reg_bit(gpio) BIT((gpio) & 0x1f) |
| 33 | |
| 34 | #define gpio_reg_rmw(reg, mask, val) \ |
| 35 | __raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg)) |
| 36 | |
| 37 | #define gpio_reg_set_bit(reg, gpio) \ |
| 38 | gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio)) |
| 39 | |
| 40 | #define gpio_reg_clear_bit(reg, gpio) \ |
| 41 | gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0) |
| 42 | |
| 43 | #define gpio_reg_get_bit(reg, gpio) \ |
| 44 | (__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio)) |
| 45 | |
| 46 | #define chip2controller(chip) \ |
| 47 | container_of(chip, struct davinci_gpio_controller, chip) |
| 48 | |
| 49 | #define TNETV107X_GPIO_CTLRS DIV_ROUND_UP(TNETV107X_N_GPIO, 32) |
| 50 | |
| 51 | static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS]; |
| 52 | |
| 53 | static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset) |
| 54 | { |
| 55 | struct davinci_gpio_controller *ctlr = chip2controller(chip); |
| 56 | struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; |
| 57 | unsigned gpio = chip->base + offset; |
| 58 | unsigned long flags; |
| 59 | |
| 60 | spin_lock_irqsave(&ctlr->lock, flags); |
| 61 | |
Hirosh Dabui | c284d9f | 2011-01-25 23:05:26 +0100 | [diff] [blame] | 62 | gpio_reg_set_bit(regs->enable, gpio); |
Cyril Chemparathy | d92c796 | 2010-05-18 12:51:20 -0400 | [diff] [blame] | 63 | |
| 64 | spin_unlock_irqrestore(&ctlr->lock, flags); |
| 65 | |
| 66 | return 0; |
| 67 | } |
| 68 | |
| 69 | static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset) |
| 70 | { |
| 71 | struct davinci_gpio_controller *ctlr = chip2controller(chip); |
| 72 | struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; |
| 73 | unsigned gpio = chip->base + offset; |
| 74 | unsigned long flags; |
| 75 | |
| 76 | spin_lock_irqsave(&ctlr->lock, flags); |
| 77 | |
Hirosh Dabui | c284d9f | 2011-01-25 23:05:26 +0100 | [diff] [blame] | 78 | gpio_reg_clear_bit(regs->enable, gpio); |
Cyril Chemparathy | d92c796 | 2010-05-18 12:51:20 -0400 | [diff] [blame] | 79 | |
| 80 | spin_unlock_irqrestore(&ctlr->lock, flags); |
| 81 | } |
| 82 | |
| 83 | static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset) |
| 84 | { |
| 85 | struct davinci_gpio_controller *ctlr = chip2controller(chip); |
| 86 | struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; |
| 87 | unsigned gpio = chip->base + offset; |
| 88 | unsigned long flags; |
| 89 | |
| 90 | spin_lock_irqsave(&ctlr->lock, flags); |
| 91 | |
Hirosh Dabui | c284d9f | 2011-01-25 23:05:26 +0100 | [diff] [blame] | 92 | gpio_reg_set_bit(regs->direction, gpio); |
Cyril Chemparathy | d92c796 | 2010-05-18 12:51:20 -0400 | [diff] [blame] | 93 | |
| 94 | spin_unlock_irqrestore(&ctlr->lock, flags); |
| 95 | |
| 96 | return 0; |
| 97 | } |
| 98 | |
| 99 | static int tnetv107x_gpio_dir_out(struct gpio_chip *chip, |
| 100 | unsigned offset, int value) |
| 101 | { |
| 102 | struct davinci_gpio_controller *ctlr = chip2controller(chip); |
| 103 | struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; |
| 104 | unsigned gpio = chip->base + offset; |
| 105 | unsigned long flags; |
| 106 | |
| 107 | spin_lock_irqsave(&ctlr->lock, flags); |
| 108 | |
| 109 | if (value) |
Hirosh Dabui | c284d9f | 2011-01-25 23:05:26 +0100 | [diff] [blame] | 110 | gpio_reg_set_bit(regs->data_out, gpio); |
Cyril Chemparathy | d92c796 | 2010-05-18 12:51:20 -0400 | [diff] [blame] | 111 | else |
Hirosh Dabui | c284d9f | 2011-01-25 23:05:26 +0100 | [diff] [blame] | 112 | gpio_reg_clear_bit(regs->data_out, gpio); |
Cyril Chemparathy | d92c796 | 2010-05-18 12:51:20 -0400 | [diff] [blame] | 113 | |
Hirosh Dabui | c284d9f | 2011-01-25 23:05:26 +0100 | [diff] [blame] | 114 | gpio_reg_clear_bit(regs->direction, gpio); |
Cyril Chemparathy | d92c796 | 2010-05-18 12:51:20 -0400 | [diff] [blame] | 115 | |
| 116 | spin_unlock_irqrestore(&ctlr->lock, flags); |
| 117 | |
| 118 | return 0; |
| 119 | } |
| 120 | |
| 121 | static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 122 | { |
| 123 | struct davinci_gpio_controller *ctlr = chip2controller(chip); |
| 124 | struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; |
| 125 | unsigned gpio = chip->base + offset; |
| 126 | int ret; |
| 127 | |
Hirosh Dabui | c284d9f | 2011-01-25 23:05:26 +0100 | [diff] [blame] | 128 | ret = gpio_reg_get_bit(regs->data_in, gpio); |
Cyril Chemparathy | d92c796 | 2010-05-18 12:51:20 -0400 | [diff] [blame] | 129 | |
| 130 | return ret ? 1 : 0; |
| 131 | } |
| 132 | |
| 133 | static void tnetv107x_gpio_set(struct gpio_chip *chip, |
| 134 | unsigned offset, int value) |
| 135 | { |
| 136 | struct davinci_gpio_controller *ctlr = chip2controller(chip); |
| 137 | struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; |
| 138 | unsigned gpio = chip->base + offset; |
| 139 | unsigned long flags; |
| 140 | |
| 141 | spin_lock_irqsave(&ctlr->lock, flags); |
| 142 | |
| 143 | if (value) |
Hirosh Dabui | c284d9f | 2011-01-25 23:05:26 +0100 | [diff] [blame] | 144 | gpio_reg_set_bit(regs->data_out, gpio); |
Cyril Chemparathy | d92c796 | 2010-05-18 12:51:20 -0400 | [diff] [blame] | 145 | else |
Hirosh Dabui | c284d9f | 2011-01-25 23:05:26 +0100 | [diff] [blame] | 146 | gpio_reg_clear_bit(regs->data_out, gpio); |
Cyril Chemparathy | d92c796 | 2010-05-18 12:51:20 -0400 | [diff] [blame] | 147 | |
| 148 | spin_unlock_irqrestore(&ctlr->lock, flags); |
| 149 | } |
| 150 | |
| 151 | static int __init tnetv107x_gpio_setup(void) |
| 152 | { |
| 153 | int i, base; |
| 154 | unsigned ngpio; |
| 155 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
| 156 | struct tnetv107x_gpio_regs *regs; |
| 157 | struct davinci_gpio_controller *ctlr; |
| 158 | |
| 159 | if (soc_info->gpio_type != GPIO_TYPE_TNETV107X) |
| 160 | return 0; |
| 161 | |
| 162 | ngpio = soc_info->gpio_num; |
| 163 | if (ngpio == 0) { |
| 164 | pr_err("GPIO setup: how many GPIOs?\n"); |
| 165 | return -EINVAL; |
| 166 | } |
| 167 | |
| 168 | if (WARN_ON(TNETV107X_N_GPIO < ngpio)) |
| 169 | ngpio = TNETV107X_N_GPIO; |
| 170 | |
| 171 | regs = ioremap(soc_info->gpio_base, SZ_4K); |
| 172 | if (WARN_ON(!regs)) |
| 173 | return -EINVAL; |
| 174 | |
| 175 | for (i = 0, base = 0; base < ngpio; i++, base += 32) { |
| 176 | ctlr = &chips[i]; |
| 177 | |
| 178 | ctlr->chip.label = "tnetv107x"; |
| 179 | ctlr->chip.can_sleep = 0; |
| 180 | ctlr->chip.base = base; |
| 181 | ctlr->chip.ngpio = ngpio - base; |
| 182 | if (ctlr->chip.ngpio > 32) |
| 183 | ctlr->chip.ngpio = 32; |
| 184 | |
| 185 | ctlr->chip.request = tnetv107x_gpio_request; |
| 186 | ctlr->chip.free = tnetv107x_gpio_free; |
| 187 | ctlr->chip.direction_input = tnetv107x_gpio_dir_in; |
| 188 | ctlr->chip.get = tnetv107x_gpio_get; |
| 189 | ctlr->chip.direction_output = tnetv107x_gpio_dir_out; |
| 190 | ctlr->chip.set = tnetv107x_gpio_set; |
| 191 | |
| 192 | spin_lock_init(&ctlr->lock); |
| 193 | |
| 194 | ctlr->regs = regs; |
| 195 | ctlr->set_data = ®s->data_out[i]; |
| 196 | ctlr->clr_data = ®s->data_out[i]; |
| 197 | ctlr->in_data = ®s->data_in[i]; |
| 198 | |
| 199 | gpiochip_add(&ctlr->chip); |
| 200 | } |
| 201 | |
| 202 | soc_info->gpio_ctlrs = chips; |
| 203 | soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32); |
| 204 | return 0; |
| 205 | } |
| 206 | pure_initcall(tnetv107x_gpio_setup); |