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gerrit-public.fairphone.software / kernel / msm-4.19 / 1eee1b3833d67eb52c0f4d293cbb796a776c5eed / . / arch / blackfin / include / asm / cplbinit.h
blob: f315c83a015d5b77827655345d264b3362a1c82b [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]1/*
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]2 * Common CPLB definitions for CPLB init
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]3 *
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]4 * Copyright 2006-2008 Analog Devices Inc.
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]5 *
Robin Getz96f10502009-09-24 14:11:24 +0000[diff] [blame]6 * Licensed under the GPL-2 or later.
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]7 */
8
Mike Frysinger81a487a2007-11-21 15:55:45 +0800[diff] [blame]9#ifndef __ASM_CPLBINIT_H__
10#define __ASM_CPLBINIT_H__
11
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]12#include <asm/blackfin.h>
13#include <asm/cplb.h>
Bernd Schmidtdbdf20d2009-01-07 23:14:38 +0800[diff] [blame]14#include <linux/threads.h>
15
16#ifdef CONFIG_CPLB_SWITCH_TAB_L1
17# define PDT_ATTR __attribute__((l1_data))
18#else
19# define PDT_ATTR
20#endif
21
22struct cplb_entry {
23 unsigned long data, addr;
24};
25
26struct cplb_boundary {
27 unsigned long eaddr; /* End of this region. */
28 unsigned long data; /* CPLB data value. */
29};
30
31extern struct cplb_boundary dcplb_bounds[];
32extern struct cplb_boundary icplb_bounds[];
33extern int dcplb_nr_bounds, icplb_nr_bounds;
34
35extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
36extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
37extern int first_switched_icplb;
38extern int first_switched_dcplb;
39
40extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];
41extern int nr_dcplb_prot[], nr_cplb_flush[];
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]42
Bernd Schmidtb97b8a92008-01-27 18:39:16 +0800[diff] [blame]43#ifdef CONFIG_MPU
44
Bernd Schmidtdbdf20d2009-01-07 23:14:38 +0800[diff] [blame]45extern int first_mask_dcplb;
Bernd Schmidtb97b8a92008-01-27 18:39:16 +0800[diff] [blame]46
Bernd Schmidtdbdf20d2009-01-07 23:14:38 +0800[diff] [blame]47extern int page_mask_order;
48extern int page_mask_nelts;
Bernd Schmidtb97b8a92008-01-27 18:39:16 +0800[diff] [blame]49
Bernd Schmidtdbdf20d2009-01-07 23:14:38 +0800[diff] [blame]50extern unsigned long *current_rwx_mask[NR_CPUS];
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]51
Bernd Schmidtdbdf20d2009-01-07 23:14:38 +0800[diff] [blame]52extern void flush_switched_cplbs(unsigned int);
53extern void set_mask_dcplbs(unsigned long *, unsigned int);
Graf Yangb8a98982008-11-18 17:48:22 +0800[diff] [blame]54
Bernd Schmidtdbdf20d2009-01-07 23:14:38 +0800[diff] [blame]55extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]56
Bernd Schmidtb97b8a92008-01-27 18:39:16 +0800[diff] [blame]57#endif /* CONFIG_MPU */
58
Bernd Schmidtdbdf20d2009-01-07 23:14:38 +0800[diff] [blame]59extern void bfin_icache_init(struct cplb_entry *icplb_tbl);
60extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);
61
Graf Yangb8a98982008-11-18 17:48:22 +0800[diff] [blame]62#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
Bernd Schmidtdbdf20d2009-01-07 23:14:38 +0800[diff] [blame]63extern void generate_cplb_tables_all(void);
Graf Yangb8a98982008-11-18 17:48:22 +0800[diff] [blame]64extern void generate_cplb_tables_cpu(unsigned int cpu);
65#endif
Mike Frysinger81a487a2007-11-21 15:55:45 +0800[diff] [blame]66#endif