blob: 21fefd4cdc2535a2ce5857c4e3523063c0196808 [file] [log] [blame]
Hauke Mehrtensd27509f2014-02-04 00:01:45 +01001/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
5 *
6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
Rafał Miłeckifb026d32014-10-01 15:45:28 +020011#include <dt-bindings/gpio/gpio.h>
Rafał Miłeckif6f82342014-11-30 18:28:29 +010012#include <dt-bindings/input/input.h>
Hauke Mehrtensd27509f2014-02-04 00:01:45 +010013#include <dt-bindings/interrupt-controller/irq.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include "skeleton.dtsi"
16
17/ {
18 interrupt-parent = <&gic>;
19
20 chipcommonA {
21 compatible = "simple-bus";
22 ranges = <0x00000000 0x18000000 0x00001000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
25
26 uart0: serial@0300 {
27 compatible = "ns16550";
28 reg = <0x0300 0x100>;
29 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
30 clock-frequency = <100000000>;
31 status = "disabled";
32 };
33
34 uart1: serial@0400 {
35 compatible = "ns16550";
36 reg = <0x0400 0x100>;
37 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
38 clock-frequency = <100000000>;
39 status = "disabled";
40 };
41 };
42
43 mpcore {
44 compatible = "simple-bus";
45 ranges = <0x00000000 0x19020000 0x00003000>;
46 #address-cells = <1>;
47 #size-cells = <1>;
48
49 scu@0000 {
50 compatible = "arm,cortex-a9-scu";
51 reg = <0x0000 0x100>;
52 };
53
54 timer@0200 {
55 compatible = "arm,cortex-a9-global-timer";
56 reg = <0x0200 0x100>;
57 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&clk_periph>;
59 };
60
61 local-timer@0600 {
62 compatible = "arm,cortex-a9-twd-timer";
63 reg = <0x0600 0x100>;
64 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
65 clocks = <&clk_periph>;
66 };
67
68 gic: interrupt-controller@1000 {
69 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>;
71 #address-cells = <0>;
72 interrupt-controller;
73 reg = <0x1000 0x1000>,
74 <0x0100 0x100>;
75 };
76
77 L2: cache-controller@2000 {
78 compatible = "arm,pl310-cache";
79 reg = <0x2000 0x1000>;
80 cache-unified;
81 cache-level = <2>;
82 };
83 };
84
85 clocks {
86 #address-cells = <1>;
87 #size-cells = <0>;
88
89 /* As long as we do not have a real clock driver us this
90 * fixed clock */
91 clk_periph: periph {
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <400000000>;
95 };
96 };
Rafał Miłeckifb026d32014-10-01 15:45:28 +020097
98 axi@18000000 {
99 compatible = "brcm,bus-axi";
100 reg = <0x18000000 0x1000>;
101 ranges = <0x00000000 0x18000000 0x00100000>;
102 #address-cells = <1>;
103 #size-cells = <1>;
104
Hauke Mehrtensdec37882014-09-24 23:50:07 +0200105 #interrupt-cells = <1>;
106 interrupt-map-mask = <0x000fffff 0xffff>;
107 interrupt-map =
108 /* ChipCommon */
109 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
110
Hauke Mehrtens1f80de62015-05-24 21:08:14 +0200111 /* PCIe Controller 0 */
112 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
113 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
114 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
115 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
116 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
117 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
118
119 /* PCIe Controller 1 */
120 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
121 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
122 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
123 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
124 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
125 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
126
127 /* PCIe Controller 2 */
128 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
129 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
130 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
131 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
132 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
133 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
134
Hauke Mehrtensdec37882014-09-24 23:50:07 +0200135 /* USB 2.0 Controller */
136 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
137
138 /* USB 3.0 Controller */
139 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
140
141 /* Ethernet Controller 0 */
142 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
143
144 /* Ethernet Controller 1 */
145 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
146
147 /* Ethernet Controller 2 */
148 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
149
150 /* Ethernet Controller 3 */
151 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
152
153 /* NAND Controller */
154 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
155 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
156 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
157 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
158 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
159 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
160 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
161 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
162
Rafał Miłeckifb026d32014-10-01 15:45:28 +0200163 chipcommon: chipcommon@0 {
164 reg = <0x00000000 0x1000>;
165
166 gpio-controller;
167 #gpio-cells = <2>;
168 };
169 };
Hauke Mehrtens9faa5962015-05-29 23:39:47 +0200170
171 nand: nand@18028000 {
172 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
173 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
174 reg-names = "nand", "iproc-idm", "iproc-ext";
175 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
176
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 brcm,nand-has-wp;
181 };
Hauke Mehrtensd27509f2014-02-04 00:01:45 +0100182};