| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | if (BF537 || BF534 || BF536) |
| 2 | |
| Mike Frysinger | 4f25eb8 | 2007-11-15 20:49:44 +0800 | [diff] [blame] | 3 | source "arch/blackfin/mach-bf537/boards/Kconfig" |
| 4 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 5 | menu "BF537 Specific Configuration" |
| 6 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 7 | comment "Interrupt Priority Assignment" |
| 8 | menu "Priority" |
| 9 | |
| 10 | config IRQ_PLL_WAKEUP |
| 11 | int "IRQ_PLL_WAKEUP" |
| 12 | default 7 |
| 13 | config IRQ_DMA_ERROR |
| 14 | int "IRQ_DMA_ERROR Generic" |
| 15 | default 7 |
| 16 | config IRQ_ERROR |
| 17 | int "IRQ_ERROR: CAN MAC SPORT0 SPORT1 SPI UART0 UART1" |
| 18 | default 7 |
| 19 | config IRQ_RTC |
| 20 | int "IRQ_RTC" |
| 21 | default 8 |
| 22 | config IRQ_PPI |
| 23 | int "IRQ_PPI" |
| 24 | default 8 |
| 25 | config IRQ_SPORT0_RX |
| 26 | int "IRQ_SPORT0_RX" |
| 27 | default 9 |
| 28 | config IRQ_SPORT0_TX |
| 29 | int "IRQ_SPORT0_TX" |
| 30 | default 9 |
| 31 | config IRQ_SPORT1_RX |
| 32 | int "IRQ_SPORT1_RX" |
| 33 | default 9 |
| 34 | config IRQ_SPORT1_TX |
| 35 | int "IRQ_SPORT1_TX" |
| 36 | default 9 |
| 37 | config IRQ_TWI |
| 38 | int "IRQ_TWI" |
| 39 | default 10 |
| 40 | config IRQ_SPI |
| 41 | int "IRQ_SPI" |
| 42 | default 10 |
| 43 | config IRQ_UART0_RX |
| 44 | int "IRQ_UART0_RX" |
| 45 | default 10 |
| 46 | config IRQ_UART0_TX |
| 47 | int "IRQ_UART0_TX" |
| 48 | default 10 |
| 49 | config IRQ_UART1_RX |
| 50 | int "IRQ_UART1_RX" |
| 51 | default 10 |
| 52 | config IRQ_UART1_TX |
| 53 | int "IRQ_UART1_TX" |
| 54 | default 10 |
| 55 | config IRQ_CAN_RX |
| 56 | int "IRQ_CAN_RX" |
| 57 | default 11 |
| 58 | config IRQ_CAN_TX |
| 59 | int "IRQ_CAN_TX" |
| 60 | default 11 |
| 61 | config IRQ_MAC_RX |
| 62 | int "IRQ_MAC_RX" |
| 63 | default 11 |
| 64 | config IRQ_MAC_TX |
| 65 | int "IRQ_MAC_TX" |
| 66 | default 11 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 67 | config IRQ_TIMER0 |
| 68 | int "IRQ_TIMER0" |
| Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame^] | 69 | default 7 if TICKSOURCE_GPTMR0 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 70 | default 8 |
| 71 | config IRQ_TIMER1 |
| 72 | int "IRQ_TIMER1" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 73 | default 12 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 74 | config IRQ_TIMER2 |
| 75 | int "IRQ_TIMER2" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 76 | default 12 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 77 | config IRQ_TIMER3 |
| 78 | int "IRQ_TIMER3" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 79 | default 12 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 80 | config IRQ_TIMER4 |
| 81 | int "IRQ_TIMER4" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 82 | default 12 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 83 | config IRQ_TIMER5 |
| 84 | int "IRQ_TIMER5" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 85 | default 12 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 86 | config IRQ_TIMER6 |
| 87 | int "IRQ_TIMER6" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 88 | default 12 |
| Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 89 | config IRQ_TIMER7 |
| 90 | int "IRQ_TIMER7" |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 91 | default 12 |
| 92 | config IRQ_PROG_INTA |
| 93 | int "IRQ_PROG_INTA" |
| 94 | default 12 |
| 95 | config IRQ_PORTG_INTB |
| 96 | int "IRQ_PORTG_INTB" |
| 97 | default 12 |
| 98 | config IRQ_MEM_DMA0 |
| 99 | int "IRQ_MEM_DMA0" |
| 100 | default 13 |
| 101 | config IRQ_MEM_DMA1 |
| 102 | int "IRQ_MEM_DMA1" |
| 103 | default 13 |
| 104 | config IRQ_WATCH |
| 105 | int "IRQ_WATCH" |
| 106 | default 13 |
| 107 | |
| 108 | help |
| 109 | Enter the priority numbers between 7-13 ONLY. Others are Reserved. |
| 110 | This applies to all the above. It is not recommended to assign the |
| 111 | highest priority number 7 to UART or any other device. |
| 112 | |
| 113 | endmenu |
| 114 | |
| 115 | endmenu |
| 116 | |
| 117 | endif |