| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * This file contains the register definitions for the Excalibur |
| 4 | * Timer TIMER00. |
| 5 | * |
| 6 | * Copyright (C) 2001 Altera Corporation |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #ifndef __INT_CTRL00_H |
| 24 | #define __INT_CTRL00_H |
| 25 | |
| 26 | #define INT_MS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x00 )) |
| 27 | #define INT_MS_FC_MSK (0x10000) |
| 28 | #define INT_MS_FC_OFST (16) |
| 29 | #define INT_MS_M1_MSK (0x8000) |
| 30 | #define INT_MS_M1_OFST (15) |
| 31 | #define INT_MS_M0_MSK (0x4000) |
| 32 | #define INT_MS_M0_OFST (14) |
| 33 | #define INT_MS_AE_MSK (0x2000) |
| 34 | #define INT_MS_AE_OFST (13) |
| 35 | #define INT_MS_PE_MSK (0x1000) |
| 36 | #define INT_MS_PE_OFST (12) |
| 37 | #define INT_MS_EE_MSK (0x0800) |
| 38 | #define INT_MS_EE_OFST (11) |
| 39 | #define INT_MS_PS_MSK (0x0400) |
| 40 | #define INT_MS_PS_OFST (10) |
| 41 | #define INT_MS_T1_MSK (0x0200) |
| 42 | #define INT_MS_T1_OFST (9) |
| 43 | #define INT_MS_T0_MSK (0x0100) |
| 44 | #define INT_MS_T0_OFST (8) |
| 45 | #define INT_MS_UA_MSK (0x0080) |
| 46 | #define INT_MS_UA_OFST (7) |
| 47 | #define INT_MS_IP_MSK (0x0040) |
| 48 | #define INT_MS_IP_OFST (6) |
| 49 | #define INT_MS_P5_MSK (0x0020) |
| 50 | #define INT_MS_P5_OFST (5) |
| 51 | #define INT_MS_P4_MSK (0x0010) |
| 52 | #define INT_MS_P4_OFST (4) |
| 53 | #define INT_MS_P3_MSK (0x0008) |
| 54 | #define INT_MS_P3_OFST (3) |
| 55 | #define INT_MS_P2_MSK (0x0004) |
| 56 | #define INT_MS_P2_OFST (2) |
| 57 | #define INT_MS_P1_MSK (0x0002) |
| 58 | #define INT_MS_P1_OFST (1) |
| 59 | #define INT_MS_P0_MSK (0x0001) |
| 60 | #define INT_MS_P0_OFST (0) |
| 61 | |
| 62 | #define INT_MC(base_addr) (INT_CTRL00_TYPE (base_addr + 0x04 )) |
| 63 | #define INT_MC_FC_MSK (0x10000) |
| 64 | #define INT_MC_FC_OFST (16) |
| 65 | #define INT_MC_M1_MSK (0x8000) |
| 66 | #define INT_MC_M1_OFST (15) |
| 67 | #define INT_MC_M0_MSK (0x4000) |
| 68 | #define INT_MC_M0_OFST (14) |
| 69 | #define INT_MC_AE_MSK (0x2000) |
| 70 | #define INT_MC_AE_OFST (13) |
| 71 | #define INT_MC_PE_MSK (0x1000) |
| 72 | #define INT_MC_PE_OFST (12) |
| 73 | #define INT_MC_EE_MSK (0x0800) |
| 74 | #define INT_MC_EE_OFST (11) |
| 75 | #define INT_MC_PS_MSK (0x0400) |
| 76 | #define INT_MC_PS_OFST (10) |
| 77 | #define INT_MC_T1_MSK (0x0200) |
| 78 | #define INT_MC_T1_OFST (9) |
| 79 | #define INT_MC_T0_MSK (0x0100) |
| 80 | #define INT_MC_T0_OFST (8) |
| 81 | #define INT_MC_UA_MSK (0x0080) |
| 82 | #define INT_MC_UA_OFST (7) |
| 83 | #define INT_MC_IP_MSK (0x0040) |
| 84 | #define INT_MC_IP_OFST (6) |
| 85 | #define INT_MC_P5_MSK (0x0020) |
| 86 | #define INT_MC_P5_OFST (5) |
| 87 | #define INT_MC_P4_MSK (0x0010) |
| 88 | #define INT_MC_P4_OFST (4) |
| 89 | #define INT_MC_P3_MSK (0x0008) |
| 90 | #define INT_MC_P3_OFST (3) |
| 91 | #define INT_MC_P2_MSK (0x0004) |
| 92 | #define INT_MC_P2_OFST (2) |
| 93 | #define INT_MC_P1_MSK (0x0002) |
| 94 | #define INT_MC_P1_OFST (1) |
| 95 | #define INT_MC_P0_MSK (0x0001) |
| 96 | #define INT_MC_P0_OFST (0) |
| 97 | |
| 98 | #define INT_SS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x08 )) |
| 99 | #define INT_SS_FC_SSK (0x8000) |
| 100 | #define INT_SS_FC_OFST (15) |
| 101 | #define INT_SS_M1_SSK (0x8000) |
| 102 | #define INT_SS_M1_OFST (15) |
| 103 | #define INT_SS_M0_SSK (0x4000) |
| 104 | #define INT_SS_M0_OFST (14) |
| 105 | #define INT_SS_AE_SSK (0x2000) |
| 106 | #define INT_SS_AE_OFST (13) |
| 107 | #define INT_SS_PE_SSK (0x1000) |
| 108 | #define INT_SS_PE_OFST (12) |
| 109 | #define INT_SS_EE_SSK (0x0800) |
| 110 | #define INT_SS_EE_OFST (11) |
| 111 | #define INT_SS_PS_SSK (0x0400) |
| 112 | #define INT_SS_PS_OFST (10) |
| 113 | #define INT_SS_T1_SSK (0x0200) |
| 114 | #define INT_SS_T1_OFST (9) |
| 115 | #define INT_SS_T0_SSK (0x0100) |
| 116 | #define INT_SS_T0_OFST (8) |
| 117 | #define INT_SS_UA_SSK (0x0080) |
| 118 | #define INT_SS_UA_OFST (7) |
| 119 | #define INT_SS_IP_SSK (0x0040) |
| 120 | #define INT_SS_IP_OFST (6) |
| 121 | #define INT_SS_P5_SSK (0x0020) |
| 122 | #define INT_SS_P5_OFST (5) |
| 123 | #define INT_SS_P4_SSK (0x0010) |
| 124 | #define INT_SS_P4_OFST (4) |
| 125 | #define INT_SS_P3_SSK (0x0008) |
| 126 | #define INT_SS_P3_OFST (3) |
| 127 | #define INT_SS_P2_SSK (0x0004) |
| 128 | #define INT_SS_P2_OFST (2) |
| 129 | #define INT_SS_P1_SSK (0x0002) |
| 130 | #define INT_SS_P1_OFST (1) |
| 131 | #define INT_SS_P0_SSK (0x0001) |
| 132 | #define INT_SS_P0_OFST (0) |
| 133 | |
| 134 | #define INT_RS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x0C )) |
| 135 | #define INT_RS_FC_RSK (0x10000) |
| 136 | #define INT_RS_FC_OFST (16) |
| 137 | #define INT_RS_M1_RSK (0x8000) |
| 138 | #define INT_RS_M1_OFST (15) |
| 139 | #define INT_RS_M0_RSK (0x4000) |
| 140 | #define INT_RS_M0_OFST (14) |
| 141 | #define INT_RS_AE_RSK (0x2000) |
| 142 | #define INT_RS_AE_OFST (13) |
| 143 | #define INT_RS_PE_RSK (0x1000) |
| 144 | #define INT_RS_PE_OFST (12) |
| 145 | #define INT_RS_EE_RSK (0x0800) |
| 146 | #define INT_RS_EE_OFST (11) |
| 147 | #define INT_RS_PS_RSK (0x0400) |
| 148 | #define INT_RS_PS_OFST (10) |
| 149 | #define INT_RS_T1_RSK (0x0200) |
| 150 | #define INT_RS_T1_OFST (9) |
| 151 | #define INT_RS_T0_RSK (0x0100) |
| 152 | #define INT_RS_T0_OFST (8) |
| 153 | #define INT_RS_UA_RSK (0x0080) |
| 154 | #define INT_RS_UA_OFST (7) |
| 155 | #define INT_RS_IP_RSK (0x0040) |
| 156 | #define INT_RS_IP_OFST (6) |
| 157 | #define INT_RS_P5_RSK (0x0020) |
| 158 | #define INT_RS_P5_OFST (5) |
| 159 | #define INT_RS_P4_RSK (0x0010) |
| 160 | #define INT_RS_P4_OFST (4) |
| 161 | #define INT_RS_P3_RSK (0x0008) |
| 162 | #define INT_RS_P3_OFST (3) |
| 163 | #define INT_RS_P2_RSK (0x0004) |
| 164 | #define INT_RS_P2_OFST (2) |
| 165 | #define INT_RS_P1_RSK (0x0002) |
| 166 | #define INT_RS_P1_OFST (1) |
| 167 | #define INT_RS_P0_RSK (0x0001) |
| 168 | #define INT_RS_P0_OFST (0) |
| 169 | |
| 170 | #define INT_ID(base_addr) (INT_CTRL00_TYPE (base_addr + 0x10 )) |
| 171 | #define INT_ID_ID_MSK (0x3F) |
| 172 | #define INT_ID_ID_OFST (0) |
| 173 | |
| 174 | #define INT_PLD_PRIORITY(base_addr) (INT_CTRL00_TYPE (base_addr + 0x14 )) |
| 175 | #define INT_PLD_PRIORITY_PRI_MSK (0x3F) |
| 176 | #define INT_PLD_PRIORITY_PRI_OFST (0) |
| 177 | #define INT_PLD_PRIORITY_GA_MSK (0x40) |
| 178 | #define INT_PLD_PRIORITY_GA_OFST (6) |
| 179 | |
| 180 | #define INT_MODE(base_addr) (INT_CTRL00_TYPE (base_addr + 0x18 )) |
| 181 | #define INT_MODE_MODE_MSK (0x3) |
| 182 | #define INT_MODE_MODE_OFST (0) |
| 183 | |
| 184 | #define INT_PRIORITY_P0(base_addr) (INT_CTRL00_TYPE (base_addr + 0x80 )) |
| 185 | #define INT_PRIORITY_P0_PRI_MSK (0x3F) |
| 186 | #define INT_PRIORITY_P0_PRI_OFST (0) |
| 187 | #define INT_PRIORITY_P0_FQ_MSK (0x40) |
| 188 | #define INT_PRIORITY_P0_FQ_OFST (6) |
| 189 | |
| 190 | #define INT_PRIORITY_P1(base_addr) (INT_CTRL00_TYPE (base_addr + 0x84 )) |
| 191 | #define INT_PRIORITY_P1_PRI_MSK (0x3F) |
| 192 | #define INT_PRIORITY_P1_PRI_OFST (0) |
| 193 | #define INT_PRIORITY_P1_FQ_MSK (0x40) |
| 194 | #define INT_PRIORITY_P1_FQ_OFST (6) |
| 195 | |
| 196 | #define INT_PRIORITY_P2(base_addr) (INT_CTRL00_TYPE (base_addr + 0x88 )) |
| 197 | #define INT_PRIORITY_P2_PRI_MSK (0x3F) |
| 198 | #define INT_PRIORITY_P2_PRI_OFST (0) |
| 199 | #define INT_PRIORITY_P2_FQ_MSK (0x40) |
| 200 | #define INT_PRIORITY_P2_FQ_OFST (6) |
| 201 | |
| 202 | #define INT_PRIORITY_P3(base_addr) (INT_CTRL00_TYPE (base_addr + 0x8C )) |
| 203 | #define INT_PRIORITY_P3_PRI_MSK (0x3F) |
| 204 | #define INT_PRIORITY_P3_PRI_OFST (0) |
| 205 | #define INT_PRIORITY_P3_FQ_MSK (0x40) |
| 206 | #define INT_PRIORITY_P3_FQ_OFST (6) |
| 207 | |
| 208 | #define INT_PRIORITY_P4(base_addr) (INT_CTRL00_TYPE (base_addr + 0x90 )) |
| 209 | #define INT_PRIORITY_P4_PRI_MSK (0x3F) |
| 210 | #define INT_PRIORITY_P4_PRI_OFST (0) |
| 211 | #define INT_PRIORITY_P4_FQ_MSK (0x40) |
| 212 | #define INT_PRIORITY_P4_FQ_OFST (6) |
| 213 | |
| 214 | #define INT_PRIORITY_P5(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 )) |
| 215 | #define INT_PRIORITY_P5_PRI_MSK (0x3F) |
| 216 | #define INT_PRIORITY_P5_PRI_OFST (0) |
| 217 | #define INT_PRIORITY_P5_FQ_MSK (0x40) |
| 218 | #define INT_PRIORITY_P5_FQ_OFST (6) |
| 219 | |
| 220 | #define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 )) |
| 221 | #define INT_PRIORITY_IP_PRI_MSK (0x3F) |
| 222 | #define INT_PRIORITY_IP_PRI_OFST (0) |
| 223 | #define INT_PRIORITY_IP_FQ_MSK (0x40) |
| 224 | #define INT_PRIORITY_IP_FQ_OFST (6) |
| 225 | |
| 226 | #define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr + 0x9C )) |
| 227 | #define INT_PRIORITY_UA_PRI_MSK (0x3F) |
| 228 | #define INT_PRIORITY_UA_PRI_OFST (0) |
| 229 | #define INT_PRIORITY_UA_FQ_MSK (0x40) |
| 230 | #define INT_PRIORITY_UA_FQ_OFST (6) |
| 231 | |
| 232 | #define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA0 )) |
| 233 | #define INT_PRIORITY_T0_PRI_MSK (0x3F) |
| 234 | #define INT_PRIORITY_T0_PRI_OFST (0) |
| 235 | #define INT_PRIORITY_T0_FQ_MSK (0x40) |
| 236 | #define INT_PRIORITY_T0_FQ_OFST (6) |
| 237 | |
| 238 | #define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA4 )) |
| 239 | #define INT_PRIORITY_T1_PRI_MSK (0x3F) |
| 240 | #define INT_PRIORITY_T1_PRI_OFST (0) |
| 241 | #define INT_PRIORITY_T1_FQ_MSK (0x40) |
| 242 | #define INT_PRIORITY_T1_FQ_OFST (6) |
| 243 | |
| 244 | #define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA8 )) |
| 245 | #define INT_PRIORITY_PS_PRI_MSK (0x3F) |
| 246 | #define INT_PRIORITY_PS_PRI_OFST (0) |
| 247 | #define INT_PRIORITY_PS_FQ_MSK (0x40) |
| 248 | #define INT_PRIORITY_PS_FQ_OFST (6) |
| 249 | |
| 250 | #define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xAC )) |
| 251 | #define INT_PRIORITY_EE_PRI_MSK (0x3F) |
| 252 | #define INT_PRIORITY_EE_PRI_OFST (0) |
| 253 | #define INT_PRIORITY_EE_FQ_MSK (0x40) |
| 254 | #define INT_PRIORITY_EE_FQ_OFST (6) |
| 255 | |
| 256 | #define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB0 )) |
| 257 | #define INT_PRIORITY_PE_PRI_MSK (0x3F) |
| 258 | #define INT_PRIORITY_PE_PRI_OFST (0) |
| 259 | #define INT_PRIORITY_PE_FQ_MSK (0x40) |
| 260 | #define INT_PRIORITY_PE_FQ_OFST (6) |
| 261 | |
| 262 | #define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB4 )) |
| 263 | #define INT_PRIORITY_AE_PRI_MSK (0x3F) |
| 264 | #define INT_PRIORITY_AE_PRI_OFST (0) |
| 265 | #define INT_PRIORITY_AE_FQ_MSK (0x40) |
| 266 | #define INT_PRIORITY_AE_FQ_OFST (6) |
| 267 | |
| 268 | #define INT_PRIORITY_M0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB8 )) |
| 269 | #define INT_PRIORITY_M0_PRI_MSK (0x3F) |
| 270 | #define INT_PRIORITY_M0_PRI_OFST (0) |
| 271 | #define INT_PRIORITY_M0_FQ_MSK (0x40) |
| 272 | #define INT_PRIORITY_M0_FQ_OFST (6) |
| 273 | |
| 274 | #define INT_PRIORITY_M1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xBC )) |
| 275 | #define INT_PRIORITY_M1_PRI_MSK (0x3F) |
| 276 | #define INT_PRIORITY_M1_PRI_OFST (0) |
| 277 | #define INT_PRIORITY_M1_FQ_MSK (0x40) |
| 278 | #define INT_PRIORITY_M1_FQ_OFST (6) |
| 279 | |
| 280 | #define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr + 0xC0 )) |
| 281 | #define INT_PRIORITY_FC_PRI_MSK (0x3F) |
| 282 | #define INT_PRIORITY_FC_PRI_OFST (0) |
| 283 | #define INT_PRIORITY_FC_FQ_MSK (0x40) |
| 284 | #define INT_PRIORITY_FC_FQ_OFST (6) |
| 285 | |
| 286 | #endif /* __INT_CTRL00_H */ |
| 287 | |
| 288 | |