| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __ASM_SH_HITACHI_SE_H |
| 2 | #define __ASM_SH_HITACHI_SE_H |
| 3 | |
| 4 | /* |
| 5 | * linux/include/asm-sh/hitachi_se.h |
| 6 | * |
| 7 | * Copyright (C) 2000 Kazumoto Kojima |
| 8 | * |
| 9 | * Hitachi SolutionEngine support |
| 10 | */ |
| 11 | |
| 12 | /* Box specific addresses. */ |
| 13 | |
| 14 | #define PA_ROM 0x00000000 /* EPROM */ |
| 15 | #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ |
| 16 | #define PA_FROM 0x01000000 /* EPROM */ |
| 17 | #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ |
| 18 | #define PA_EXT1 0x04000000 |
| 19 | #define PA_EXT1_SIZE 0x04000000 |
| 20 | #define PA_EXT2 0x08000000 |
| 21 | #define PA_EXT2_SIZE 0x04000000 |
| 22 | #define PA_SDRAM 0x0c000000 |
| 23 | #define PA_SDRAM_SIZE 0x04000000 |
| 24 | |
| 25 | #define PA_EXT4 0x12000000 |
| 26 | #define PA_EXT4_SIZE 0x02000000 |
| 27 | #define PA_EXT5 0x14000000 |
| 28 | #define PA_EXT5_SIZE 0x04000000 |
| 29 | #define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ |
| 30 | |
| 31 | #define PA_83902 0xb0000000 /* DP83902A */ |
| 32 | #define PA_83902_IF 0xb0040000 /* DP83902A remote io port */ |
| 33 | #define PA_83902_RST 0xb0080000 /* DP83902A reset port */ |
| 34 | |
| 35 | #define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */ |
| 36 | #define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */ |
| 37 | #define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */ |
| 38 | #define PA_LED 0xb0c00000 /* LED */ |
| 39 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) |
| 40 | #define PA_BCR 0xb0e00000 |
| 41 | #else |
| 42 | #define PA_BCR 0xb1400000 /* FPGA */ |
| 43 | #endif |
| 44 | |
| 45 | #define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ |
| 46 | #define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ |
| 47 | #define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ |
| 48 | #define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ |
| 49 | #define MRSHPC_OPTION (PA_MRSHPC + 6) |
| 50 | #define MRSHPC_CSR (PA_MRSHPC + 8) |
| 51 | #define MRSHPC_ISR (PA_MRSHPC + 10) |
| 52 | #define MRSHPC_ICR (PA_MRSHPC + 12) |
| 53 | #define MRSHPC_CPWCR (PA_MRSHPC + 14) |
| 54 | #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) |
| 55 | #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) |
| 56 | #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) |
| 57 | #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) |
| 58 | #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) |
| 59 | #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) |
| 60 | #define MRSHPC_CDCR (PA_MRSHPC + 28) |
| 61 | #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) |
| 62 | |
| 63 | #define BCR_ILCRA (PA_BCR + 0) |
| 64 | #define BCR_ILCRB (PA_BCR + 2) |
| 65 | #define BCR_ILCRC (PA_BCR + 4) |
| 66 | #define BCR_ILCRD (PA_BCR + 6) |
| 67 | #define BCR_ILCRE (PA_BCR + 8) |
| 68 | #define BCR_ILCRF (PA_BCR + 10) |
| 69 | #define BCR_ILCRG (PA_BCR + 12) |
| 70 | |
| 71 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) |
| 72 | #define IRQ_STNIC 12 |
| 73 | #else |
| 74 | #define IRQ_STNIC 10 |
| 75 | #endif |
| 76 | |
| 77 | #endif /* __ASM_SH_HITACHI_SE_H */ |