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Linus Torvalds1da177e2005-04-16 15:20:36 -07001Accessing PCI device resources through sysfs
Jesse Barnes5d135dff2005-12-09 11:55:03 -08002--------------------------------------------
Linus Torvalds1da177e2005-04-16 15:20:36 -07003
4sysfs, usually mounted at /sys, provides access to PCI resources on platforms
5that support it. For example, a given bus might look like this:
6
7 /sys/devices/pci0000:17
8 |-- 0000:17:00.0
9 | |-- class
10 | |-- config
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 | |-- device
Timothy S. Nelson97c44832009-01-30 06:12:47 +110012 | |-- enable
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 | |-- irq
14 | |-- local_cpus
Alex Chiang77c27c72009-03-20 14:56:36 -060015 | |-- remove
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 | |-- resource
17 | |-- resource0
18 | |-- resource1
19 | |-- resource2
Emil Velikov702ed3b2016-11-21 16:24:49 -060020 | |-- revision
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 | |-- rom
22 | |-- subsystem_device
23 | |-- subsystem_vendor
24 | `-- vendor
David Brownell0b405a02005-05-12 12:06:27 -070025 `-- ...
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
27The topmost element describes the PCI domain and bus number. In this case,
28the domain number is 0000 and the bus number is 17 (both values are in hex).
29This bus contains a single function device in slot 0. The domain and bus
30numbers are reproduced for convenience. Under the device directory are several
31files, each with their own function.
32
33 file function
34 ---- --------
35 class PCI class (ascii, ro)
36 config PCI config space (binary, rw)
Linus Torvalds1da177e2005-04-16 15:20:36 -070037 device PCI device (ascii, ro)
Timothy S. Nelson97c44832009-01-30 06:12:47 +110038 enable Whether the device is enabled (ascii, rw)
Linus Torvalds1da177e2005-04-16 15:20:36 -070039 irq IRQ number (ascii, ro)
40 local_cpus nearby CPU mask (cpumask, ro)
Alex Chiang77c27c72009-03-20 14:56:36 -060041 remove remove device from kernel's list (ascii, wo)
Linus Torvalds1da177e2005-04-16 15:20:36 -070042 resource PCI resource host addresses (ascii, ro)
Alex Williamson86333282010-07-19 09:45:34 -060043 resource0..N PCI resource N, if present (binary, mmap, rw[1])
venkatesh.pallipadi@intel.com45aec1ae2008-03-18 17:00:22 -070044 resource0_wc..N_wc PCI WC map resource N, if prefetchable (binary, mmap)
Emil Velikov702ed3b2016-11-21 16:24:49 -060045 revision PCI revision (ascii, ro)
Linus Torvalds1da177e2005-04-16 15:20:36 -070046 rom PCI ROM resource, if present (binary, ro)
47 subsystem_device PCI subsystem device (ascii, ro)
48 subsystem_vendor PCI subsystem vendor (ascii, ro)
49 vendor PCI vendor (ascii, ro)
50
51 ro - read only file
52 rw - file is readable and writable
Alex Chiang77c27c72009-03-20 14:56:36 -060053 wo - write only file
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 mmap - file is mmapable
55 ascii - file contains ascii text
56 binary - file contains binary data
57 cpumask - file contains a cpumask type
58
Alex Williamson86333282010-07-19 09:45:34 -060059[1] rw for RESOURCE_IO (I/O port) regions only
60
Jesse Barnes5d135dff2005-12-09 11:55:03 -080061The read only files are informational, writes to them will be ignored, with
62the exception of the 'rom' file. Writable files can be used to perform
63actions on the device (e.g. changing config space, detaching a device).
64mmapable files are available via an mmap of the file at offset 0 and can be
65used to do actual device programming from userspace. Note that some platforms
66don't support mmapping of certain resources, so be sure to check the return
Alex Williamson86333282010-07-19 09:45:34 -060067value from any attempted mmap. The most notable of these are I/O port
68resources, which also provide read/write access.
Jesse Barnes5d135dff2005-12-09 11:55:03 -080069
Timothy S. Nelson97c44832009-01-30 06:12:47 +110070The 'enable' file provides a counter that indicates how many times the device
71has been enabled. If the 'enable' file currently returns '4', and a '1' is
72echoed into it, it will then return '5'. Echoing a '0' into it will decrease
73the count. Even when it returns to 0, though, some of the initialisation
74may not be reversed.
75
Jesse Barnes5d135dff2005-12-09 11:55:03 -080076The 'rom' file is special in that it provides read-only access to the device's
77ROM file, if available. It's disabled by default, however, so applications
78should write the string "1" to the file to enable it before attempting a read
Timothy S. Nelson97c44832009-01-30 06:12:47 +110079call, and disable it following the access by writing "0" to the file. Note
Matt LaPlante19f59462009-04-27 15:06:31 +020080that the device must be enabled for a rom read to return data successfully.
Timothy S. Nelson97c44832009-01-30 06:12:47 +110081In the event a driver is not bound to the device, it can be enabled using the
82'enable' file, documented above.
Linus Torvalds1da177e2005-04-16 15:20:36 -070083
Alex Chiang77c27c72009-03-20 14:56:36 -060084The 'remove' file is used to remove the PCI device, by writing a non-zero
85integer to the file. This does not involve any kind of hot-plug functionality,
86e.g. powering off the device. The device is removed from the kernel's list of
87PCI devices, the sysfs directory for it is removed, and the device will be
88removed from any drivers attached to it. Removal of PCI root buses is
89disallowed.
90
Linus Torvalds1da177e2005-04-16 15:20:36 -070091Accessing legacy resources through sysfs
Jesse Barnes5d135dff2005-12-09 11:55:03 -080092----------------------------------------
Linus Torvalds1da177e2005-04-16 15:20:36 -070093
94Legacy I/O port and ISA memory resources are also provided in sysfs if the
Uwe Kleine-König1b3c3712007-02-17 19:23:03 +010095underlying platform supports them. They're located in the PCI class hierarchy,
Linus Torvalds1da177e2005-04-16 15:20:36 -070096e.g.
97
98 /sys/class/pci_bus/0000:17/
99 |-- bridge -> ../../../devices/pci0000:17
100 |-- cpuaffinity
101 |-- legacy_io
102 `-- legacy_mem
103
104The legacy_io file is a read/write file that can be used by applications to
105do legacy port I/O. The application should open the file, seek to the desired
106port (e.g. 0x3e8) and do a read or a write of 1, 2 or 4 bytes. The legacy_mem
107file should be mmapped with an offset corresponding to the memory offset
108desired, e.g. 0xa0000 for the VGA frame buffer. The application can then
109simply dereference the returned pointer (after checking for errors of course)
110to access legacy memory space.
111
112Supporting PCI access on new platforms
Jesse Barnes5d135dff2005-12-09 11:55:03 -0800113--------------------------------------
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114
115In order to support PCI resource mapping as described above, Linux platform
David Woodhousef7195822017-04-12 13:25:59 +0100116code should ideally define ARCH_GENERIC_PCI_MMAP_RESOURCE and use the generic
117implementation of that functionality. To support the historical interface of
118mmap() through files in /proc/bus/pci, platforms may also set HAVE_PCI_MMAP.
119
120Alternatively, platforms which set HAVE_PCI_MMAP may provide their own
121implementation of pci_mmap_page_range() instead of defining
122ARCH_GENERIC_PCI_MMAP_RESOURCE.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123
David Woodhouseae749c72017-04-12 13:25:54 +0100124Platforms which support write-combining maps of PCI resources must define
125arch_can_pci_mmap_wc() which shall evaluate to non-zero at runtime when
David Woodhousee854d8b2017-04-12 13:25:56 +0100126write-combining is permitted. Platforms which support maps of I/O resources
127define arch_can_pci_mmap_io() similarly.
David Woodhouseae749c72017-04-12 13:25:54 +0100128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129Legacy resources are protected by the HAVE_PCI_LEGACY define. Platforms
130wishing to support legacy functionality should define it and provide
David Brownell0b405a02005-05-12 12:06:27 -0700131pci_legacy_read, pci_legacy_write and pci_mmap_legacy_page_range functions.