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Byungho Minff54b452009-06-23 21:39:49 +09001/* linux/arch/arm/mach-s5pc100/include/mach/map.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
Marek Szyprowskiacc84702010-05-20 07:51:08 +02006 * S5PC100 - Memory map definitions
Byungho Minff54b452009-06-23 21:39:49 +09007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
Marek Szyprowskiacc84702010-05-20 07:51:08 +020017#include <plat/map-s5p.h>
Byungho Minff54b452009-06-23 21:39:49 +090018
Kyungmin Parkb0cc3032009-11-17 08:41:11 +010019/*
20 * map-base.h has already defined virtual memory address
21 * S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s)
22 * S3C_VA_SYS S3C_ADDR(0x00100000) system control
23 * S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used)
24 * S3C_VA_TIMER S3C_ADDR(0x00300000) timer block
25 * S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog
26 * S3C_VA_UART S3C_ADDR(0x01000000) UART
27 *
28 * S5PC100 specific virtual memory address can be defined here
29 * S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO
30 *
31 */
Byungho Minff54b452009-06-23 21:39:49 +090032
Marek Szyprowski999304b2010-05-20 08:59:05 +020033#define S5PC100_PA_ONENAND_BUF (0xB0000000)
34#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
35
Byungho Minff54b452009-06-23 21:39:49 +090036/* Chip ID */
Ben Dooks206a1a82010-05-20 20:25:59 +090037
Byungho Minff54b452009-06-23 21:39:49 +090038#define S5PC100_PA_CHIPID (0xE0000000)
Marek Szyprowskiacc84702010-05-20 07:51:08 +020039#define S5P_PA_CHIPID S5PC100_PA_CHIPID
Byungho Minff54b452009-06-23 21:39:49 +090040
Marek Szyprowskiacc84702010-05-20 07:51:08 +020041#define S5PC100_PA_SYSCON (0xE0100000)
42#define S5P_PA_SYSCON S5PC100_PA_SYSCON
Kyungmin Parkb0cc3032009-11-17 08:41:11 +010043
Marek Szyprowskiacc84702010-05-20 07:51:08 +020044#define S5PC100_PA_OTHERS (0xE0200000)
45#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
46
Kyungmin Parkb0cc3032009-11-17 08:41:11 +010047#define S5PC100_PA_GPIO (0xE0300000)
Byungho Minff54b452009-06-23 21:39:49 +090048
Byungho Minff54b452009-06-23 21:39:49 +090049#define S5PC1XX_PA_GPIO S5PC100_PA_GPIO
50#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
Byungho Minff54b452009-06-23 21:39:49 +090051
Byungho Minff54b452009-06-23 21:39:49 +090052/* Interrupt */
53#define S5PC100_PA_VIC (0xE4000000)
54#define S5PC100_VA_VIC S3C_VA_IRQ
55#define S5PC100_PA_VIC_OFFSET 0x100000
56#define S5PC100_VA_VIC_OFFSET 0x10000
57#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
58#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
Kyungmin Parkb0cc3032009-11-17 08:41:11 +010059
Marek Szyprowski999304b2010-05-20 08:59:05 +020060#define S5PC100_PA_ONENAND (0xE7100000)
Marek Szyprowskiacc84702010-05-20 07:51:08 +020061
Byungho Minff54b452009-06-23 21:39:49 +090062/* DMA */
63#define S5PC100_PA_MDMA (0xE8100000)
64#define S5PC100_PA_PDMA0 (0xE9000000)
65#define S5PC100_PA_PDMA1 (0xE9200000)
66
67/* Timer */
68#define S5PC100_PA_TIMER (0xEA000000)
Marek Szyprowskiacc84702010-05-20 07:51:08 +020069#define S5P_PA_TIMER S5PC100_PA_TIMER
Byungho Minff54b452009-06-23 21:39:49 +090070
Marek Szyprowskiacc84702010-05-20 07:51:08 +020071#define S5PC100_PA_SYSTIMER (0xEA100000)
Kyungmin Parkb0cc3032009-11-17 08:41:11 +010072
Byungho Minff54b452009-06-23 21:39:49 +090073#define S5PC100_PA_UART (0xEC000000)
Byungho Minff54b452009-06-23 21:39:49 +090074
Marek Szyprowskiacc84702010-05-20 07:51:08 +020075#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0)
76#define S5P_PA_UART1 (S5PC100_PA_UART + 0x400)
77#define S5P_PA_UART2 (S5PC100_PA_UART + 0x800)
78#define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00)
79#define S5P_SZ_UART SZ_256
Kyungmin Parkb0cc3032009-11-17 08:41:11 +010080
Marek Szyprowskiacc84702010-05-20 07:51:08 +020081#define S5PC100_PA_IIC0 (0xEC100000)
82#define S5PC100_PA_IIC1 (0xEC200000)
Kyungmin Parkb0cc3032009-11-17 08:41:11 +010083
Jassi Brar7c3943f2010-05-18 16:43:34 +090084/* SPI */
85#define S5PC100_PA_SPI0 0xEC300000
86#define S5PC100_PA_SPI1 0xEC400000
87#define S5PC100_PA_SPI2 0xEC500000
88
Kyungmin Parkb0cc3032009-11-17 08:41:11 +010089/* USB HS OTG */
90#define S5PC100_PA_USB_HSOTG (0xED200000)
91#define S5PC100_PA_USB_HSPHY (0xED300000)
92
Kyungmin Parkb0cc3032009-11-17 08:41:11 +010093#define S5PC100_PA_FB (0xEE000000)
94
Jassi Brar9e4ed5c32010-05-18 16:02:39 +090095#define S5PC100_PA_AC97 0xF2300000
96
97/* PCM */
98#define S5PC100_PA_PCM0 0xF2400000
99#define S5PC100_PA_PCM1 0xF2500000
100
Kyungmin Parkb0cc3032009-11-17 08:41:11 +0100101/* KEYPAD */
102#define S5PC100_PA_KEYPAD (0xF3100000)
103
Marek Szyprowskiacc84702010-05-20 07:51:08 +0200104#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
Kyungmin Parkb0cc3032009-11-17 08:41:11 +0100105
Byungho Minff54b452009-06-23 21:39:49 +0900106#define S5PC100_PA_SDRAM (0x20000000)
Marek Szyprowskiacc84702010-05-20 07:51:08 +0200107#define S5P_PA_SDRAM S5PC100_PA_SDRAM
Byungho Minff54b452009-06-23 21:39:49 +0900108
Marek Szyprowskiacc84702010-05-20 07:51:08 +0200109/* compatibiltiy defines. */
Byungho Minff54b452009-06-23 21:39:49 +0900110#define S3C_PA_UART S5PC100_PA_UART
Marek Szyprowskiacc84702010-05-20 07:51:08 +0200111#define S3C_PA_IIC S5PC100_PA_IIC0
112#define S3C_PA_IIC1 S5PC100_PA_IIC1
Kyungmin Parkb0cc3032009-11-17 08:41:11 +0100113#define S3C_PA_FB S5PC100_PA_FB
114#define S3C_PA_G2D S5PC100_PA_G2D
115#define S3C_PA_G3D S5PC100_PA_G3D
116#define S3C_PA_JPEG S5PC100_PA_JPEG
117#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR
Byungho Minff54b452009-06-23 21:39:49 +0900118#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0)
119#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
120#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000)
Kyungmin Parkb0cc3032009-11-17 08:41:11 +0100121#define S3C_PA_IIC S5PC100_PA_I2C
122#define S3C_PA_IIC1 S5PC100_PA_I2C1
123#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
124#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
125#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC0
126#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC1
127#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2
128#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
129#define S3C_PA_TSADC S5PC100_PA_TSADC
Marek Szyprowski999304b2010-05-20 08:59:05 +0200130#define S3C_PA_ONENAND S5PC100_PA_ONENAND
131#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
132#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF
Byungho Minff54b452009-06-23 21:39:49 +0900133
134#endif /* __ASM_ARCH_C100_MAP_H */