blob: eaf0003ddfd960eb6918430f3b8222a3eba6c5cf [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
Damien Lespiau178f7362013-08-06 20:32:18 +010029#include <linux/hdmi.h>
David Howells760285e2012-10-02 18:01:07 +010030#include <drm/i915_drm.h>
Jesse Barnes80824002009-09-10 15:28:06 -070031#include "i915_drv.h"
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_fb_helper.h>
Linus Torvalds612a9aa2012-10-03 23:29:23 -070035#include <drm/drm_dp_helper.h>
Chris Wilson913d8d12010-08-07 11:01:35 +010036
Daniel Vetter1d5bfac2013-03-28 00:03:25 +010037/**
38 * _wait_for - magic (register) wait macro
39 *
40 * Does the right thing for modeset paths when run under kdgb or similar atomic
41 * contexts. Note that it's important that we check the condition again after
42 * having timed out, since the timeout could be due to preemption or similar and
43 * we've never had a chance to check the condition before the timeout.
44 */
Chris Wilson481b6af2010-08-23 17:43:35 +010045#define _wait_for(COND, MS, W) ({ \
Daniel Vetter1d5bfac2013-03-28 00:03:25 +010046 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
Chris Wilson913d8d12010-08-07 11:01:35 +010047 int ret__ = 0; \
Akshay Joshi0206e352011-08-16 15:34:10 -040048 while (!(COND)) { \
Chris Wilson913d8d12010-08-07 11:01:35 +010049 if (time_after(jiffies, timeout__)) { \
Daniel Vetter1d5bfac2013-03-28 00:03:25 +010050 if (!(COND)) \
51 ret__ = -ETIMEDOUT; \
Chris Wilson913d8d12010-08-07 11:01:35 +010052 break; \
53 } \
Ben Widawsky0cc27642012-09-01 22:59:48 -070054 if (W && drm_can_sleep()) { \
55 msleep(W); \
56 } else { \
57 cpu_relax(); \
58 } \
Chris Wilson913d8d12010-08-07 11:01:35 +010059 } \
60 ret__; \
61})
62
Chris Wilson481b6af2010-08-23 17:43:35 +010063#define wait_for(COND, MS) _wait_for(COND, MS, 1)
64#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
Daniel Vetter6effa332013-03-28 11:31:04 +010065#define wait_for_atomic_us(COND, US) _wait_for((COND), \
66 DIV_ROUND_UP((US), 1000), 0)
Chris Wilson481b6af2010-08-23 17:43:35 +010067
Chris Wilson021357a2010-09-07 20:54:59 +010068#define KHz(x) (1000*x)
69#define MHz(x) KHz(1000*x)
70
Jesse Barnes79e53942008-11-07 14:24:08 -080071/*
72 * Display related stuff
73 */
74
75/* store information about an Ixxx DVO */
76/* The i830->i865 use multiple DVOs with multiple i2cs */
77/* the i915, i945 have a single sDVO i2c bus - which is different */
78#define MAX_OUTPUTS 6
79/* maximum connectors per crtcs in the mode set */
Jesse Barnes79e53942008-11-07 14:24:08 -080080
81#define INTEL_I2C_BUS_DVO 1
82#define INTEL_I2C_BUS_SDVO 2
83
84/* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86#define INTEL_OUTPUT_UNUSED 0
87#define INTEL_OUTPUT_ANALOG 1
88#define INTEL_OUTPUT_DVO 2
89#define INTEL_OUTPUT_SDVO 3
90#define INTEL_OUTPUT_LVDS 4
91#define INTEL_OUTPUT_TVOUT 5
Eric Anholt7d573822009-01-02 13:33:00 -080092#define INTEL_OUTPUT_HDMI 6
Keith Packarda4fc5ed2009-04-07 16:16:42 -070093#define INTEL_OUTPUT_DISPLAYPORT 7
Zhenyu Wang32f9d652009-07-24 01:00:32 +080094#define INTEL_OUTPUT_EDP 8
Jani Nikula72ffa332013-08-27 15:12:17 +030095#define INTEL_OUTPUT_DSI 9
96#define INTEL_OUTPUT_UNKNOWN 10
Jesse Barnes79e53942008-11-07 14:24:08 -080097
98#define INTEL_DVO_CHIP_NONE 0
99#define INTEL_DVO_CHIP_LVDS 1
100#define INTEL_DVO_CHIP_TMDS 2
101#define INTEL_DVO_CHIP_TVOUT 4
102
Jani Nikula72ffa332013-08-27 15:12:17 +0300103#define INTEL_DSI_COMMAND_MODE 0
104#define INTEL_DSI_VIDEO_MODE 1
105
Jesse Barnes79e53942008-11-07 14:24:08 -0800106struct intel_framebuffer {
107 struct drm_framebuffer base;
Chris Wilson05394f32010-11-08 19:18:58 +0000108 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -0800109};
110
Chris Wilson37811fc2010-08-25 22:45:57 +0100111struct intel_fbdev {
112 struct drm_fb_helper helper;
113 struct intel_framebuffer ifb;
114 struct list_head fbdev_list;
115 struct drm_display_mode *our_mode;
116};
Jesse Barnes79e53942008-11-07 14:24:08 -0800117
Eric Anholt21d40d32010-03-25 11:11:14 -0700118struct intel_encoder {
Chris Wilson4ef69c72010-09-09 15:14:28 +0100119 struct drm_encoder base;
Daniel Vetter9a935852012-07-05 22:34:27 +0200120 /*
121 * The new crtc this encoder will be driven from. Only differs from
122 * base->crtc while a modeset is in progress.
123 */
124 struct intel_crtc *new_crtc;
125
Jesse Barnes79e53942008-11-07 14:24:08 -0800126 int type;
Daniel Vetter66a92782012-07-12 20:08:18 +0200127 /*
128 * Intel hw has only one MUX where encoders could be clone, hence a
129 * simple flag is enough to compute the possible_clones mask.
130 */
131 bool cloneable;
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200132 bool connectors_active;
Eric Anholt21d40d32010-03-25 11:11:14 -0700133 void (*hot_plug)(struct intel_encoder *);
Daniel Vetter7ae89232013-03-27 00:44:52 +0100134 bool (*compute_config)(struct intel_encoder *,
135 struct intel_crtc_config *);
Daniel Vetterdafd2262012-11-26 17:22:07 +0100136 void (*pre_pll_enable)(struct intel_encoder *);
Daniel Vetterbf49ec8c2012-09-06 22:15:40 +0200137 void (*pre_enable)(struct intel_encoder *);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +0200138 void (*enable)(struct intel_encoder *);
Daniel Vetter6cc5f342013-03-27 00:44:53 +0100139 void (*mode_set)(struct intel_encoder *intel_encoder);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +0200140 void (*disable)(struct intel_encoder *);
Daniel Vetterbf49ec8c2012-09-06 22:15:40 +0200141 void (*post_disable)(struct intel_encoder *);
Daniel Vetterf0947c32012-07-02 13:10:34 +0200142 /* Read out the current hw state of this connector, returning true if
143 * the encoder is active. If the encoder is enabled it also set the pipe
144 * it is connected to in the pipe parameter. */
145 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700146 /* Reconstructs the equivalent mode flags for the current hardware
Daniel Vetterfdafa9e2013-06-12 11:47:24 +0200147 * state. This must be called _after_ display->get_pipe_config has
Xiong Zhang63000ef2013-06-28 12:59:06 +0800148 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
149 * be set correctly before calling this function. */
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700150 void (*get_config)(struct intel_encoder *,
151 struct intel_crtc_config *pipe_config);
Ma Lingf8aed702009-08-24 13:50:24 +0800152 int crtc_mask;
Egbert Eich1d843f92013-02-25 12:06:49 -0500153 enum hpd_pin hpd_pin;
Jesse Barnes79e53942008-11-07 14:24:08 -0800154};
155
Jani Nikula1d508702012-10-19 14:51:49 +0300156struct intel_panel {
Jani Nikuladd06f902012-10-19 14:51:50 +0300157 struct drm_display_mode *fixed_mode;
Jani Nikula4d891522012-10-26 12:03:59 +0300158 int fitting_mode;
Jani Nikula1d508702012-10-19 14:51:49 +0300159};
160
Zhenyu Wang5daa55e2010-03-30 14:39:28 +0800161struct intel_connector {
162 struct drm_connector base;
Daniel Vetter9a935852012-07-05 22:34:27 +0200163 /*
164 * The fixed encoder this connector is connected to.
165 */
Chris Wilsondf0e9242010-09-09 16:20:55 +0100166 struct intel_encoder *encoder;
Daniel Vetter9a935852012-07-05 22:34:27 +0200167
168 /*
169 * The new encoder this connector will be driven. Only differs from
170 * encoder while a modeset is in progress.
171 */
172 struct intel_encoder *new_encoder;
173
Daniel Vetterf0947c32012-07-02 13:10:34 +0200174 /* Reads out the current hw, returning true if the connector is enabled
175 * and active (i.e. dpms ON state). */
176 bool (*get_hw_state)(struct intel_connector *);
Jani Nikula1d508702012-10-19 14:51:49 +0300177
178 /* Panel info for eDP and LVDS */
179 struct intel_panel panel;
Jani Nikula9cd300e2012-10-19 14:51:52 +0300180
181 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
182 struct edid *edid;
Egbert Eich821450c2013-04-16 13:36:55 +0200183
184 /* since POLL and HPD connectors may use the same HPD line keep the native
185 state of connector->polled in case hotplug storm detection changes it */
186 u8 polled;
Zhenyu Wang5daa55e2010-03-30 14:39:28 +0800187};
188
Ville Syrjälä80ad9202013-04-19 14:36:51 +0300189typedef struct dpll {
190 /* given values */
191 int n;
192 int m1, m2;
193 int p1, p2;
194 /* derived values */
195 int dot;
196 int vco;
197 int m;
198 int p;
199} intel_clock_t;
200
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100201struct intel_crtc_config {
Daniel Vetterbb760062013-06-06 14:55:52 +0200202 /**
203 * quirks - bitfield with hw state readout quirks
204 *
205 * For various reasons the hw state readout code might not be able to
206 * completely faithfully read out the current state. These cases are
207 * tracked with quirk flags so that fastboot and state checker can act
208 * accordingly.
209 */
210#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
211 unsigned long quirks;
212
Ville Syrjälä5113bc92013-09-04 18:25:29 +0300213 /* User requested mode, only valid as a starting point to
214 * compute adjusted_mode, except in the case of (S)DVO where
215 * it's also for the output timings of the (S)DVO chip.
216 * adjusted_mode will then correspond to the S(DVO) chip's
217 * preferred input timings. */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100218 struct drm_display_mode requested_mode;
Ville Syrjälä3c52f4e2013-09-06 23:28:59 +0300219 /* Actual pipe timings ie. what we program into the pipe timing
Damien Lespiau241bfc32013-09-25 16:45:37 +0100220 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100221 struct drm_display_mode adjusted_mode;
Ville Syrjälä37327ab2013-09-04 18:25:28 +0300222
223 /* Pipe source size (ie. panel fitter input size)
224 * All planes will be positioned inside this space,
225 * and get clipped at the edges. */
226 int pipe_src_w, pipe_src_h;
227
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100228 /* Whether to set up the PCH/FDI. Note that we never allow sharing
229 * between pch encoders and cpu encoders. */
230 bool has_pch_encoder;
Daniel Vetter50f3b012013-03-27 00:44:56 +0100231
Daniel Vetter3b117c82013-04-17 20:15:07 +0200232 /* CPU Transcoder for the pipe. Currently this can only differ from the
233 * pipe on Haswell (where we have a special eDP transcoder). */
234 enum transcoder cpu_transcoder;
235
Daniel Vetter50f3b012013-03-27 00:44:56 +0100236 /*
237 * Use reduced/limited/broadcast rbg range, compressing from the full
238 * range fed into the crtcs.
239 */
240 bool limited_color_range;
241
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200242 /* DP has a bunch of special case unfortunately, so mark the pipe
243 * accordingly. */
244 bool has_dp_encoder;
Daniel Vetterd8b32242013-04-25 17:54:44 +0200245
246 /*
247 * Enable dithering, used when the selected pipe bpp doesn't match the
248 * plane bpp.
249 */
Daniel Vetter965e0c42013-03-27 00:44:57 +0100250 bool dither;
Daniel Vetterf47709a2013-03-28 10:42:02 +0100251
252 /* Controls for the clock computation, to override various stages. */
253 bool clock_set;
254
Daniel Vetter09ede542013-04-30 14:01:45 +0200255 /* SDVO TV has a bunch of special case. To make multifunction encoders
256 * work correctly, we need to track this at runtime.*/
257 bool sdvo_tv_clock;
258
Daniel Vettere29c22c2013-02-21 00:00:16 +0100259 /*
260 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
261 * required. This is set in the 2nd loop of calling encoder's
262 * ->compute_config if the first pick doesn't work out.
263 */
264 bool bw_constrained;
265
Daniel Vetterf47709a2013-03-28 10:42:02 +0100266 /* Settings for the intel dpll used on pretty much everything but
267 * haswell. */
Ville Syrjälä80ad9202013-04-19 14:36:51 +0300268 struct dpll dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +0100269
Daniel Vettera43f6e02013-06-07 23:10:32 +0200270 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
271 enum intel_dpll_id shared_dpll;
272
Daniel Vetter66e985c2013-06-05 13:34:20 +0200273 /* Actual register state of the dpll, for shared dpll cross-checking. */
274 struct intel_dpll_hw_state dpll_hw_state;
275
Daniel Vetter965e0c42013-03-27 00:44:57 +0100276 int pipe_bpp;
Daniel Vetter6cf86a52013-04-02 23:38:10 +0200277 struct intel_link_m_n dp_m_n;
Daniel Vetterff9a6752013-06-01 17:16:21 +0200278
279 /*
280 * Frequence the dpll for the port should run at. Differs from the
Ville Syrjälä3c52f4e2013-09-06 23:28:59 +0300281 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
282 * already multiplied by pixel_multiplier.
Daniel Vetterdf92b1e2013-03-28 10:41:58 +0100283 */
Daniel Vetterff9a6752013-06-01 17:16:21 +0200284 int port_clock;
285
Daniel Vetter6cc5f342013-03-27 00:44:53 +0100286 /* Used by SDVO (and if we ever fix it, HDMI). */
287 unsigned pixel_multiplier;
Jesse Barnes2dd24552013-04-25 12:55:01 -0700288
289 /* Panel fitter controls for gen2-gen4 + VLV */
Jesse Barnesb074cec2013-04-25 12:55:02 -0700290 struct {
291 u32 control;
292 u32 pgm_ratios;
Daniel Vetter68fc8742013-04-25 22:52:16 +0200293 u32 lvds_border_bits;
Jesse Barnesb074cec2013-04-25 12:55:02 -0700294 } gmch_pfit;
295
296 /* Panel fitter placement and size for Ironlake+ */
297 struct {
298 u32 pos;
299 u32 size;
Chris Wilsonfd4daa92013-08-27 17:04:17 +0100300 bool enabled;
Jesse Barnesb074cec2013-04-25 12:55:02 -0700301 } pch_pfit;
Daniel Vetter33d29b12013-02-13 18:04:45 +0100302
Daniel Vetterca3a0ff2013-02-14 16:54:22 +0100303 /* FDI configuration, only valid if has_pch_encoder is set. */
Daniel Vetter33d29b12013-02-13 18:04:45 +0100304 int fdi_lanes;
Daniel Vetterca3a0ff2013-02-14 16:54:22 +0100305 struct intel_link_m_n fdi_m_n;
Paulo Zanoni42db64e2013-05-31 16:33:22 -0300306
307 bool ips_enabled;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +0300308
309 bool double_wide;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100310};
311
Jesse Barnes79e53942008-11-07 14:24:08 -0800312struct intel_crtc {
313 struct drm_crtc base;
Jesse Barnes80824002009-09-10 15:28:06 -0700314 enum pipe pipe;
315 enum plane plane;
Jesse Barnes79e53942008-11-07 14:24:08 -0800316 u8 lut_r[256], lut_g[256], lut_b[256];
Daniel Vetter08a48462012-07-02 11:43:47 +0200317 /*
318 * Whether the crtc and the connected output pipeline is active. Implies
319 * that crtc->enabled is set, i.e. the current mode configuration has
320 * some outputs connected to this crtc.
Daniel Vetter08a48462012-07-02 11:43:47 +0200321 */
322 bool active;
Wang Xingchao7b9f35a2013-01-22 23:25:25 +0800323 bool eld_vld;
Chris Wilson93314b52012-06-13 17:36:55 +0100324 bool primary_disabled; /* is the crtc obscured by a plane? */
Jesse Barnes652c3932009-08-17 13:31:43 -0700325 bool lowfreq_avail;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200326 struct intel_overlay *overlay;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500327 struct intel_unpin_work *unpin_work;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +0100328
Chris Wilsonb4a98e52012-11-01 09:26:26 +0000329 atomic_t unpin_work_count;
330
Daniel Vettere506a0c2012-07-05 12:17:29 +0200331 /* Display surface base address adjustement for pageflips. Note that on
332 * gen4+ this only adjusts up to a tile, offsets within a tile are
333 * handled in the hw itself (with the TILEOFF register). */
334 unsigned long dspaddr_offset;
335
Chris Wilson05394f32010-11-08 19:18:58 +0000336 struct drm_i915_gem_object *cursor_bo;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +0100337 uint32_t cursor_addr;
338 int16_t cursor_x, cursor_y;
339 int16_t cursor_width, cursor_height;
Chris Wilson6b383a72010-09-13 13:54:26 +0100340 bool cursor_visible;
Jesse Barnes4b645f12011-10-12 09:51:31 -0700341
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100342 struct intel_crtc_config config;
343
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300344 uint32_t ddi_pll_sel;
Ville Syrjälä10d83732013-01-29 18:13:34 +0200345
346 /* reset counter value when the last flip was submitted */
347 unsigned int reset_counter;
Paulo Zanoni86642812013-04-12 17:57:57 -0300348
349 /* Access to these should be protected by dev_priv->irq_lock. */
350 bool cpu_fifo_underrun_disabled;
351 bool pch_fifo_underrun_disabled;
Jesse Barnes79e53942008-11-07 14:24:08 -0800352};
353
Ville Syrjäläc35426d2013-08-07 13:29:50 +0300354struct intel_plane_wm_parameters {
355 uint32_t horiz_pixels;
356 uint8_t bytes_per_pixel;
357 bool enabled;
358 bool scaled;
359};
360
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800361struct intel_plane {
362 struct drm_plane base;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700363 int plane;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800364 enum pipe pipe;
365 struct drm_i915_gem_object *obj;
Damien Lespiau2d354c32012-10-22 18:19:27 +0100366 bool can_scale;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800367 int max_downscale;
368 u32 lut_r[1024], lut_g[1024], lut_b[1024];
Jesse Barnes5e1bac22013-03-26 09:25:43 -0700369 int crtc_x, crtc_y;
370 unsigned int crtc_w, crtc_h;
371 uint32_t src_x, src_y;
372 uint32_t src_w, src_h;
Paulo Zanoni526682e2013-05-24 11:59:18 -0300373
374 /* Since we need to change the watermarks before/after
375 * enabling/disabling the planes, we need to store the parameters here
376 * as the other pieces of the struct may not reflect the values we want
377 * for the watermark calculations. Currently only Haswell uses this.
378 */
Ville Syrjäläc35426d2013-08-07 13:29:50 +0300379 struct intel_plane_wm_parameters wm;
Paulo Zanoni526682e2013-05-24 11:59:18 -0300380
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800381 void (*update_plane)(struct drm_plane *plane,
Ville Syrjäläb39d53f2013-08-06 22:24:09 +0300382 struct drm_crtc *crtc,
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800383 struct drm_framebuffer *fb,
384 struct drm_i915_gem_object *obj,
385 int crtc_x, int crtc_y,
386 unsigned int crtc_w, unsigned int crtc_h,
387 uint32_t x, uint32_t y,
388 uint32_t src_w, uint32_t src_h);
Ville Syrjäläb39d53f2013-08-06 22:24:09 +0300389 void (*disable_plane)(struct drm_plane *plane,
390 struct drm_crtc *crtc);
Jesse Barnes8ea30862012-01-03 08:05:39 -0800391 int (*update_colorkey)(struct drm_plane *plane,
392 struct drm_intel_sprite_colorkey *key);
393 void (*get_colorkey)(struct drm_plane *plane,
394 struct drm_intel_sprite_colorkey *key);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800395};
396
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300397struct intel_watermark_params {
398 unsigned long fifo_size;
399 unsigned long max_wm;
400 unsigned long default_wm;
401 unsigned long guard_size;
402 unsigned long cacheline_size;
403};
404
405struct cxsr_latency {
406 int is_desktop;
407 int is_ddr3;
408 unsigned long fsb_freq;
409 unsigned long mem_freq;
410 unsigned long display_sr;
411 unsigned long display_hpll_disable;
412 unsigned long cursor_sr;
413 unsigned long cursor_hpll_disable;
414};
415
Jesse Barnes79e53942008-11-07 14:24:08 -0800416#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
Zhenyu Wang5daa55e2010-03-30 14:39:28 +0800417#define to_intel_connector(x) container_of(x, struct intel_connector, base)
Chris Wilson4ef69c72010-09-09 15:14:28 +0100418#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
Jesse Barnes79e53942008-11-07 14:24:08 -0800419#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800420#define to_intel_plane(x) container_of(x, struct intel_plane, base)
Jesse Barnes79e53942008-11-07 14:24:08 -0800421
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300422struct intel_hdmi {
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300423 u32 hdmi_reg;
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300424 int ddc_bus;
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300425 uint32_t color_range;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200426 bool color_range_auto;
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300427 bool has_hdmi_sink;
428 bool has_audio;
429 enum hdmi_force_audio force_audio;
Ville Syrjäläabedc072013-01-17 16:31:31 +0200430 bool rgb_quant_range_selectable;
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300431 void (*write_infoframe)(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100432 enum hdmi_infoframe_type type,
433 const uint8_t *frame, ssize_t len);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300434 void (*set_infoframes)(struct drm_encoder *encoder,
435 struct drm_display_mode *adjusted_mode);
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300436};
437
Adam Jacksonb091cd92012-09-18 10:58:49 -0400438#define DP_MAX_DOWNSTREAM_PORTS 0x10
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300439
440struct intel_dp {
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300441 uint32_t output_reg;
Paulo Zanoni9ed35ab2013-02-18 19:00:25 -0300442 uint32_t aux_ch_ctl_reg;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300443 uint32_t DP;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300444 bool has_audio;
445 enum hdmi_force_audio force_audio;
446 uint32_t color_range;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200447 bool color_range_auto;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300448 uint8_t link_bw;
449 uint8_t lane_count;
450 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
Shobhit Kumar2293bb52013-07-11 18:44:56 -0300451 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
Adam Jacksonb091cd92012-09-18 10:58:49 -0400452 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300453 struct i2c_adapter adapter;
454 struct i2c_algo_dp_aux_data algo;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300455 uint8_t train_set[4];
456 int panel_power_up_delay;
457 int panel_power_down_delay;
458 int panel_power_cycle_delay;
459 int backlight_on_delay;
460 int backlight_off_delay;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300461 struct delayed_work panel_vdd_work;
462 bool want_panel_vdd;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -0300463 bool psr_setup_done;
Jani Nikuladd06f902012-10-19 14:51:50 +0300464 struct intel_connector *attached_connector;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300465};
466
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200467struct intel_digital_port {
468 struct intel_encoder base;
Paulo Zanoni174edf12012-10-26 19:05:50 -0200469 enum port port;
Stéphane Marchesinbcf53de2013-07-12 13:54:41 -0700470 u32 saved_port_bits;
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200471 struct intel_dp dp;
472 struct intel_hdmi hdmi;
473};
474
Jesse Barnes89b667f2013-04-18 14:51:36 -0700475static inline int
476vlv_dport_to_channel(struct intel_digital_port *dport)
477{
478 switch (dport->port) {
479 case PORT_B:
480 return 0;
481 case PORT_C:
482 return 1;
483 default:
484 BUG();
485 }
486}
487
Chris Wilsonf875c152010-09-09 15:44:14 +0100488static inline struct drm_crtc *
489intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
490{
491 struct drm_i915_private *dev_priv = dev->dev_private;
492 return dev_priv->pipe_to_crtc_mapping[pipe];
493}
494
Chris Wilson417ae142011-01-19 15:04:42 +0000495static inline struct drm_crtc *
496intel_get_crtc_for_plane(struct drm_device *dev, int plane)
497{
498 struct drm_i915_private *dev_priv = dev->dev_private;
499 return dev_priv->plane_to_crtc_mapping[plane];
500}
501
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100502struct intel_unpin_work {
503 struct work_struct work;
Chris Wilsonb4a98e52012-11-01 09:26:26 +0000504 struct drm_crtc *crtc;
Chris Wilson05394f32010-11-08 19:18:58 +0000505 struct drm_i915_gem_object *old_fb_obj;
506 struct drm_i915_gem_object *pending_flip_obj;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100507 struct drm_pending_vblank_event *event;
Chris Wilsone7d841c2012-12-03 11:36:30 +0000508 atomic_t pending;
509#define INTEL_FLIP_INACTIVE 0
510#define INTEL_FLIP_PENDING 1
511#define INTEL_FLIP_COMPLETE 2
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100512 bool enable_stall_check;
513};
514
Daniel Vetterd9e55602012-07-04 22:16:09 +0200515struct intel_set_config {
Daniel Vetter1aa4b622012-07-05 16:20:48 +0200516 struct drm_encoder **save_connector_encoders;
517 struct drm_crtc **save_encoder_crtcs;
Daniel Vetter5e2b5842012-07-04 22:41:29 +0200518
519 bool fb_changed;
520 bool mode_changed;
Daniel Vetterd9e55602012-07-04 22:16:09 +0200521};
522
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300523struct intel_load_detect_pipe {
524 struct drm_framebuffer *release_fb;
525 bool load_detect_temp;
526 int dpms_mode;
527};
Daniel Vetterb9805142012-08-31 17:37:33 +0200528
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300529static inline struct intel_encoder *
530intel_attached_encoder(struct drm_connector *connector)
Chris Wilsondf0e9242010-09-09 16:20:55 +0100531{
532 return to_intel_connector(connector)->encoder;
533}
534
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200535static inline struct intel_digital_port *
536enc_to_dig_port(struct drm_encoder *encoder)
537{
538 return container_of(encoder, struct intel_digital_port, base.base);
539}
540
Imre Deak9ff8c9b2013-05-08 13:14:02 +0300541static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
542{
543 return &enc_to_dig_port(encoder)->dp;
544}
545
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200546static inline struct intel_digital_port *
547dp_to_dig_port(struct intel_dp *intel_dp)
548{
549 return container_of(intel_dp, struct intel_digital_port, dp);
550}
551
552static inline struct intel_digital_port *
553hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
554{
555 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
Paulo Zanoni7739c332012-10-15 15:51:29 -0300556}
557
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000558
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300559/* i915_irq.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300560bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
561 enum pipe pipe, bool enable);
562bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
563 enum transcoder pch_transcoder,
564 bool enable);
565void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
566void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
567void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
568void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
569void hsw_pc8_disable_interrupts(struct drm_device *dev);
570void hsw_pc8_restore_interrupts(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -0800571
Chris Wilson8261b192011-04-19 23:18:09 +0100572
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300573/* intel_crt.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300574void intel_crt_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -0800575
Jesse Barnes79e53942008-11-07 14:24:08 -0800576
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300577/* intel_ddi.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300578void intel_prepare_ddi(struct drm_device *dev);
579void hsw_fdi_link_train(struct drm_crtc *crtc);
580void intel_ddi_init(struct drm_device *dev, enum port port);
581enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
582bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
583int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
584void intel_ddi_pll_init(struct drm_device *dev);
585void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
586void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
587 enum transcoder cpu_transcoder);
588void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
589void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
590void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
591bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
592void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
593void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
594void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
595bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
596void intel_ddi_fdi_disable(struct drm_crtc *crtc);
597void intel_ddi_get_config(struct intel_encoder *encoder,
598 struct intel_crtc_config *pipe_config);
Eugeni Dodonov72662e12012-05-09 15:37:31 -0300599
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300600
601/* intel_display.c */
602int intel_pch_rawclk(struct drm_device *dev);
Paulo Zanoni87440422013-09-24 15:48:31 -0300603void intel_mark_busy(struct drm_device *dev);
604void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
605 struct intel_ring_buffer *ring);
606void intel_mark_idle(struct drm_device *dev);
607void intel_crtc_restore_mode(struct drm_crtc *crtc);
608void intel_crtc_update_dpms(struct drm_crtc *crtc);
609void intel_encoder_destroy(struct drm_encoder *encoder);
610void intel_connector_dpms(struct drm_connector *, int mode);
611bool intel_connector_get_hw_state(struct intel_connector *connector);
612void intel_modeset_check_state(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300613bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
614 struct intel_digital_port *port);
Paulo Zanoni87440422013-09-24 15:48:31 -0300615void intel_connector_attach_encoder(struct intel_connector *connector,
616 struct intel_encoder *encoder);
617struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
618struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
619 struct drm_crtc *crtc);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300620int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
621 struct drm_file *file_priv);
Paulo Zanoni87440422013-09-24 15:48:31 -0300622enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
623 enum pipe pipe);
624void intel_wait_for_vblank(struct drm_device *dev, int pipe);
625void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
626int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
627void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
628bool intel_get_load_detect_pipe(struct drm_connector *connector,
629 struct drm_display_mode *mode,
630 struct intel_load_detect_pipe *old);
631void intel_release_load_detect_pipe(struct drm_connector *connector,
632 struct intel_load_detect_pipe *old);
633int intel_pin_and_fence_fb_obj(struct drm_device *dev,
634 struct drm_i915_gem_object *obj,
635 struct intel_ring_buffer *pipelined);
636void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
637int intel_framebuffer_init(struct drm_device *dev,
638 struct intel_framebuffer *ifb,
639 struct drm_mode_fb_cmd2 *mode_cmd,
640 struct drm_i915_gem_object *obj);
641void intel_framebuffer_fini(struct intel_framebuffer *fb);
642void intel_prepare_page_flip(struct drm_device *dev, int plane);
643void intel_finish_page_flip(struct drm_device *dev, int pipe);
644void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300645struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
646void assert_shared_dpll(struct drm_i915_private *dev_priv,
647 struct intel_shared_dpll *pll,
648 bool state);
649#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
650#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
651void assert_pll(struct drm_i915_private *dev_priv,
652 enum pipe pipe, bool state);
653#define assert_pll_enabled(d, p) assert_pll(d, p, true)
654#define assert_pll_disabled(d, p) assert_pll(d, p, false)
655void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
656 enum pipe pipe, bool state);
657#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
658#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
Paulo Zanoni87440422013-09-24 15:48:31 -0300659void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300660#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
661#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
Paulo Zanoni87440422013-09-24 15:48:31 -0300662void intel_write_eld(struct drm_encoder *encoder,
663 struct drm_display_mode *mode);
664unsigned long intel_gen4_compute_page_offset(int *x, int *y,
665 unsigned int tiling_mode,
666 unsigned int bpp,
667 unsigned int pitch);
668void intel_display_handle_reset(struct drm_device *dev);
669void hsw_enable_pc8_work(struct work_struct *__work);
670void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
671void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
672void intel_dp_get_m_n(struct intel_crtc *crtc,
673 struct intel_crtc_config *pipe_config);
674int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
675void
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300676ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
677 int dotclock);
Paulo Zanoni87440422013-09-24 15:48:31 -0300678bool intel_crtc_active(struct drm_crtc *crtc);
679void i915_disable_vga_mem(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300680
681
682/* intel_dp.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300683void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
684bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
685 struct intel_connector *intel_connector);
Paulo Zanoni87440422013-09-24 15:48:31 -0300686void intel_dp_start_link_train(struct intel_dp *intel_dp);
687void intel_dp_complete_link_train(struct intel_dp *intel_dp);
688void intel_dp_stop_link_train(struct intel_dp *intel_dp);
689void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
690void intel_dp_encoder_destroy(struct drm_encoder *encoder);
691void intel_dp_check_link_status(struct intel_dp *intel_dp);
692bool intel_dp_compute_config(struct intel_encoder *encoder,
693 struct intel_crtc_config *pipe_config);
694bool intel_dpd_is_edp(struct drm_device *dev);
695void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
696void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
697void ironlake_edp_panel_on(struct intel_dp *intel_dp);
698void ironlake_edp_panel_off(struct intel_dp *intel_dp);
699void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
700void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
701void intel_edp_psr_enable(struct intel_dp *intel_dp);
702void intel_edp_psr_disable(struct intel_dp *intel_dp);
703void intel_edp_psr_update(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300704
705
706/* intel_dsi.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300707bool intel_dsi_init(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300708
709
710/* intel_dvo.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300711void intel_dvo_init(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300712
713
714/* intel_fb.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300715int intel_fbdev_init(struct drm_device *dev);
716void intel_fbdev_initial_config(struct drm_device *dev);
717void intel_fbdev_fini(struct drm_device *dev);
718void intel_fbdev_set_suspend(struct drm_device *dev, int state);
719void intel_fb_output_poll_changed(struct drm_device *dev);
720void intel_fb_restore_mode(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300721
722
723/* intel_hdmi.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300724void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
725void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
726 struct intel_connector *intel_connector);
727struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
728bool intel_hdmi_compute_config(struct intel_encoder *encoder,
729 struct intel_crtc_config *pipe_config);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300730
731
732/* intel_lvds.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300733void intel_lvds_init(struct drm_device *dev);
734bool intel_is_dual_link_lvds(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300735
736
737/* intel_modes.c */
738int intel_connector_update_modes(struct drm_connector *connector,
Paulo Zanoni87440422013-09-24 15:48:31 -0300739 struct edid *edid);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300740int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
Paulo Zanoni87440422013-09-24 15:48:31 -0300741void intel_attach_force_audio_property(struct drm_connector *connector);
742void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300743
744
745/* intel_overlay.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300746void intel_setup_overlay(struct drm_device *dev);
747void intel_cleanup_overlay(struct drm_device *dev);
748int intel_overlay_switch_off(struct intel_overlay *overlay);
749int intel_overlay_put_image(struct drm_device *dev, void *data,
750 struct drm_file *file_priv);
751int intel_overlay_attrs(struct drm_device *dev, void *data,
752 struct drm_file *file_priv);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300753
754
755/* intel_panel.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300756int intel_panel_init(struct intel_panel *panel,
757 struct drm_display_mode *fixed_mode);
758void intel_panel_fini(struct intel_panel *panel);
759void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
760 struct drm_display_mode *adjusted_mode);
761void intel_pch_panel_fitting(struct intel_crtc *crtc,
762 struct intel_crtc_config *pipe_config,
763 int fitting_mode);
764void intel_gmch_panel_fitting(struct intel_crtc *crtc,
765 struct intel_crtc_config *pipe_config,
766 int fitting_mode);
767void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max);
768int intel_panel_setup_backlight(struct drm_connector *connector);
769void intel_panel_enable_backlight(struct drm_device *dev, enum pipe pipe);
770void intel_panel_disable_backlight(struct drm_device *dev);
771void intel_panel_destroy_backlight(struct drm_device *dev);
772enum drm_connector_status intel_panel_detect(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300773
774
775/* intel_pm.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300776void intel_init_clock_gating(struct drm_device *dev);
777void intel_suspend_hw(struct drm_device *dev);
778void intel_update_watermarks(struct drm_crtc *crtc);
779void intel_update_sprite_watermarks(struct drm_plane *plane,
780 struct drm_crtc *crtc,
781 uint32_t sprite_width, int pixel_size,
782 bool enabled, bool scaled);
783void intel_init_pm(struct drm_device *dev);
784bool intel_fbc_enabled(struct drm_device *dev);
785void intel_update_fbc(struct drm_device *dev);
786void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
787void intel_gpu_ips_teardown(void);
788int i915_init_power_well(struct drm_device *dev);
789void i915_remove_power_well(struct drm_device *dev);
790bool intel_display_power_enabled(struct drm_device *dev,
791 enum intel_display_power_domain domain);
792void intel_display_power_get(struct drm_device *dev,
793 enum intel_display_power_domain domain);
794void intel_display_power_put(struct drm_device *dev,
795 enum intel_display_power_domain domain);
796void intel_init_power_well(struct drm_device *dev);
797void intel_set_power_well(struct drm_device *dev, bool enable);
Paulo Zanoni87440422013-09-24 15:48:31 -0300798void intel_enable_gt_powersave(struct drm_device *dev);
799void intel_disable_gt_powersave(struct drm_device *dev);
800void ironlake_teardown_rc6(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300801void gen6_update_ring_freq(struct drm_device *dev);
Paulo Zanoni87440422013-09-24 15:48:31 -0300802void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
803void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300804
805
806/* intel_sdvo.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300807bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300808
809
810/* intel_sprite.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300811int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
812void intel_flush_display_plane(struct drm_i915_private *dev_priv,
813 enum plane plane);
814void intel_plane_restore(struct drm_plane *plane);
815void intel_plane_disable(struct drm_plane *plane);
816int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
817 struct drm_file *file_priv);
818int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
819 struct drm_file *file_priv);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300820
821
822/* intel_tv.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300823void intel_tv_init(struct drm_device *dev);
Ville Syrjälä20ddf662013-09-04 18:25:25 +0300824
Chris Wilsonb29c19b2013-09-25 17:34:56 +0100825void gen6_rps_idle(struct drm_i915_private *dev_priv);
826void gen6_rps_boost(struct drm_i915_private *dev_priv);
827
Jesse Barnes79e53942008-11-07 14:24:08 -0800828#endif /* __INTEL_DRV_H__ */