blob: ddf287f52d498dd5bfe6d5451e019f64dda6f20c [file] [log] [blame]
Marc Dietrichcc2afa42011-11-01 10:37:05 +00001/dts-v1/;
2
Marc Dietrichcc2afa42011-11-01 10:37:05 +00003/include/ "tegra20.dtsi"
4
5/ {
6 model = "Toshiba AC100 / Dynabook AZ";
7 compatible = "compal,paz00", "nvidia,tegra20";
8
Stephen Warrenf9eb26a2012-05-11 16:17:47 -06009 memory {
Marc Dietrichcc2afa42011-11-01 10:37:05 +000010 reg = <0x00000000 0x20000000>;
11 };
12
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060013 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060014 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata", "atc", "atd", "ate",
20 "dap2", "gmb", "gmc", "gmd", "spia",
21 "spib", "spic", "spid", "spie";
22 nvidia,function = "gmi";
23 };
24 atb {
25 nvidia,pins = "atb", "gma", "gme";
26 nvidia,function = "sdio4";
27 };
28 cdev1 {
29 nvidia,pins = "cdev1";
30 nvidia,function = "plla_out";
31 };
32 cdev2 {
33 nvidia,pins = "cdev2";
34 nvidia,function = "pllp_out4";
35 };
36 crtp {
37 nvidia,pins = "crtp";
38 nvidia,function = "crt";
39 };
40 csus {
41 nvidia,pins = "csus";
42 nvidia,function = "pllc_out1";
43 };
44 dap1 {
45 nvidia,pins = "dap1";
46 nvidia,function = "dap1";
47 };
48 dap3 {
49 nvidia,pins = "dap3";
50 nvidia,function = "dap3";
51 };
52 dap4 {
53 nvidia,pins = "dap4";
54 nvidia,function = "dap4";
55 };
56 ddc {
57 nvidia,pins = "ddc";
58 nvidia,function = "i2c2";
59 };
60 dta {
61 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
62 nvidia,function = "rsvd1";
63 };
64 dtf {
65 nvidia,pins = "dtf";
66 nvidia,function = "i2c3";
67 };
68 gpu {
69 nvidia,pins = "gpu", "sdb", "sdd";
70 nvidia,function = "pwm";
71 };
72 gpu7 {
73 nvidia,pins = "gpu7";
74 nvidia,function = "rtck";
75 };
76 gpv {
77 nvidia,pins = "gpv", "slxa", "slxk";
78 nvidia,function = "pcie";
79 };
80 hdint {
81 nvidia,pins = "hdint", "pta";
82 nvidia,function = "hdmi";
83 };
84 i2cp {
85 nvidia,pins = "i2cp";
86 nvidia,function = "i2cp";
87 };
88 irrx {
89 nvidia,pins = "irrx", "irtx";
90 nvidia,function = "uarta";
91 };
92 kbca {
93 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
94 nvidia,function = "kbc";
95 };
96 kbcb {
97 nvidia,pins = "kbcb", "kbcd";
98 nvidia,function = "sdio2";
99 };
100 lcsn {
101 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
102 "ld3", "ld4", "ld5", "ld6", "ld7",
103 "ld8", "ld9", "ld10", "ld11", "ld12",
104 "ld13", "ld14", "ld15", "ld16", "ld17",
105 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
106 "lhs", "lm0", "lm1", "lpp", "lpw0",
107 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
108 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
109 "lvs";
110 nvidia,function = "displaya";
111 };
112 owc {
113 nvidia,pins = "owc";
114 nvidia,function = "owr";
115 };
116 pmc {
117 nvidia,pins = "pmc";
118 nvidia,function = "pwr_on";
119 };
120 rm {
121 nvidia,pins = "rm";
122 nvidia,function = "i2c1";
123 };
124 sdc {
125 nvidia,pins = "sdc";
126 nvidia,function = "twc";
127 };
128 sdio1 {
129 nvidia,pins = "sdio1";
130 nvidia,function = "sdio1";
131 };
132 slxc {
133 nvidia,pins = "slxc", "slxd";
134 nvidia,function = "spi4";
135 };
136 spdi {
137 nvidia,pins = "spdi", "spdo";
138 nvidia,function = "rsvd2";
139 };
140 spif {
141 nvidia,pins = "spif", "uac";
142 nvidia,function = "rsvd4";
143 };
144 spig {
145 nvidia,pins = "spig", "spih";
146 nvidia,function = "spi2_alt";
147 };
148 uaa {
149 nvidia,pins = "uaa", "uab", "uda";
150 nvidia,function = "ulpi";
151 };
152 uad {
153 nvidia,pins = "uad";
154 nvidia,function = "spdif";
155 };
156 uca {
157 nvidia,pins = "uca", "ucb";
158 nvidia,function = "uartc";
159 };
160 conf_ata {
161 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600162 "cdev1", "cdev2", "dap1", "dap2", "dtf",
163 "gma", "gmb", "gmc", "gmd", "gme",
164 "gpu", "gpu7", "gpv", "i2cp", "pta",
165 "rm", "sdio1", "slxk", "spdo", "uac",
166 "uda";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600167 nvidia,pull = <0>;
168 nvidia,tristate = <0>;
169 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600170 conf_ck32 {
171 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
172 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
173 nvidia,pull = <0>;
174 };
175 conf_crtp {
176 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
177 "dtc", "dte", "slxa", "slxc", "slxd",
178 "spdi";
179 nvidia,pull = <0>;
180 nvidia,tristate = <1>;
181 };
182 conf_csus {
183 nvidia,pins = "csus", "spia", "spib", "spid",
184 "spif";
185 nvidia,pull = <1>;
186 nvidia,tristate = <1>;
187 };
188 conf_ddc {
189 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
190 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
191 "spic", "spig", "uaa", "uab";
192 nvidia,pull = <2>;
193 nvidia,tristate = <0>;
194 };
195 conf_dta {
196 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
197 "spie", "spih", "uad", "uca", "ucb";
198 nvidia,pull = <2>;
199 nvidia,tristate = <1>;
200 };
201 conf_hdint {
202 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
203 "ld3", "ld4", "ld5", "ld6", "ld7",
204 "ld8", "ld9", "ld10", "ld11", "ld12",
205 "ld13", "ld14", "ld15", "ld16", "ld17",
206 "ldc", "ldi", "lhs", "lsc0", "lspi",
207 "lvs", "pmc";
208 nvidia,tristate = <0>;
209 };
210 conf_lc {
211 nvidia,pins = "lc", "ls";
212 nvidia,pull = <2>;
213 };
214 conf_lcsn {
215 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
216 "lm0", "lm1", "lpp", "lpw0", "lpw1",
217 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
218 "lvp0", "lvp1", "sdb";
219 nvidia,tristate = <1>;
220 };
221 conf_ld17_0 {
222 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
223 "ld23_22";
224 nvidia,pull = <1>;
225 };
226 };
227 };
228
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600229 i2s@70002800 {
230 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600231 };
232
233 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600234 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600235 clock-frequency = <216000000>;
236 };
237
Stephen Warrenc04abb32012-05-11 17:03:26 -0600238 serial@70006200 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600239 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600240 clock-frequency = <216000000>;
241 };
242
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000243 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600244 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000245 clock-frequency = <400000>;
Leon Romanovsky613e9652012-02-02 22:13:35 +0200246
247 alc5632: alc5632@1e {
248 compatible = "realtek,alc5632";
249 reg = <0x1e>;
250 gpio-controller;
251 #gpio-cells = <2>;
252 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000253 };
254
255 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600256 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000257 clock-frequency = <400000>;
258 };
259
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600260 nvec {
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000261 compatible = "nvidia,nvec";
Stephen Warrenba04c282012-05-11 16:28:59 -0600262 reg = <0x7000c500 0x100>;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700263 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600264 #address-cells = <1>;
265 #size-cells = <0>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000266 clock-frequency = <80000>;
Stephen Warrenc44e4382012-05-11 16:21:10 -0600267 request-gpios = <&gpio 170 0>; /* gpio PV2 */
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000268 slave-addr = <138>;
269 };
270
271 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600272 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000273 clock-frequency = <400000>;
Marc Dietrich1266f892012-01-31 19:53:21 +0100274
Stephen Warren217b8f02012-06-21 14:24:57 -0600275 pmic: tps6586x@34 {
276 compatible = "ti,tps6586x";
277 reg = <0x34>;
278 interrupts = <0 86 0x4>;
279
280 #gpio-cells = <2>;
281 gpio-controller;
282
283 sys-supply = <&p5valw_reg>;
284 vin-sm0-supply = <&sys_reg>;
285 vin-sm1-supply = <&sys_reg>;
286 vin-sm2-supply = <&sys_reg>;
287 vinldo01-supply = <&sm2_reg>;
288 vinldo23-supply = <&sm2_reg>;
289 vinldo4-supply = <&sm2_reg>;
290 vinldo678-supply = <&sm2_reg>;
291 vinldo9-supply = <&sm2_reg>;
292
293 regulators {
294 #address-cells = <1>;
295 #size-cells = <0>;
296
297 sys_reg: regulator@0 {
298 reg = <0>;
299 regulator-compatible = "sys";
300 regulator-name = "vdd_sys";
301 regulator-always-on;
302 };
303
304 regulator@1 {
305 reg = <1>;
306 regulator-compatible = "sm0";
307 regulator-name = "+1.2vs_sm0,vdd_core";
308 regulator-min-microvolt = <1200000>;
309 regulator-max-microvolt = <1200000>;
310 regulator-always-on;
311 };
312
313 regulator@2 {
314 reg = <2>;
315 regulator-compatible = "sm1";
316 regulator-name = "+1.0vs_sm1,vdd_cpu";
317 regulator-min-microvolt = <1000000>;
318 regulator-max-microvolt = <1000000>;
319 regulator-always-on;
320 };
321
322 sm2_reg: regulator@3 {
323 reg = <3>;
324 regulator-compatible = "sm2";
325 regulator-name = "+3.7vs_sm2,vin_ldo*";
326 regulator-min-microvolt = <3700000>;
327 regulator-max-microvolt = <3700000>;
328 regulator-always-on;
329 };
330
331 /* LDO0 is not connected to anything */
332
333 regulator@5 {
334 reg = <5>;
335 regulator-compatible = "ldo1";
336 regulator-name = "+1.1vs_ldo1,avdd_pll*";
337 regulator-min-microvolt = <1100000>;
338 regulator-max-microvolt = <1100000>;
339 regulator-always-on;
340 };
341
342 regulator@6 {
343 reg = <6>;
344 regulator-compatible = "ldo2";
345 regulator-name = "+1.2vs_ldo2,vdd_rtc";
346 regulator-min-microvolt = <1200000>;
347 regulator-max-microvolt = <1200000>;
348 };
349
350 regulator@7 {
351 reg = <7>;
352 regulator-compatible = "ldo3";
353 regulator-name = "+3.3vs_ldo3,avdd_usb*";
354 regulator-min-microvolt = <3300000>;
355 regulator-max-microvolt = <3300000>;
356 regulator-always-on;
357 };
358
359 regulator@8 {
360 reg = <8>;
361 regulator-compatible = "ldo4";
362 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
363 regulator-min-microvolt = <1800000>;
364 regulator-max-microvolt = <1800000>;
365 regulator-always-on;
366 };
367
368 regulator@9 {
369 reg = <9>;
370 regulator-compatible = "ldo5";
371 regulator-name = "+2.85vs_ldo5,vcore_mmc";
372 regulator-min-microvolt = <2850000>;
373 regulator-max-microvolt = <2850000>;
374 regulator-always-on;
375 };
376
377 regulator@10 {
378 reg = <10>;
379 regulator-compatible = "ldo6";
380 /*
381 * Research indicates this should be
382 * 1.8v; other boards that use this
383 * rail for the same purpose need it
384 * set to 1.8v. The schematic signal
385 * name is incorrect; perhaps copied
386 * from an incorrect NVIDIA reference.
387 */
388 regulator-name = "+2.85vs_ldo6,avdd_vdac";
389 regulator-min-microvolt = <1800000>;
390 regulator-max-microvolt = <1800000>;
391 };
392
393 regulator@11 {
394 reg = <11>;
395 regulator-compatible = "ldo7";
396 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
397 regulator-min-microvolt = <3300000>;
398 regulator-max-microvolt = <3300000>;
399 };
400
401 regulator@12 {
402 reg = <12>;
403 regulator-compatible = "ldo8";
404 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
405 regulator-min-microvolt = <1800000>;
406 regulator-max-microvolt = <1800000>;
407 };
408
409 regulator@13 {
410 reg = <13>;
411 regulator-compatible = "ldo9";
412 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
413 regulator-min-microvolt = <2850000>;
414 regulator-max-microvolt = <2850000>;
415 regulator-always-on;
416 };
417
418 regulator@14 {
419 reg = <14>;
420 regulator-compatible = "ldo_rtc";
421 regulator-name = "+3.3vs_rtc";
422 regulator-min-microvolt = <3300000>;
423 regulator-max-microvolt = <3300000>;
424 regulator-always-on;
425 };
426 };
427 };
428
Marc Dietrich1266f892012-01-31 19:53:21 +0100429 adt7461@4c {
430 compatible = "adi,adt7461";
431 reg = <0x4c>;
432 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000433 };
434
Stephen Warren217b8f02012-06-21 14:24:57 -0600435 pmc {
436 nvidia,invert-interrupt;
437 };
438
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600439 usb@c5000000 {
440 status = "okay";
441 };
442
Stephen Warrenc04abb32012-05-11 17:03:26 -0600443 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600444 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600445 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000446 };
447
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600448 usb@c5008000 {
449 status = "okay";
450 };
451
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000452 sdhci@c8000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600453 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000454 cd-gpios = <&gpio 173 0>; /* gpio PV5 */
455 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
Marc Dietrich5f21f122012-01-28 20:03:04 +0100456 power-gpios = <&gpio 169 0>; /* gpio PV1 */
Arnd Bergmann7f217792012-05-13 00:14:24 -0400457 bus-width = <4>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000458 };
459
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000460 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600461 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400462 bus-width = <8>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000463 };
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100464
465 gpio-keys {
466 compatible = "gpio-keys";
467
468 power {
469 label = "Power";
470 gpios = <&gpio 79 1>; /* gpio PJ7, active low */
471 linux,code = <116>; /* KEY_POWER */
472 gpio-key,wakeup;
473 };
474 };
Marc Dietrich80c94732012-01-28 20:03:08 +0100475
476 gpio-leds {
477 compatible = "gpio-leds";
478
479 wifi {
480 label = "wifi-led";
Stephen Warrenc44e4382012-05-11 16:21:10 -0600481 gpios = <&gpio 24 0>; /* gpio PD0 */
Marc Dietrich80c94732012-01-28 20:03:08 +0100482 linux,default-trigger = "rfkill0";
483 };
484 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600485
Stephen Warren217b8f02012-06-21 14:24:57 -0600486 regulators {
487 compatible = "simple-bus";
488 #address-cells = <1>;
489 #size-cells = <0>;
490
491 p5valw_reg: regulator@0 {
492 compatible = "regulator-fixed";
493 reg = <0>;
494 regulator-name = "+5valw";
495 regulator-min-microvolt = <5000000>;
496 regulator-max-microvolt = <5000000>;
497 regulator-always-on;
498 };
499 };
500
Stephen Warrenc04abb32012-05-11 17:03:26 -0600501 sound {
502 compatible = "nvidia,tegra-audio-alc5632-paz00",
503 "nvidia,tegra-audio-alc5632";
504
505 nvidia,model = "Compal PAZ00";
506
507 nvidia,audio-routing =
508 "Int Spk", "SPKOUT",
509 "Int Spk", "SPKOUTN",
510 "Headset Mic", "MICBIAS1",
511 "MIC1", "Headset Mic",
512 "Headset Stereophone", "HPR",
513 "Headset Stereophone", "HPL",
514 "DMICDAT", "Digital Mic";
515
516 nvidia,audio-codec = <&alc5632>;
517 nvidia,i2s-controller = <&tegra_i2s1>;
518 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600519 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000520};