Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #include <linux/seq_file.h> |
| 29 | #include "drmP.h" |
| 30 | #include "drm.h" |
| 31 | #include "radeon_drm.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 32 | #include "radeon_reg.h" |
| 33 | #include "radeon.h" |
Daniel Vetter | e699037 | 2010-03-11 21:19:17 +0000 | [diff] [blame] | 34 | #include "radeon_asic.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 35 | #include "r100d.h" |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 36 | #include "rs100d.h" |
| 37 | #include "rv200d.h" |
| 38 | #include "rv250d.h" |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 39 | |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 40 | #include <linux/firmware.h> |
| 41 | #include <linux/platform_device.h> |
| 42 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 43 | #include "r100_reg_safe.h" |
| 44 | #include "rn50_reg_safe.h" |
| 45 | |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 46 | /* Firmware Names */ |
| 47 | #define FIRMWARE_R100 "radeon/R100_cp.bin" |
| 48 | #define FIRMWARE_R200 "radeon/R200_cp.bin" |
| 49 | #define FIRMWARE_R300 "radeon/R300_cp.bin" |
| 50 | #define FIRMWARE_R420 "radeon/R420_cp.bin" |
| 51 | #define FIRMWARE_RS690 "radeon/RS690_cp.bin" |
| 52 | #define FIRMWARE_RS600 "radeon/RS600_cp.bin" |
| 53 | #define FIRMWARE_R520 "radeon/R520_cp.bin" |
| 54 | |
| 55 | MODULE_FIRMWARE(FIRMWARE_R100); |
| 56 | MODULE_FIRMWARE(FIRMWARE_R200); |
| 57 | MODULE_FIRMWARE(FIRMWARE_R300); |
| 58 | MODULE_FIRMWARE(FIRMWARE_R420); |
| 59 | MODULE_FIRMWARE(FIRMWARE_RS690); |
| 60 | MODULE_FIRMWARE(FIRMWARE_RS600); |
| 61 | MODULE_FIRMWARE(FIRMWARE_R520); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 62 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 63 | #include "r100_track.h" |
| 64 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 65 | /* This files gather functions specifics to: |
| 66 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 67 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 68 | |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 69 | /* hpd for digital panel detect/disconnect */ |
| 70 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
| 71 | { |
| 72 | bool connected = false; |
| 73 | |
| 74 | switch (hpd) { |
| 75 | case RADEON_HPD_1: |
| 76 | if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) |
| 77 | connected = true; |
| 78 | break; |
| 79 | case RADEON_HPD_2: |
| 80 | if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) |
| 81 | connected = true; |
| 82 | break; |
| 83 | default: |
| 84 | break; |
| 85 | } |
| 86 | return connected; |
| 87 | } |
| 88 | |
| 89 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
| 90 | enum radeon_hpd_id hpd) |
| 91 | { |
| 92 | u32 tmp; |
| 93 | bool connected = r100_hpd_sense(rdev, hpd); |
| 94 | |
| 95 | switch (hpd) { |
| 96 | case RADEON_HPD_1: |
| 97 | tmp = RREG32(RADEON_FP_GEN_CNTL); |
| 98 | if (connected) |
| 99 | tmp &= ~RADEON_FP_DETECT_INT_POL; |
| 100 | else |
| 101 | tmp |= RADEON_FP_DETECT_INT_POL; |
| 102 | WREG32(RADEON_FP_GEN_CNTL, tmp); |
| 103 | break; |
| 104 | case RADEON_HPD_2: |
| 105 | tmp = RREG32(RADEON_FP2_GEN_CNTL); |
| 106 | if (connected) |
| 107 | tmp &= ~RADEON_FP2_DETECT_INT_POL; |
| 108 | else |
| 109 | tmp |= RADEON_FP2_DETECT_INT_POL; |
| 110 | WREG32(RADEON_FP2_GEN_CNTL, tmp); |
| 111 | break; |
| 112 | default: |
| 113 | break; |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | void r100_hpd_init(struct radeon_device *rdev) |
| 118 | { |
| 119 | struct drm_device *dev = rdev->ddev; |
| 120 | struct drm_connector *connector; |
| 121 | |
| 122 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 123 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 124 | switch (radeon_connector->hpd.hpd) { |
| 125 | case RADEON_HPD_1: |
| 126 | rdev->irq.hpd[0] = true; |
| 127 | break; |
| 128 | case RADEON_HPD_2: |
| 129 | rdev->irq.hpd[1] = true; |
| 130 | break; |
| 131 | default: |
| 132 | break; |
| 133 | } |
| 134 | } |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 135 | if (rdev->irq.installed) |
| 136 | r100_irq_set(rdev); |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | void r100_hpd_fini(struct radeon_device *rdev) |
| 140 | { |
| 141 | struct drm_device *dev = rdev->ddev; |
| 142 | struct drm_connector *connector; |
| 143 | |
| 144 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 145 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 146 | switch (radeon_connector->hpd.hpd) { |
| 147 | case RADEON_HPD_1: |
| 148 | rdev->irq.hpd[0] = false; |
| 149 | break; |
| 150 | case RADEON_HPD_2: |
| 151 | rdev->irq.hpd[1] = false; |
| 152 | break; |
| 153 | default: |
| 154 | break; |
| 155 | } |
| 156 | } |
| 157 | } |
| 158 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 159 | /* |
| 160 | * PCI GART |
| 161 | */ |
| 162 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev) |
| 163 | { |
| 164 | /* TODO: can we do somethings here ? */ |
| 165 | /* It seems hw only cache one entry so we should discard this |
| 166 | * entry otherwise if first GPU GART read hit this entry it |
| 167 | * could end up in wrong address. */ |
| 168 | } |
| 169 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 170 | int r100_pci_gart_init(struct radeon_device *rdev) |
| 171 | { |
| 172 | int r; |
| 173 | |
| 174 | if (rdev->gart.table.ram.ptr) { |
| 175 | WARN(1, "R100 PCI GART already initialized.\n"); |
| 176 | return 0; |
| 177 | } |
| 178 | /* Initialize common gart structure */ |
| 179 | r = radeon_gart_init(rdev); |
| 180 | if (r) |
| 181 | return r; |
| 182 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
| 183 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; |
| 184 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; |
| 185 | return radeon_gart_table_ram_alloc(rdev); |
| 186 | } |
| 187 | |
Dave Airlie | 17e15b0 | 2009-11-05 15:36:53 +1000 | [diff] [blame] | 188 | /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
| 189 | void r100_enable_bm(struct radeon_device *rdev) |
| 190 | { |
| 191 | uint32_t tmp; |
| 192 | /* Enable bus mastering */ |
| 193 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
| 194 | WREG32(RADEON_BUS_CNTL, tmp); |
| 195 | } |
| 196 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 197 | int r100_pci_gart_enable(struct radeon_device *rdev) |
| 198 | { |
| 199 | uint32_t tmp; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 200 | |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 201 | radeon_gart_restore(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 202 | /* discard memory request outside of configured range */ |
| 203 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
| 204 | WREG32(RADEON_AIC_CNTL, tmp); |
| 205 | /* set address range for PCI address translate */ |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 206 | WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); |
| 207 | WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 208 | /* set PCI GART page-table base address */ |
| 209 | WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); |
| 210 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; |
| 211 | WREG32(RADEON_AIC_CNTL, tmp); |
| 212 | r100_pci_gart_tlb_flush(rdev); |
| 213 | rdev->gart.ready = true; |
| 214 | return 0; |
| 215 | } |
| 216 | |
| 217 | void r100_pci_gart_disable(struct radeon_device *rdev) |
| 218 | { |
| 219 | uint32_t tmp; |
| 220 | |
| 221 | /* discard memory request outside of configured range */ |
| 222 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
| 223 | WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
| 224 | WREG32(RADEON_AIC_LO_ADDR, 0); |
| 225 | WREG32(RADEON_AIC_HI_ADDR, 0); |
| 226 | } |
| 227 | |
| 228 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
| 229 | { |
| 230 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
| 231 | return -EINVAL; |
| 232 | } |
Dave Airlie | ed10f95 | 2009-06-29 18:29:11 +1000 | [diff] [blame] | 233 | rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 234 | return 0; |
| 235 | } |
| 236 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 237 | void r100_pci_gart_fini(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 238 | { |
Jerome Glisse | f927456 | 2010-03-17 14:44:29 +0000 | [diff] [blame] | 239 | radeon_gart_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 240 | r100_pci_gart_disable(rdev); |
| 241 | radeon_gart_table_ram_free(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 242 | } |
| 243 | |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 244 | int r100_irq_set(struct radeon_device *rdev) |
| 245 | { |
| 246 | uint32_t tmp = 0; |
| 247 | |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 248 | if (!rdev->irq.installed) { |
| 249 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); |
| 250 | WREG32(R_000040_GEN_INT_CNTL, 0); |
| 251 | return -EINVAL; |
| 252 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 253 | if (rdev->irq.sw_int) { |
| 254 | tmp |= RADEON_SW_INT_ENABLE; |
| 255 | } |
| 256 | if (rdev->irq.crtc_vblank_int[0]) { |
| 257 | tmp |= RADEON_CRTC_VBLANK_MASK; |
| 258 | } |
| 259 | if (rdev->irq.crtc_vblank_int[1]) { |
| 260 | tmp |= RADEON_CRTC2_VBLANK_MASK; |
| 261 | } |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 262 | if (rdev->irq.hpd[0]) { |
| 263 | tmp |= RADEON_FP_DETECT_MASK; |
| 264 | } |
| 265 | if (rdev->irq.hpd[1]) { |
| 266 | tmp |= RADEON_FP2_DETECT_MASK; |
| 267 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 268 | WREG32(RADEON_GEN_INT_CNTL, tmp); |
| 269 | return 0; |
| 270 | } |
| 271 | |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 272 | void r100_irq_disable(struct radeon_device *rdev) |
| 273 | { |
| 274 | u32 tmp; |
| 275 | |
| 276 | WREG32(R_000040_GEN_INT_CNTL, 0); |
| 277 | /* Wait and acknowledge irq */ |
| 278 | mdelay(1); |
| 279 | tmp = RREG32(R_000044_GEN_INT_STATUS); |
| 280 | WREG32(R_000044_GEN_INT_STATUS, tmp); |
| 281 | } |
| 282 | |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 283 | static inline uint32_t r100_irq_ack(struct radeon_device *rdev) |
| 284 | { |
| 285 | uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 286 | uint32_t irq_mask = RADEON_SW_INT_TEST | |
| 287 | RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | |
| 288 | RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 289 | |
| 290 | if (irqs) { |
| 291 | WREG32(RADEON_GEN_INT_STATUS, irqs); |
| 292 | } |
| 293 | return irqs & irq_mask; |
| 294 | } |
| 295 | |
| 296 | int r100_irq_process(struct radeon_device *rdev) |
| 297 | { |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 298 | uint32_t status, msi_rearm; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 299 | bool queue_hotplug = false; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 300 | |
| 301 | status = r100_irq_ack(rdev); |
| 302 | if (!status) { |
| 303 | return IRQ_NONE; |
| 304 | } |
Jerome Glisse | a513c18 | 2009-09-09 22:23:07 +0200 | [diff] [blame] | 305 | if (rdev->shutdown) { |
| 306 | return IRQ_NONE; |
| 307 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 308 | while (status) { |
| 309 | /* SW interrupt */ |
| 310 | if (status & RADEON_SW_INT_TEST) { |
| 311 | radeon_fence_process(rdev); |
| 312 | } |
| 313 | /* Vertical blank interrupts */ |
| 314 | if (status & RADEON_CRTC_VBLANK_STAT) { |
| 315 | drm_handle_vblank(rdev->ddev, 0); |
Rafał Miłecki | 839461d | 2010-03-02 22:06:51 +0100 | [diff] [blame] | 316 | rdev->pm.vblank_sync = true; |
Rafał Miłecki | 73a6d3f | 2010-01-08 00:22:47 +0100 | [diff] [blame] | 317 | wake_up(&rdev->irq.vblank_queue); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 318 | } |
| 319 | if (status & RADEON_CRTC2_VBLANK_STAT) { |
| 320 | drm_handle_vblank(rdev->ddev, 1); |
Rafał Miłecki | 839461d | 2010-03-02 22:06:51 +0100 | [diff] [blame] | 321 | rdev->pm.vblank_sync = true; |
Rafał Miłecki | 73a6d3f | 2010-01-08 00:22:47 +0100 | [diff] [blame] | 322 | wake_up(&rdev->irq.vblank_queue); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 323 | } |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 324 | if (status & RADEON_FP_DETECT_STAT) { |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 325 | queue_hotplug = true; |
| 326 | DRM_DEBUG("HPD1\n"); |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 327 | } |
| 328 | if (status & RADEON_FP2_DETECT_STAT) { |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 329 | queue_hotplug = true; |
| 330 | DRM_DEBUG("HPD2\n"); |
Alex Deucher | 05a05c5 | 2009-12-04 14:53:41 -0500 | [diff] [blame] | 331 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 332 | status = r100_irq_ack(rdev); |
| 333 | } |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 334 | if (queue_hotplug) |
| 335 | queue_work(rdev->wq, &rdev->hotplug_work); |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 336 | if (rdev->msi_enabled) { |
| 337 | switch (rdev->family) { |
| 338 | case CHIP_RS400: |
| 339 | case CHIP_RS480: |
| 340 | msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; |
| 341 | WREG32(RADEON_AIC_CNTL, msi_rearm); |
| 342 | WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); |
| 343 | break; |
| 344 | default: |
| 345 | msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; |
| 346 | WREG32(RADEON_MSI_REARM_EN, msi_rearm); |
| 347 | WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); |
| 348 | break; |
| 349 | } |
| 350 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 351 | return IRQ_HANDLED; |
| 352 | } |
| 353 | |
| 354 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) |
| 355 | { |
| 356 | if (crtc == 0) |
| 357 | return RREG32(RADEON_CRTC_CRNT_FRAME); |
| 358 | else |
| 359 | return RREG32(RADEON_CRTC2_CRNT_FRAME); |
| 360 | } |
| 361 | |
Pauli Nieminen | 9e5b2af | 2010-02-04 19:20:53 +0200 | [diff] [blame] | 362 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
| 363 | * for enough space (today caller are ib schedule and buffer move) */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 364 | void r100_fence_ring_emit(struct radeon_device *rdev, |
| 365 | struct radeon_fence *fence) |
| 366 | { |
Pauli Nieminen | 9e5b2af | 2010-02-04 19:20:53 +0200 | [diff] [blame] | 367 | /* We have to make sure that caches are flushed before |
| 368 | * CPU might read something from VRAM. */ |
| 369 | radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); |
| 370 | radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL); |
| 371 | radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); |
| 372 | radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 373 | /* Wait until IDLE & CLEAN */ |
Alex Deucher | 4612dc9 | 2010-02-05 01:58:28 -0500 | [diff] [blame] | 374 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| 375 | radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
Jerome Glisse | cafe660 | 2010-01-07 12:39:21 +0100 | [diff] [blame] | 376 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
| 377 | radeon_ring_write(rdev, rdev->config.r100.hdp_cntl | |
| 378 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
| 379 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
| 380 | radeon_ring_write(rdev, rdev->config.r100.hdp_cntl); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 381 | /* Emit fence sequence & fire IRQ */ |
| 382 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
| 383 | radeon_ring_write(rdev, fence->seq); |
| 384 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
| 385 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
| 386 | } |
| 387 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 388 | int r100_wb_init(struct radeon_device *rdev) |
| 389 | { |
| 390 | int r; |
| 391 | |
| 392 | if (rdev->wb.wb_obj == NULL) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 393 | r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, |
| 394 | RADEON_GEM_DOMAIN_GTT, |
| 395 | &rdev->wb.wb_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 396 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 397 | dev_err(rdev->dev, "(%d) create WB buffer failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 398 | return r; |
| 399 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 400 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
| 401 | if (unlikely(r != 0)) |
| 402 | return r; |
| 403 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
| 404 | &rdev->wb.gpu_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 405 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 406 | dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r); |
| 407 | radeon_bo_unreserve(rdev->wb.wb_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 408 | return r; |
| 409 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 410 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
| 411 | radeon_bo_unreserve(rdev->wb.wb_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 412 | if (r) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 413 | dev_err(rdev->dev, "(%d) map WB buffer failed\n", r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 414 | return r; |
| 415 | } |
| 416 | } |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 417 | WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr); |
| 418 | WREG32(R_00070C_CP_RB_RPTR_ADDR, |
| 419 | S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2)); |
| 420 | WREG32(R_000770_SCRATCH_UMSK, 0xff); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 421 | return 0; |
| 422 | } |
| 423 | |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 424 | void r100_wb_disable(struct radeon_device *rdev) |
| 425 | { |
| 426 | WREG32(R_000770_SCRATCH_UMSK, 0); |
| 427 | } |
| 428 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 429 | void r100_wb_fini(struct radeon_device *rdev) |
| 430 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 431 | int r; |
| 432 | |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 433 | r100_wb_disable(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 434 | if (rdev->wb.wb_obj) { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 435 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
| 436 | if (unlikely(r != 0)) { |
| 437 | dev_err(rdev->dev, "(%d) can't finish WB\n", r); |
| 438 | return; |
| 439 | } |
| 440 | radeon_bo_kunmap(rdev->wb.wb_obj); |
| 441 | radeon_bo_unpin(rdev->wb.wb_obj); |
| 442 | radeon_bo_unreserve(rdev->wb.wb_obj); |
| 443 | radeon_bo_unref(&rdev->wb.wb_obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 444 | rdev->wb.wb = NULL; |
| 445 | rdev->wb.wb_obj = NULL; |
| 446 | } |
| 447 | } |
| 448 | |
| 449 | int r100_copy_blit(struct radeon_device *rdev, |
| 450 | uint64_t src_offset, |
| 451 | uint64_t dst_offset, |
| 452 | unsigned num_pages, |
| 453 | struct radeon_fence *fence) |
| 454 | { |
| 455 | uint32_t cur_pages; |
| 456 | uint32_t stride_bytes = PAGE_SIZE; |
| 457 | uint32_t pitch; |
| 458 | uint32_t stride_pixels; |
| 459 | unsigned ndw; |
| 460 | int num_loops; |
| 461 | int r = 0; |
| 462 | |
| 463 | /* radeon limited to 16k stride */ |
| 464 | stride_bytes &= 0x3fff; |
| 465 | /* radeon pitch is /64 */ |
| 466 | pitch = stride_bytes / 64; |
| 467 | stride_pixels = stride_bytes / 4; |
| 468 | num_loops = DIV_ROUND_UP(num_pages, 8191); |
| 469 | |
| 470 | /* Ask for enough room for blit + flush + fence */ |
| 471 | ndw = 64 + (10 * num_loops); |
| 472 | r = radeon_ring_lock(rdev, ndw); |
| 473 | if (r) { |
| 474 | DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); |
| 475 | return -EINVAL; |
| 476 | } |
| 477 | while (num_pages > 0) { |
| 478 | cur_pages = num_pages; |
| 479 | if (cur_pages > 8191) { |
| 480 | cur_pages = 8191; |
| 481 | } |
| 482 | num_pages -= cur_pages; |
| 483 | |
| 484 | /* pages are in Y direction - height |
| 485 | page width in X direction - width */ |
| 486 | radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8)); |
| 487 | radeon_ring_write(rdev, |
| 488 | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
| 489 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 490 | RADEON_GMC_SRC_CLIPPING | |
| 491 | RADEON_GMC_DST_CLIPPING | |
| 492 | RADEON_GMC_BRUSH_NONE | |
| 493 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | |
| 494 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 495 | RADEON_ROP3_S | |
| 496 | RADEON_DP_SRC_SOURCE_MEMORY | |
| 497 | RADEON_GMC_CLR_CMP_CNTL_DIS | |
| 498 | RADEON_GMC_WR_MSK_DIS); |
| 499 | radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10)); |
| 500 | radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10)); |
| 501 | radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); |
| 502 | radeon_ring_write(rdev, 0); |
| 503 | radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); |
| 504 | radeon_ring_write(rdev, num_pages); |
| 505 | radeon_ring_write(rdev, num_pages); |
| 506 | radeon_ring_write(rdev, cur_pages | (stride_pixels << 16)); |
| 507 | } |
| 508 | radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); |
| 509 | radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); |
| 510 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| 511 | radeon_ring_write(rdev, |
| 512 | RADEON_WAIT_2D_IDLECLEAN | |
| 513 | RADEON_WAIT_HOST_IDLECLEAN | |
| 514 | RADEON_WAIT_DMA_GUI_IDLE); |
| 515 | if (fence) { |
| 516 | r = radeon_fence_emit(rdev, fence); |
| 517 | } |
| 518 | radeon_ring_unlock_commit(rdev); |
| 519 | return r; |
| 520 | } |
| 521 | |
Jerome Glisse | 4560023 | 2009-09-09 22:23:45 +0200 | [diff] [blame] | 522 | static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
| 523 | { |
| 524 | unsigned i; |
| 525 | u32 tmp; |
| 526 | |
| 527 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 528 | tmp = RREG32(R_000E40_RBBM_STATUS); |
| 529 | if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { |
| 530 | return 0; |
| 531 | } |
| 532 | udelay(1); |
| 533 | } |
| 534 | return -1; |
| 535 | } |
| 536 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 537 | void r100_ring_start(struct radeon_device *rdev) |
| 538 | { |
| 539 | int r; |
| 540 | |
| 541 | r = radeon_ring_lock(rdev, 2); |
| 542 | if (r) { |
| 543 | return; |
| 544 | } |
| 545 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); |
| 546 | radeon_ring_write(rdev, |
| 547 | RADEON_ISYNC_ANY2D_IDLE3D | |
| 548 | RADEON_ISYNC_ANY3D_IDLE2D | |
| 549 | RADEON_ISYNC_WAIT_IDLEGUI | |
| 550 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
| 551 | radeon_ring_unlock_commit(rdev); |
| 552 | } |
| 553 | |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 554 | |
| 555 | /* Load the microcode for the CP */ |
| 556 | static int r100_cp_init_microcode(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 557 | { |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 558 | struct platform_device *pdev; |
| 559 | const char *fw_name = NULL; |
| 560 | int err; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 561 | |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 562 | DRM_DEBUG("\n"); |
| 563 | |
| 564 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
| 565 | err = IS_ERR(pdev); |
| 566 | if (err) { |
| 567 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); |
| 568 | return -EINVAL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 569 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 570 | if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || |
| 571 | (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || |
| 572 | (rdev->family == CHIP_RS200)) { |
| 573 | DRM_INFO("Loading R100 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 574 | fw_name = FIRMWARE_R100; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 575 | } else if ((rdev->family == CHIP_R200) || |
| 576 | (rdev->family == CHIP_RV250) || |
| 577 | (rdev->family == CHIP_RV280) || |
| 578 | (rdev->family == CHIP_RS300)) { |
| 579 | DRM_INFO("Loading R200 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 580 | fw_name = FIRMWARE_R200; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 581 | } else if ((rdev->family == CHIP_R300) || |
| 582 | (rdev->family == CHIP_R350) || |
| 583 | (rdev->family == CHIP_RV350) || |
| 584 | (rdev->family == CHIP_RV380) || |
| 585 | (rdev->family == CHIP_RS400) || |
| 586 | (rdev->family == CHIP_RS480)) { |
| 587 | DRM_INFO("Loading R300 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 588 | fw_name = FIRMWARE_R300; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 589 | } else if ((rdev->family == CHIP_R420) || |
| 590 | (rdev->family == CHIP_R423) || |
| 591 | (rdev->family == CHIP_RV410)) { |
| 592 | DRM_INFO("Loading R400 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 593 | fw_name = FIRMWARE_R420; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 594 | } else if ((rdev->family == CHIP_RS690) || |
| 595 | (rdev->family == CHIP_RS740)) { |
| 596 | DRM_INFO("Loading RS690/RS740 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 597 | fw_name = FIRMWARE_RS690; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 598 | } else if (rdev->family == CHIP_RS600) { |
| 599 | DRM_INFO("Loading RS600 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 600 | fw_name = FIRMWARE_RS600; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 601 | } else if ((rdev->family == CHIP_RV515) || |
| 602 | (rdev->family == CHIP_R520) || |
| 603 | (rdev->family == CHIP_RV530) || |
| 604 | (rdev->family == CHIP_R580) || |
| 605 | (rdev->family == CHIP_RV560) || |
| 606 | (rdev->family == CHIP_RV570)) { |
| 607 | DRM_INFO("Loading R500 Microcode\n"); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 608 | fw_name = FIRMWARE_R520; |
| 609 | } |
| 610 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 611 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 612 | platform_device_unregister(pdev); |
| 613 | if (err) { |
| 614 | printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", |
| 615 | fw_name); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 616 | } else if (rdev->me_fw->size % 8) { |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 617 | printk(KERN_ERR |
| 618 | "radeon_cp: Bogus length %zu in firmware \"%s\"\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 619 | rdev->me_fw->size, fw_name); |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 620 | err = -EINVAL; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 621 | release_firmware(rdev->me_fw); |
| 622 | rdev->me_fw = NULL; |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 623 | } |
| 624 | return err; |
| 625 | } |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 626 | |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 627 | static void r100_cp_load_microcode(struct radeon_device *rdev) |
| 628 | { |
| 629 | const __be32 *fw_data; |
| 630 | int i, size; |
| 631 | |
| 632 | if (r100_gui_wait_for_idle(rdev)) { |
| 633 | printk(KERN_WARNING "Failed to wait GUI idle while " |
| 634 | "programming pipes. Bad things might happen.\n"); |
| 635 | } |
| 636 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 637 | if (rdev->me_fw) { |
| 638 | size = rdev->me_fw->size / 4; |
| 639 | fw_data = (const __be32 *)&rdev->me_fw->data[0]; |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 640 | WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
| 641 | for (i = 0; i < size; i += 2) { |
| 642 | WREG32(RADEON_CP_ME_RAM_DATAH, |
| 643 | be32_to_cpup(&fw_data[i])); |
| 644 | WREG32(RADEON_CP_ME_RAM_DATAL, |
| 645 | be32_to_cpup(&fw_data[i + 1])); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 646 | } |
| 647 | } |
| 648 | } |
| 649 | |
| 650 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) |
| 651 | { |
| 652 | unsigned rb_bufsz; |
| 653 | unsigned rb_blksz; |
| 654 | unsigned max_fetch; |
| 655 | unsigned pre_write_timer; |
| 656 | unsigned pre_write_limit; |
| 657 | unsigned indirect2_start; |
| 658 | unsigned indirect1_start; |
| 659 | uint32_t tmp; |
| 660 | int r; |
| 661 | |
| 662 | if (r100_debugfs_cp_init(rdev)) { |
| 663 | DRM_ERROR("Failed to register debugfs file for CP !\n"); |
| 664 | } |
| 665 | /* Reset CP */ |
| 666 | tmp = RREG32(RADEON_CP_CSQ_STAT); |
| 667 | if ((tmp & (1 << 31))) { |
| 668 | DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp); |
| 669 | WREG32(RADEON_CP_CSQ_MODE, 0); |
| 670 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
| 671 | WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP); |
| 672 | tmp = RREG32(RADEON_RBBM_SOFT_RESET); |
| 673 | mdelay(2); |
| 674 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
| 675 | tmp = RREG32(RADEON_RBBM_SOFT_RESET); |
| 676 | mdelay(2); |
| 677 | tmp = RREG32(RADEON_CP_CSQ_STAT); |
| 678 | if ((tmp & (1 << 31))) { |
| 679 | DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp); |
| 680 | } |
| 681 | } else { |
| 682 | DRM_INFO("radeon: cp idle (0x%08X)\n", tmp); |
| 683 | } |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 684 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 685 | if (!rdev->me_fw) { |
Ben Hutchings | 70967ab | 2009-08-29 14:53:51 +0100 | [diff] [blame] | 686 | r = r100_cp_init_microcode(rdev); |
| 687 | if (r) { |
| 688 | DRM_ERROR("Failed to load firmware!\n"); |
| 689 | return r; |
| 690 | } |
| 691 | } |
| 692 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 693 | /* Align ring size */ |
| 694 | rb_bufsz = drm_order(ring_size / 8); |
| 695 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
| 696 | r100_cp_load_microcode(rdev); |
| 697 | r = radeon_ring_init(rdev, ring_size); |
| 698 | if (r) { |
| 699 | return r; |
| 700 | } |
| 701 | /* Each time the cp read 1024 bytes (16 dword/quadword) update |
| 702 | * the rptr copy in system ram */ |
| 703 | rb_blksz = 9; |
| 704 | /* cp will read 128bytes at a time (4 dwords) */ |
| 705 | max_fetch = 1; |
| 706 | rdev->cp.align_mask = 16 - 1; |
| 707 | /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ |
| 708 | pre_write_timer = 64; |
| 709 | /* Force CP_RB_WPTR write if written more than one time before the |
| 710 | * delay expire |
| 711 | */ |
| 712 | pre_write_limit = 0; |
| 713 | /* Setup the cp cache like this (cache size is 96 dwords) : |
| 714 | * RING 0 to 15 |
| 715 | * INDIRECT1 16 to 79 |
| 716 | * INDIRECT2 80 to 95 |
| 717 | * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
| 718 | * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) |
| 719 | * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
| 720 | * Idea being that most of the gpu cmd will be through indirect1 buffer |
| 721 | * so it gets the bigger cache. |
| 722 | */ |
| 723 | indirect2_start = 80; |
| 724 | indirect1_start = 16; |
| 725 | /* cp setup */ |
| 726 | WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); |
Alex Deucher | d6f2893 | 2009-11-02 16:01:27 -0500 | [diff] [blame] | 727 | tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 728 | REG_SET(RADEON_RB_BLKSZ, rb_blksz) | |
| 729 | REG_SET(RADEON_MAX_FETCH, max_fetch) | |
| 730 | RADEON_RB_NO_UPDATE); |
Alex Deucher | d6f2893 | 2009-11-02 16:01:27 -0500 | [diff] [blame] | 731 | #ifdef __BIG_ENDIAN |
| 732 | tmp |= RADEON_BUF_SWAP_32BIT; |
| 733 | #endif |
| 734 | WREG32(RADEON_CP_RB_CNTL, tmp); |
| 735 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 736 | /* Set ring address */ |
| 737 | DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr); |
| 738 | WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr); |
| 739 | /* Force read & write ptr to 0 */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 740 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
| 741 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
| 742 | WREG32(RADEON_CP_RB_WPTR, 0); |
| 743 | WREG32(RADEON_CP_RB_CNTL, tmp); |
| 744 | udelay(10); |
| 745 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); |
| 746 | rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR); |
Dave Airlie | 9e5786b | 2010-03-31 13:38:56 +1000 | [diff] [blame] | 747 | /* protect against crazy HW on resume */ |
| 748 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 749 | /* Set cp mode to bus mastering & enable cp*/ |
| 750 | WREG32(RADEON_CP_CSQ_MODE, |
| 751 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | |
| 752 | REG_SET(RADEON_INDIRECT1_START, indirect1_start)); |
| 753 | WREG32(0x718, 0); |
| 754 | WREG32(0x744, 0x00004D4D); |
| 755 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
| 756 | radeon_ring_start(rdev); |
| 757 | r = radeon_ring_test(rdev); |
| 758 | if (r) { |
| 759 | DRM_ERROR("radeon: cp isn't working (%d).\n", r); |
| 760 | return r; |
| 761 | } |
| 762 | rdev->cp.ready = true; |
| 763 | return 0; |
| 764 | } |
| 765 | |
| 766 | void r100_cp_fini(struct radeon_device *rdev) |
| 767 | { |
Jerome Glisse | 4560023 | 2009-09-09 22:23:45 +0200 | [diff] [blame] | 768 | if (r100_cp_wait_for_idle(rdev)) { |
| 769 | DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); |
| 770 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 771 | /* Disable ring */ |
Jerome Glisse | a18d7ea | 2009-09-09 22:23:27 +0200 | [diff] [blame] | 772 | r100_cp_disable(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 773 | radeon_ring_fini(rdev); |
| 774 | DRM_INFO("radeon: cp finalized\n"); |
| 775 | } |
| 776 | |
| 777 | void r100_cp_disable(struct radeon_device *rdev) |
| 778 | { |
| 779 | /* Disable ring */ |
| 780 | rdev->cp.ready = false; |
| 781 | WREG32(RADEON_CP_CSQ_MODE, 0); |
| 782 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
| 783 | if (r100_gui_wait_for_idle(rdev)) { |
| 784 | printk(KERN_WARNING "Failed to wait GUI idle while " |
| 785 | "programming pipes. Bad things might happen.\n"); |
| 786 | } |
| 787 | } |
| 788 | |
| 789 | int r100_cp_reset(struct radeon_device *rdev) |
| 790 | { |
| 791 | uint32_t tmp; |
| 792 | bool reinit_cp; |
| 793 | int i; |
| 794 | |
| 795 | reinit_cp = rdev->cp.ready; |
| 796 | rdev->cp.ready = false; |
| 797 | WREG32(RADEON_CP_CSQ_MODE, 0); |
| 798 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
| 799 | WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP); |
| 800 | (void)RREG32(RADEON_RBBM_SOFT_RESET); |
| 801 | udelay(200); |
| 802 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
| 803 | /* Wait to prevent race in RBBM_STATUS */ |
| 804 | mdelay(1); |
| 805 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 806 | tmp = RREG32(RADEON_RBBM_STATUS); |
| 807 | if (!(tmp & (1 << 16))) { |
| 808 | DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n", |
| 809 | tmp); |
| 810 | if (reinit_cp) { |
| 811 | return r100_cp_init(rdev, rdev->cp.ring_size); |
| 812 | } |
| 813 | return 0; |
| 814 | } |
| 815 | DRM_UDELAY(1); |
| 816 | } |
| 817 | tmp = RREG32(RADEON_RBBM_STATUS); |
| 818 | DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp); |
| 819 | return -1; |
| 820 | } |
| 821 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 822 | void r100_cp_commit(struct radeon_device *rdev) |
| 823 | { |
| 824 | WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); |
| 825 | (void)RREG32(RADEON_CP_RB_WPTR); |
| 826 | } |
| 827 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 828 | |
| 829 | /* |
| 830 | * CS functions |
| 831 | */ |
| 832 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
| 833 | struct radeon_cs_packet *pkt, |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 834 | const unsigned *auth, unsigned n, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 835 | radeon_packet0_check_t check) |
| 836 | { |
| 837 | unsigned reg; |
| 838 | unsigned i, j, m; |
| 839 | unsigned idx; |
| 840 | int r; |
| 841 | |
| 842 | idx = pkt->idx + 1; |
| 843 | reg = pkt->reg; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 844 | /* Check that register fall into register range |
| 845 | * determined by the number of entry (n) in the |
| 846 | * safe register bitmap. |
| 847 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 848 | if (pkt->one_reg_wr) { |
| 849 | if ((reg >> 7) > n) { |
| 850 | return -EINVAL; |
| 851 | } |
| 852 | } else { |
| 853 | if (((reg + (pkt->count << 2)) >> 7) > n) { |
| 854 | return -EINVAL; |
| 855 | } |
| 856 | } |
| 857 | for (i = 0; i <= pkt->count; i++, idx++) { |
| 858 | j = (reg >> 7); |
| 859 | m = 1 << ((reg >> 2) & 31); |
| 860 | if (auth[j] & m) { |
| 861 | r = check(p, pkt, idx, reg); |
| 862 | if (r) { |
| 863 | return r; |
| 864 | } |
| 865 | } |
| 866 | if (pkt->one_reg_wr) { |
| 867 | if (!(auth[j] & m)) { |
| 868 | break; |
| 869 | } |
| 870 | } else { |
| 871 | reg += 4; |
| 872 | } |
| 873 | } |
| 874 | return 0; |
| 875 | } |
| 876 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 877 | void r100_cs_dump_packet(struct radeon_cs_parser *p, |
| 878 | struct radeon_cs_packet *pkt) |
| 879 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 880 | volatile uint32_t *ib; |
| 881 | unsigned i; |
| 882 | unsigned idx; |
| 883 | |
| 884 | ib = p->ib->ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 885 | idx = pkt->idx; |
| 886 | for (i = 0; i <= (pkt->count + 1); i++, idx++) { |
| 887 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); |
| 888 | } |
| 889 | } |
| 890 | |
| 891 | /** |
| 892 | * r100_cs_packet_parse() - parse cp packet and point ib index to next packet |
| 893 | * @parser: parser structure holding parsing context. |
| 894 | * @pkt: where to store packet informations |
| 895 | * |
| 896 | * Assume that chunk_ib_index is properly set. Will return -EINVAL |
| 897 | * if packet is bigger than remaining ib size. or if packets is unknown. |
| 898 | **/ |
| 899 | int r100_cs_packet_parse(struct radeon_cs_parser *p, |
| 900 | struct radeon_cs_packet *pkt, |
| 901 | unsigned idx) |
| 902 | { |
| 903 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; |
Roel Kluin | fa99239 | 2009-08-03 14:20:32 +0200 | [diff] [blame] | 904 | uint32_t header; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 905 | |
| 906 | if (idx >= ib_chunk->length_dw) { |
| 907 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", |
| 908 | idx, ib_chunk->length_dw); |
| 909 | return -EINVAL; |
| 910 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 911 | header = radeon_get_ib_value(p, idx); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 912 | pkt->idx = idx; |
| 913 | pkt->type = CP_PACKET_GET_TYPE(header); |
| 914 | pkt->count = CP_PACKET_GET_COUNT(header); |
| 915 | switch (pkt->type) { |
| 916 | case PACKET_TYPE0: |
| 917 | pkt->reg = CP_PACKET0_GET_REG(header); |
| 918 | pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); |
| 919 | break; |
| 920 | case PACKET_TYPE3: |
| 921 | pkt->opcode = CP_PACKET3_GET_OPCODE(header); |
| 922 | break; |
| 923 | case PACKET_TYPE2: |
| 924 | pkt->count = -1; |
| 925 | break; |
| 926 | default: |
| 927 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); |
| 928 | return -EINVAL; |
| 929 | } |
| 930 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { |
| 931 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", |
| 932 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); |
| 933 | return -EINVAL; |
| 934 | } |
| 935 | return 0; |
| 936 | } |
| 937 | |
| 938 | /** |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 939 | * r100_cs_packet_next_vline() - parse userspace VLINE packet |
| 940 | * @parser: parser structure holding parsing context. |
| 941 | * |
| 942 | * Userspace sends a special sequence for VLINE waits. |
| 943 | * PACKET0 - VLINE_START_END + value |
| 944 | * PACKET0 - WAIT_UNTIL +_value |
| 945 | * RELOC (P3) - crtc_id in reloc. |
| 946 | * |
| 947 | * This function parses this and relocates the VLINE START END |
| 948 | * and WAIT UNTIL packets to the correct crtc. |
| 949 | * It also detects a switched off crtc and nulls out the |
| 950 | * wait in that case. |
| 951 | */ |
| 952 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) |
| 953 | { |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 954 | struct drm_mode_object *obj; |
| 955 | struct drm_crtc *crtc; |
| 956 | struct radeon_crtc *radeon_crtc; |
| 957 | struct radeon_cs_packet p3reloc, waitreloc; |
| 958 | int crtc_id; |
| 959 | int r; |
| 960 | uint32_t header, h_idx, reg; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 961 | volatile uint32_t *ib; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 962 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 963 | ib = p->ib->ptr; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 964 | |
| 965 | /* parse the wait until */ |
| 966 | r = r100_cs_packet_parse(p, &waitreloc, p->idx); |
| 967 | if (r) |
| 968 | return r; |
| 969 | |
| 970 | /* check its a wait until and only 1 count */ |
| 971 | if (waitreloc.reg != RADEON_WAIT_UNTIL || |
| 972 | waitreloc.count != 0) { |
| 973 | DRM_ERROR("vline wait had illegal wait until segment\n"); |
| 974 | r = -EINVAL; |
| 975 | return r; |
| 976 | } |
| 977 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 978 | if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 979 | DRM_ERROR("vline wait had illegal wait until\n"); |
| 980 | r = -EINVAL; |
| 981 | return r; |
| 982 | } |
| 983 | |
| 984 | /* jump over the NOP */ |
Alex Deucher | 90ebd06 | 2009-09-25 16:39:24 -0400 | [diff] [blame] | 985 | r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 986 | if (r) |
| 987 | return r; |
| 988 | |
| 989 | h_idx = p->idx - 2; |
Alex Deucher | 90ebd06 | 2009-09-25 16:39:24 -0400 | [diff] [blame] | 990 | p->idx += waitreloc.count + 2; |
| 991 | p->idx += p3reloc.count + 2; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 992 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 993 | header = radeon_get_ib_value(p, h_idx); |
| 994 | crtc_id = radeon_get_ib_value(p, h_idx + 5); |
Dave Airlie | d4ac6a0 | 2009-10-08 11:32:49 +1000 | [diff] [blame] | 995 | reg = CP_PACKET0_GET_REG(header); |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 996 | mutex_lock(&p->rdev->ddev->mode_config.mutex); |
| 997 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); |
| 998 | if (!obj) { |
| 999 | DRM_ERROR("cannot find crtc %d\n", crtc_id); |
| 1000 | r = -EINVAL; |
| 1001 | goto out; |
| 1002 | } |
| 1003 | crtc = obj_to_crtc(obj); |
| 1004 | radeon_crtc = to_radeon_crtc(crtc); |
| 1005 | crtc_id = radeon_crtc->crtc_id; |
| 1006 | |
| 1007 | if (!crtc->enabled) { |
| 1008 | /* if the CRTC isn't enabled - we need to nop out the wait until */ |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1009 | ib[h_idx + 2] = PACKET2(0); |
| 1010 | ib[h_idx + 3] = PACKET2(0); |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1011 | } else if (crtc_id == 1) { |
| 1012 | switch (reg) { |
| 1013 | case AVIVO_D1MODE_VLINE_START_END: |
Alex Deucher | 90ebd06 | 2009-09-25 16:39:24 -0400 | [diff] [blame] | 1014 | header &= ~R300_CP_PACKET0_REG_MASK; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1015 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; |
| 1016 | break; |
| 1017 | case RADEON_CRTC_GUI_TRIG_VLINE: |
Alex Deucher | 90ebd06 | 2009-09-25 16:39:24 -0400 | [diff] [blame] | 1018 | header &= ~R300_CP_PACKET0_REG_MASK; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1019 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; |
| 1020 | break; |
| 1021 | default: |
| 1022 | DRM_ERROR("unknown crtc reloc\n"); |
| 1023 | r = -EINVAL; |
| 1024 | goto out; |
| 1025 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1026 | ib[h_idx] = header; |
| 1027 | ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; |
Dave Airlie | 531369e | 2009-06-29 11:21:25 +1000 | [diff] [blame] | 1028 | } |
| 1029 | out: |
| 1030 | mutex_unlock(&p->rdev->ddev->mode_config.mutex); |
| 1031 | return r; |
| 1032 | } |
| 1033 | |
| 1034 | /** |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1035 | * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 |
| 1036 | * @parser: parser structure holding parsing context. |
| 1037 | * @data: pointer to relocation data |
| 1038 | * @offset_start: starting offset |
| 1039 | * @offset_mask: offset mask (to align start offset on) |
| 1040 | * @reloc: reloc informations |
| 1041 | * |
| 1042 | * Check next packet is relocation packet3, do bo validation and compute |
| 1043 | * GPU offset using the provided start. |
| 1044 | **/ |
| 1045 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, |
| 1046 | struct radeon_cs_reloc **cs_reloc) |
| 1047 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1048 | struct radeon_cs_chunk *relocs_chunk; |
| 1049 | struct radeon_cs_packet p3reloc; |
| 1050 | unsigned idx; |
| 1051 | int r; |
| 1052 | |
| 1053 | if (p->chunk_relocs_idx == -1) { |
| 1054 | DRM_ERROR("No relocation chunk !\n"); |
| 1055 | return -EINVAL; |
| 1056 | } |
| 1057 | *cs_reloc = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1058 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
| 1059 | r = r100_cs_packet_parse(p, &p3reloc, p->idx); |
| 1060 | if (r) { |
| 1061 | return r; |
| 1062 | } |
| 1063 | p->idx += p3reloc.count + 2; |
| 1064 | if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { |
| 1065 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", |
| 1066 | p3reloc.idx); |
| 1067 | r100_cs_dump_packet(p, &p3reloc); |
| 1068 | return -EINVAL; |
| 1069 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1070 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1071 | if (idx >= relocs_chunk->length_dw) { |
| 1072 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
| 1073 | idx, relocs_chunk->length_dw); |
| 1074 | r100_cs_dump_packet(p, &p3reloc); |
| 1075 | return -EINVAL; |
| 1076 | } |
| 1077 | /* FIXME: we assume reloc size is 4 dwords */ |
| 1078 | *cs_reloc = p->relocs_ptr[(idx / 4)]; |
| 1079 | return 0; |
| 1080 | } |
| 1081 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1082 | static int r100_get_vtx_size(uint32_t vtx_fmt) |
| 1083 | { |
| 1084 | int vtx_size; |
| 1085 | vtx_size = 2; |
| 1086 | /* ordered according to bits in spec */ |
| 1087 | if (vtx_fmt & RADEON_SE_VTX_FMT_W0) |
| 1088 | vtx_size++; |
| 1089 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) |
| 1090 | vtx_size += 3; |
| 1091 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) |
| 1092 | vtx_size++; |
| 1093 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) |
| 1094 | vtx_size++; |
| 1095 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) |
| 1096 | vtx_size += 3; |
| 1097 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) |
| 1098 | vtx_size++; |
| 1099 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) |
| 1100 | vtx_size++; |
| 1101 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) |
| 1102 | vtx_size += 2; |
| 1103 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) |
| 1104 | vtx_size += 2; |
| 1105 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) |
| 1106 | vtx_size++; |
| 1107 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) |
| 1108 | vtx_size += 2; |
| 1109 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) |
| 1110 | vtx_size++; |
| 1111 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) |
| 1112 | vtx_size += 2; |
| 1113 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) |
| 1114 | vtx_size++; |
| 1115 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) |
| 1116 | vtx_size++; |
| 1117 | /* blend weight */ |
| 1118 | if (vtx_fmt & (0x7 << 15)) |
| 1119 | vtx_size += (vtx_fmt >> 15) & 0x7; |
| 1120 | if (vtx_fmt & RADEON_SE_VTX_FMT_N0) |
| 1121 | vtx_size += 3; |
| 1122 | if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) |
| 1123 | vtx_size += 2; |
| 1124 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) |
| 1125 | vtx_size++; |
| 1126 | if (vtx_fmt & RADEON_SE_VTX_FMT_W1) |
| 1127 | vtx_size++; |
| 1128 | if (vtx_fmt & RADEON_SE_VTX_FMT_N1) |
| 1129 | vtx_size++; |
| 1130 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z) |
| 1131 | vtx_size++; |
| 1132 | return vtx_size; |
| 1133 | } |
| 1134 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1135 | static int r100_packet0_check(struct radeon_cs_parser *p, |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1136 | struct radeon_cs_packet *pkt, |
| 1137 | unsigned idx, unsigned reg) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1138 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1139 | struct radeon_cs_reloc *reloc; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1140 | struct r100_cs_track *track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1141 | volatile uint32_t *ib; |
| 1142 | uint32_t tmp; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1143 | int r; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1144 | int i, face; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1145 | u32 tile_flags = 0; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1146 | u32 idx_value; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1147 | |
| 1148 | ib = p->ib->ptr; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1149 | track = (struct r100_cs_track *)p->track; |
| 1150 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1151 | idx_value = radeon_get_ib_value(p, idx); |
| 1152 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1153 | switch (reg) { |
| 1154 | case RADEON_CRTC_GUI_TRIG_VLINE: |
| 1155 | r = r100_cs_packet_parse_vline(p); |
| 1156 | if (r) { |
| 1157 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1158 | idx, reg); |
| 1159 | r100_cs_dump_packet(p, pkt); |
| 1160 | return r; |
| 1161 | } |
| 1162 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1163 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
| 1164 | * range access */ |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1165 | case RADEON_DST_PITCH_OFFSET: |
| 1166 | case RADEON_SRC_PITCH_OFFSET: |
| 1167 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
| 1168 | if (r) |
| 1169 | return r; |
| 1170 | break; |
| 1171 | case RADEON_RB3D_DEPTHOFFSET: |
| 1172 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1173 | if (r) { |
| 1174 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1175 | idx, reg); |
| 1176 | r100_cs_dump_packet(p, pkt); |
| 1177 | return r; |
| 1178 | } |
| 1179 | track->zb.robj = reloc->robj; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1180 | track->zb.offset = idx_value; |
| 1181 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1182 | break; |
| 1183 | case RADEON_RB3D_COLOROFFSET: |
| 1184 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1185 | if (r) { |
| 1186 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1187 | idx, reg); |
| 1188 | r100_cs_dump_packet(p, pkt); |
| 1189 | return r; |
| 1190 | } |
| 1191 | track->cb[0].robj = reloc->robj; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1192 | track->cb[0].offset = idx_value; |
| 1193 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1194 | break; |
| 1195 | case RADEON_PP_TXOFFSET_0: |
| 1196 | case RADEON_PP_TXOFFSET_1: |
| 1197 | case RADEON_PP_TXOFFSET_2: |
| 1198 | i = (reg - RADEON_PP_TXOFFSET_0) / 24; |
| 1199 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1200 | if (r) { |
| 1201 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1202 | idx, reg); |
| 1203 | r100_cs_dump_packet(p, pkt); |
| 1204 | return r; |
| 1205 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1206 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1207 | track->textures[i].robj = reloc->robj; |
| 1208 | break; |
| 1209 | case RADEON_PP_CUBIC_OFFSET_T0_0: |
| 1210 | case RADEON_PP_CUBIC_OFFSET_T0_1: |
| 1211 | case RADEON_PP_CUBIC_OFFSET_T0_2: |
| 1212 | case RADEON_PP_CUBIC_OFFSET_T0_3: |
| 1213 | case RADEON_PP_CUBIC_OFFSET_T0_4: |
| 1214 | i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; |
| 1215 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1216 | if (r) { |
| 1217 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1218 | idx, reg); |
| 1219 | r100_cs_dump_packet(p, pkt); |
| 1220 | return r; |
| 1221 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1222 | track->textures[0].cube_info[i].offset = idx_value; |
| 1223 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1224 | track->textures[0].cube_info[i].robj = reloc->robj; |
| 1225 | break; |
| 1226 | case RADEON_PP_CUBIC_OFFSET_T1_0: |
| 1227 | case RADEON_PP_CUBIC_OFFSET_T1_1: |
| 1228 | case RADEON_PP_CUBIC_OFFSET_T1_2: |
| 1229 | case RADEON_PP_CUBIC_OFFSET_T1_3: |
| 1230 | case RADEON_PP_CUBIC_OFFSET_T1_4: |
| 1231 | i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; |
| 1232 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1233 | if (r) { |
| 1234 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1235 | idx, reg); |
| 1236 | r100_cs_dump_packet(p, pkt); |
| 1237 | return r; |
| 1238 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1239 | track->textures[1].cube_info[i].offset = idx_value; |
| 1240 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1241 | track->textures[1].cube_info[i].robj = reloc->robj; |
| 1242 | break; |
| 1243 | case RADEON_PP_CUBIC_OFFSET_T2_0: |
| 1244 | case RADEON_PP_CUBIC_OFFSET_T2_1: |
| 1245 | case RADEON_PP_CUBIC_OFFSET_T2_2: |
| 1246 | case RADEON_PP_CUBIC_OFFSET_T2_3: |
| 1247 | case RADEON_PP_CUBIC_OFFSET_T2_4: |
| 1248 | i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; |
| 1249 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1250 | if (r) { |
| 1251 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1252 | idx, reg); |
| 1253 | r100_cs_dump_packet(p, pkt); |
| 1254 | return r; |
| 1255 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1256 | track->textures[2].cube_info[i].offset = idx_value; |
| 1257 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1258 | track->textures[2].cube_info[i].robj = reloc->robj; |
| 1259 | break; |
| 1260 | case RADEON_RE_WIDTH_HEIGHT: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1261 | track->maxy = ((idx_value >> 16) & 0x7FF); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1262 | break; |
| 1263 | case RADEON_RB3D_COLORPITCH: |
| 1264 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1265 | if (r) { |
| 1266 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1267 | idx, reg); |
| 1268 | r100_cs_dump_packet(p, pkt); |
| 1269 | return r; |
| 1270 | } |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1271 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1272 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
| 1273 | tile_flags |= RADEON_COLOR_TILE_ENABLE; |
| 1274 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) |
| 1275 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1276 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1277 | tmp = idx_value & ~(0x7 << 16); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1278 | tmp |= tile_flags; |
| 1279 | ib[idx] = tmp; |
| 1280 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1281 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1282 | break; |
| 1283 | case RADEON_RB3D_DEPTHPITCH: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1284 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1285 | break; |
| 1286 | case RADEON_RB3D_CNTL: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1287 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1288 | case 7: |
| 1289 | case 8: |
| 1290 | case 9: |
| 1291 | case 11: |
| 1292 | case 12: |
| 1293 | track->cb[0].cpp = 1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1294 | break; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1295 | case 3: |
| 1296 | case 4: |
| 1297 | case 15: |
| 1298 | track->cb[0].cpp = 2; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1299 | break; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1300 | case 6: |
| 1301 | track->cb[0].cpp = 4; |
Dave Airlie | 17782d9 | 2009-08-21 10:07:54 +1000 | [diff] [blame] | 1302 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1303 | default: |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1304 | DRM_ERROR("Invalid color buffer format (%d) !\n", |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1305 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1306 | return -EINVAL; |
| 1307 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1308 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1309 | break; |
| 1310 | case RADEON_RB3D_ZSTENCILCNTL: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1311 | switch (idx_value & 0xf) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1312 | case 0: |
| 1313 | track->zb.cpp = 2; |
| 1314 | break; |
| 1315 | case 2: |
| 1316 | case 3: |
| 1317 | case 4: |
| 1318 | case 5: |
| 1319 | case 9: |
| 1320 | case 11: |
| 1321 | track->zb.cpp = 4; |
| 1322 | break; |
| 1323 | default: |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1324 | break; |
| 1325 | } |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1326 | break; |
| 1327 | case RADEON_RB3D_ZPASS_ADDR: |
| 1328 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1329 | if (r) { |
| 1330 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| 1331 | idx, reg); |
| 1332 | r100_cs_dump_packet(p, pkt); |
| 1333 | return r; |
| 1334 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1335 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1336 | break; |
| 1337 | case RADEON_PP_CNTL: |
| 1338 | { |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1339 | uint32_t temp = idx_value >> 4; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1340 | for (i = 0; i < track->num_texture; i++) |
| 1341 | track->textures[i].enabled = !!(temp & (1 << i)); |
| 1342 | } |
| 1343 | break; |
| 1344 | case RADEON_SE_VF_CNTL: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1345 | track->vap_vf_cntl = idx_value; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1346 | break; |
| 1347 | case RADEON_SE_VTX_FMT: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1348 | track->vtx_size = r100_get_vtx_size(idx_value); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1349 | break; |
| 1350 | case RADEON_PP_TEX_SIZE_0: |
| 1351 | case RADEON_PP_TEX_SIZE_1: |
| 1352 | case RADEON_PP_TEX_SIZE_2: |
| 1353 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1354 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
| 1355 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1356 | break; |
| 1357 | case RADEON_PP_TEX_PITCH_0: |
| 1358 | case RADEON_PP_TEX_PITCH_1: |
| 1359 | case RADEON_PP_TEX_PITCH_2: |
| 1360 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1361 | track->textures[i].pitch = idx_value + 32; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1362 | break; |
| 1363 | case RADEON_PP_TXFILTER_0: |
| 1364 | case RADEON_PP_TXFILTER_1: |
| 1365 | case RADEON_PP_TXFILTER_2: |
| 1366 | i = (reg - RADEON_PP_TXFILTER_0) / 24; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1367 | track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1368 | >> RADEON_MAX_MIP_LEVEL_SHIFT); |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1369 | tmp = (idx_value >> 23) & 0x7; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1370 | if (tmp == 2 || tmp == 6) |
| 1371 | track->textures[i].roundup_w = false; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1372 | tmp = (idx_value >> 27) & 0x7; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1373 | if (tmp == 2 || tmp == 6) |
| 1374 | track->textures[i].roundup_h = false; |
| 1375 | break; |
| 1376 | case RADEON_PP_TXFORMAT_0: |
| 1377 | case RADEON_PP_TXFORMAT_1: |
| 1378 | case RADEON_PP_TXFORMAT_2: |
| 1379 | i = (reg - RADEON_PP_TXFORMAT_0) / 24; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1380 | if (idx_value & RADEON_TXFORMAT_NON_POWER2) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1381 | track->textures[i].use_pitch = 1; |
| 1382 | } else { |
| 1383 | track->textures[i].use_pitch = 0; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1384 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
| 1385 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1386 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1387 | if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1388 | track->textures[i].tex_coord_type = 2; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1389 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1390 | case RADEON_TXFORMAT_I8: |
| 1391 | case RADEON_TXFORMAT_RGB332: |
| 1392 | case RADEON_TXFORMAT_Y8: |
| 1393 | track->textures[i].cpp = 1; |
| 1394 | break; |
| 1395 | case RADEON_TXFORMAT_AI88: |
| 1396 | case RADEON_TXFORMAT_ARGB1555: |
| 1397 | case RADEON_TXFORMAT_RGB565: |
| 1398 | case RADEON_TXFORMAT_ARGB4444: |
| 1399 | case RADEON_TXFORMAT_VYUY422: |
| 1400 | case RADEON_TXFORMAT_YVYU422: |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1401 | case RADEON_TXFORMAT_SHADOW16: |
| 1402 | case RADEON_TXFORMAT_LDUDV655: |
| 1403 | case RADEON_TXFORMAT_DUDV88: |
| 1404 | track->textures[i].cpp = 2; |
| 1405 | break; |
| 1406 | case RADEON_TXFORMAT_ARGB8888: |
| 1407 | case RADEON_TXFORMAT_RGBA8888: |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1408 | case RADEON_TXFORMAT_SHADOW32: |
| 1409 | case RADEON_TXFORMAT_LDUDUV8888: |
| 1410 | track->textures[i].cpp = 4; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1411 | break; |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 1412 | case RADEON_TXFORMAT_DXT1: |
| 1413 | track->textures[i].cpp = 1; |
| 1414 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; |
| 1415 | break; |
| 1416 | case RADEON_TXFORMAT_DXT23: |
| 1417 | case RADEON_TXFORMAT_DXT45: |
| 1418 | track->textures[i].cpp = 1; |
| 1419 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; |
| 1420 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1421 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1422 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
| 1423 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1424 | break; |
| 1425 | case RADEON_PP_CUBIC_FACES_0: |
| 1426 | case RADEON_PP_CUBIC_FACES_1: |
| 1427 | case RADEON_PP_CUBIC_FACES_2: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1428 | tmp = idx_value; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1429 | i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; |
| 1430 | for (face = 0; face < 4; face++) { |
| 1431 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); |
| 1432 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); |
| 1433 | } |
| 1434 | break; |
| 1435 | default: |
| 1436 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", |
| 1437 | reg, idx); |
| 1438 | return -EINVAL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1439 | } |
| 1440 | return 0; |
| 1441 | } |
| 1442 | |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1443 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
| 1444 | struct radeon_cs_packet *pkt, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1445 | struct radeon_bo *robj) |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1446 | { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1447 | unsigned idx; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1448 | u32 value; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1449 | idx = pkt->idx + 1; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1450 | value = radeon_get_ib_value(p, idx + 2); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1451 | if ((value + 1) > radeon_bo_size(robj)) { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1452 | DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
| 1453 | "(need %u have %lu) !\n", |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1454 | value + 1, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1455 | radeon_bo_size(robj)); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1456 | return -EINVAL; |
| 1457 | } |
| 1458 | return 0; |
| 1459 | } |
| 1460 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1461 | static int r100_packet3_check(struct radeon_cs_parser *p, |
| 1462 | struct radeon_cs_packet *pkt) |
| 1463 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1464 | struct radeon_cs_reloc *reloc; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1465 | struct r100_cs_track *track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1466 | unsigned idx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1467 | volatile uint32_t *ib; |
| 1468 | int r; |
| 1469 | |
| 1470 | ib = p->ib->ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1471 | idx = pkt->idx + 1; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1472 | track = (struct r100_cs_track *)p->track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1473 | switch (pkt->opcode) { |
| 1474 | case PACKET3_3D_LOAD_VBPNTR: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1475 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
| 1476 | if (r) |
| 1477 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1478 | break; |
| 1479 | case PACKET3_INDX_BUFFER: |
| 1480 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1481 | if (r) { |
| 1482 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
| 1483 | r100_cs_dump_packet(p, pkt); |
| 1484 | return r; |
| 1485 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1486 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1487 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
| 1488 | if (r) { |
| 1489 | return r; |
| 1490 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1491 | break; |
| 1492 | case 0x23: |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1493 | /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ |
| 1494 | r = r100_cs_packet_next_reloc(p, &reloc); |
| 1495 | if (r) { |
| 1496 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
| 1497 | r100_cs_dump_packet(p, pkt); |
| 1498 | return r; |
| 1499 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1500 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1501 | track->num_arrays = 1; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1502 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1503 | |
| 1504 | track->arrays[0].robj = reloc->robj; |
| 1505 | track->arrays[0].esize = track->vtx_size; |
| 1506 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1507 | track->max_indx = radeon_get_ib_value(p, idx+1); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1508 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1509 | track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1510 | track->immd_dwords = pkt->count - 1; |
| 1511 | r = r100_cs_track_check(p->rdev, track); |
| 1512 | if (r) |
| 1513 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1514 | break; |
| 1515 | case PACKET3_3D_DRAW_IMMD: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1516 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1517 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
| 1518 | return -EINVAL; |
| 1519 | } |
Alex Deucher | cf57fc7 | 2010-01-18 20:20:07 -0500 | [diff] [blame] | 1520 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1521 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1522 | track->immd_dwords = pkt->count - 1; |
| 1523 | r = r100_cs_track_check(p->rdev, track); |
| 1524 | if (r) |
| 1525 | return r; |
| 1526 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1527 | /* triggers drawing using in-packet vertex data */ |
| 1528 | case PACKET3_3D_DRAW_IMMD_2: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1529 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1530 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
| 1531 | return -EINVAL; |
| 1532 | } |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1533 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1534 | track->immd_dwords = pkt->count; |
| 1535 | r = r100_cs_track_check(p->rdev, track); |
| 1536 | if (r) |
| 1537 | return r; |
| 1538 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1539 | /* triggers drawing using in-packet vertex data */ |
| 1540 | case PACKET3_3D_DRAW_VBUF_2: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1541 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1542 | r = r100_cs_track_check(p->rdev, track); |
| 1543 | if (r) |
| 1544 | return r; |
| 1545 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1546 | /* triggers drawing of vertex buffers setup elsewhere */ |
| 1547 | case PACKET3_3D_DRAW_INDX_2: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1548 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1549 | r = r100_cs_track_check(p->rdev, track); |
| 1550 | if (r) |
| 1551 | return r; |
| 1552 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1553 | /* triggers drawing using indices to vertex buffer */ |
| 1554 | case PACKET3_3D_DRAW_VBUF: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1555 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1556 | r = r100_cs_track_check(p->rdev, track); |
| 1557 | if (r) |
| 1558 | return r; |
| 1559 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1560 | /* triggers drawing of vertex buffers setup elsewhere */ |
| 1561 | case PACKET3_3D_DRAW_INDX: |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 1562 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1563 | r = r100_cs_track_check(p->rdev, track); |
| 1564 | if (r) |
| 1565 | return r; |
| 1566 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1567 | /* triggers drawing using indices to vertex buffer */ |
| 1568 | case PACKET3_NOP: |
| 1569 | break; |
| 1570 | default: |
| 1571 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
| 1572 | return -EINVAL; |
| 1573 | } |
| 1574 | return 0; |
| 1575 | } |
| 1576 | |
| 1577 | int r100_cs_parse(struct radeon_cs_parser *p) |
| 1578 | { |
| 1579 | struct radeon_cs_packet pkt; |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1580 | struct r100_cs_track *track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1581 | int r; |
| 1582 | |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1583 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
| 1584 | r100_cs_track_clear(p->rdev, track); |
| 1585 | p->track = track; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1586 | do { |
| 1587 | r = r100_cs_packet_parse(p, &pkt, p->idx); |
| 1588 | if (r) { |
| 1589 | return r; |
| 1590 | } |
| 1591 | p->idx += pkt.count + 2; |
| 1592 | switch (pkt.type) { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1593 | case PACKET_TYPE0: |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1594 | if (p->rdev->family >= CHIP_R200) |
| 1595 | r = r100_cs_parse_packet0(p, &pkt, |
| 1596 | p->rdev->config.r100.reg_safe_bm, |
| 1597 | p->rdev->config.r100.reg_safe_bm_size, |
| 1598 | &r200_packet0_check); |
| 1599 | else |
| 1600 | r = r100_cs_parse_packet0(p, &pkt, |
| 1601 | p->rdev->config.r100.reg_safe_bm, |
| 1602 | p->rdev->config.r100.reg_safe_bm_size, |
| 1603 | &r100_packet0_check); |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1604 | break; |
| 1605 | case PACKET_TYPE2: |
| 1606 | break; |
| 1607 | case PACKET_TYPE3: |
| 1608 | r = r100_packet3_check(p, &pkt); |
| 1609 | break; |
| 1610 | default: |
| 1611 | DRM_ERROR("Unknown packet type %d !\n", |
| 1612 | pkt.type); |
| 1613 | return -EINVAL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1614 | } |
| 1615 | if (r) { |
| 1616 | return r; |
| 1617 | } |
| 1618 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
| 1619 | return 0; |
| 1620 | } |
| 1621 | |
| 1622 | |
| 1623 | /* |
| 1624 | * Global GPU functions |
| 1625 | */ |
| 1626 | void r100_errata(struct radeon_device *rdev) |
| 1627 | { |
| 1628 | rdev->pll_errata = 0; |
| 1629 | |
| 1630 | if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { |
| 1631 | rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; |
| 1632 | } |
| 1633 | |
| 1634 | if (rdev->family == CHIP_RV100 || |
| 1635 | rdev->family == CHIP_RS100 || |
| 1636 | rdev->family == CHIP_RS200) { |
| 1637 | rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; |
| 1638 | } |
| 1639 | } |
| 1640 | |
| 1641 | /* Wait for vertical sync on primary CRTC */ |
| 1642 | void r100_gpu_wait_for_vsync(struct radeon_device *rdev) |
| 1643 | { |
| 1644 | uint32_t crtc_gen_cntl, tmp; |
| 1645 | int i; |
| 1646 | |
| 1647 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
| 1648 | if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || |
| 1649 | !(crtc_gen_cntl & RADEON_CRTC_EN)) { |
| 1650 | return; |
| 1651 | } |
| 1652 | /* Clear the CRTC_VBLANK_SAVE bit */ |
| 1653 | WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); |
| 1654 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 1655 | tmp = RREG32(RADEON_CRTC_STATUS); |
| 1656 | if (tmp & RADEON_CRTC_VBLANK_SAVE) { |
| 1657 | return; |
| 1658 | } |
| 1659 | DRM_UDELAY(1); |
| 1660 | } |
| 1661 | } |
| 1662 | |
| 1663 | /* Wait for vertical sync on secondary CRTC */ |
| 1664 | void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) |
| 1665 | { |
| 1666 | uint32_t crtc2_gen_cntl, tmp; |
| 1667 | int i; |
| 1668 | |
| 1669 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
| 1670 | if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || |
| 1671 | !(crtc2_gen_cntl & RADEON_CRTC2_EN)) |
| 1672 | return; |
| 1673 | |
| 1674 | /* Clear the CRTC_VBLANK_SAVE bit */ |
| 1675 | WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); |
| 1676 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 1677 | tmp = RREG32(RADEON_CRTC2_STATUS); |
| 1678 | if (tmp & RADEON_CRTC2_VBLANK_SAVE) { |
| 1679 | return; |
| 1680 | } |
| 1681 | DRM_UDELAY(1); |
| 1682 | } |
| 1683 | } |
| 1684 | |
| 1685 | int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) |
| 1686 | { |
| 1687 | unsigned i; |
| 1688 | uint32_t tmp; |
| 1689 | |
| 1690 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 1691 | tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; |
| 1692 | if (tmp >= n) { |
| 1693 | return 0; |
| 1694 | } |
| 1695 | DRM_UDELAY(1); |
| 1696 | } |
| 1697 | return -1; |
| 1698 | } |
| 1699 | |
| 1700 | int r100_gui_wait_for_idle(struct radeon_device *rdev) |
| 1701 | { |
| 1702 | unsigned i; |
| 1703 | uint32_t tmp; |
| 1704 | |
| 1705 | if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { |
| 1706 | printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" |
| 1707 | " Bad things might happen.\n"); |
| 1708 | } |
| 1709 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 1710 | tmp = RREG32(RADEON_RBBM_STATUS); |
Alex Deucher | 4612dc9 | 2010-02-05 01:58:28 -0500 | [diff] [blame] | 1711 | if (!(tmp & RADEON_RBBM_ACTIVE)) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1712 | return 0; |
| 1713 | } |
| 1714 | DRM_UDELAY(1); |
| 1715 | } |
| 1716 | return -1; |
| 1717 | } |
| 1718 | |
| 1719 | int r100_mc_wait_for_idle(struct radeon_device *rdev) |
| 1720 | { |
| 1721 | unsigned i; |
| 1722 | uint32_t tmp; |
| 1723 | |
| 1724 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 1725 | /* read MC_STATUS */ |
Alex Deucher | 4612dc9 | 2010-02-05 01:58:28 -0500 | [diff] [blame] | 1726 | tmp = RREG32(RADEON_MC_STATUS); |
| 1727 | if (tmp & RADEON_MC_IDLE) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1728 | return 0; |
| 1729 | } |
| 1730 | DRM_UDELAY(1); |
| 1731 | } |
| 1732 | return -1; |
| 1733 | } |
| 1734 | |
| 1735 | void r100_gpu_init(struct radeon_device *rdev) |
| 1736 | { |
| 1737 | /* TODO: anythings to do here ? pipes ? */ |
| 1738 | r100_hdp_reset(rdev); |
| 1739 | } |
| 1740 | |
| 1741 | void r100_hdp_reset(struct radeon_device *rdev) |
| 1742 | { |
| 1743 | uint32_t tmp; |
| 1744 | |
| 1745 | tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL; |
| 1746 | tmp |= (7 << 28); |
| 1747 | WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE); |
| 1748 | (void)RREG32(RADEON_HOST_PATH_CNTL); |
| 1749 | udelay(200); |
| 1750 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
| 1751 | WREG32(RADEON_HOST_PATH_CNTL, tmp); |
| 1752 | (void)RREG32(RADEON_HOST_PATH_CNTL); |
| 1753 | } |
| 1754 | |
| 1755 | int r100_rb2d_reset(struct radeon_device *rdev) |
| 1756 | { |
| 1757 | uint32_t tmp; |
| 1758 | int i; |
| 1759 | |
| 1760 | WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2); |
| 1761 | (void)RREG32(RADEON_RBBM_SOFT_RESET); |
| 1762 | udelay(200); |
| 1763 | WREG32(RADEON_RBBM_SOFT_RESET, 0); |
| 1764 | /* Wait to prevent race in RBBM_STATUS */ |
| 1765 | mdelay(1); |
| 1766 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 1767 | tmp = RREG32(RADEON_RBBM_STATUS); |
| 1768 | if (!(tmp & (1 << 26))) { |
| 1769 | DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n", |
| 1770 | tmp); |
| 1771 | return 0; |
| 1772 | } |
| 1773 | DRM_UDELAY(1); |
| 1774 | } |
| 1775 | tmp = RREG32(RADEON_RBBM_STATUS); |
| 1776 | DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp); |
| 1777 | return -1; |
| 1778 | } |
| 1779 | |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame^] | 1780 | void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp) |
| 1781 | { |
| 1782 | lockup->last_cp_rptr = cp->rptr; |
| 1783 | lockup->last_jiffies = jiffies; |
| 1784 | } |
| 1785 | |
| 1786 | /** |
| 1787 | * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information |
| 1788 | * @rdev: radeon device structure |
| 1789 | * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations |
| 1790 | * @cp: radeon_cp structure holding CP information |
| 1791 | * |
| 1792 | * We don't need to initialize the lockup tracking information as we will either |
| 1793 | * have CP rptr to a different value of jiffies wrap around which will force |
| 1794 | * initialization of the lockup tracking informations. |
| 1795 | * |
| 1796 | * A possible false positivie is if we get call after while and last_cp_rptr == |
| 1797 | * the current CP rptr, even if it's unlikely it might happen. To avoid this |
| 1798 | * if the elapsed time since last call is bigger than 2 second than we return |
| 1799 | * false and update the tracking information. Due to this the caller must call |
| 1800 | * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported |
| 1801 | * the fencing code should be cautious about that. |
| 1802 | * |
| 1803 | * Caller should write to the ring to force CP to do something so we don't get |
| 1804 | * false positive when CP is just gived nothing to do. |
| 1805 | * |
| 1806 | **/ |
| 1807 | bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp) |
| 1808 | { |
| 1809 | unsigned long cjiffies, elapsed; |
| 1810 | |
| 1811 | cjiffies = jiffies; |
| 1812 | if (!time_after(cjiffies, lockup->last_jiffies)) { |
| 1813 | /* likely a wrap around */ |
| 1814 | lockup->last_cp_rptr = cp->rptr; |
| 1815 | lockup->last_jiffies = jiffies; |
| 1816 | return false; |
| 1817 | } |
| 1818 | if (cp->rptr != lockup->last_cp_rptr) { |
| 1819 | /* CP is still working no lockup */ |
| 1820 | lockup->last_cp_rptr = cp->rptr; |
| 1821 | lockup->last_jiffies = jiffies; |
| 1822 | return false; |
| 1823 | } |
| 1824 | elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); |
| 1825 | if (elapsed >= 3000) { |
| 1826 | /* very likely the improbable case where current |
| 1827 | * rptr is equal to last recorded, a while ago, rptr |
| 1828 | * this is more likely a false positive update tracking |
| 1829 | * information which should force us to be recall at |
| 1830 | * latter point |
| 1831 | */ |
| 1832 | lockup->last_cp_rptr = cp->rptr; |
| 1833 | lockup->last_jiffies = jiffies; |
| 1834 | return false; |
| 1835 | } |
| 1836 | if (elapsed >= 1000) { |
| 1837 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
| 1838 | return true; |
| 1839 | } |
| 1840 | /* give a chance to the GPU ... */ |
| 1841 | return false; |
| 1842 | } |
| 1843 | |
| 1844 | bool r100_gpu_is_lockup(struct radeon_device *rdev) |
| 1845 | { |
| 1846 | u32 rbbm_status; |
| 1847 | int r; |
| 1848 | |
| 1849 | rbbm_status = RREG32(R_000E40_RBBM_STATUS); |
| 1850 | if (!G_000E40_GUI_ACTIVE(rbbm_status)) { |
| 1851 | r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp); |
| 1852 | return false; |
| 1853 | } |
| 1854 | /* force CP activities */ |
| 1855 | r = radeon_ring_lock(rdev, 2); |
| 1856 | if (!r) { |
| 1857 | /* PACKET2 NOP */ |
| 1858 | radeon_ring_write(rdev, 0x80000000); |
| 1859 | radeon_ring_write(rdev, 0x80000000); |
| 1860 | radeon_ring_unlock_commit(rdev); |
| 1861 | } |
| 1862 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); |
| 1863 | return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp); |
| 1864 | } |
| 1865 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1866 | int r100_gpu_reset(struct radeon_device *rdev) |
| 1867 | { |
| 1868 | uint32_t status; |
| 1869 | |
| 1870 | /* reset order likely matter */ |
| 1871 | status = RREG32(RADEON_RBBM_STATUS); |
| 1872 | /* reset HDP */ |
| 1873 | r100_hdp_reset(rdev); |
| 1874 | /* reset rb2d */ |
| 1875 | if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
| 1876 | r100_rb2d_reset(rdev); |
| 1877 | } |
| 1878 | /* TODO: reset 3D engine */ |
| 1879 | /* reset CP */ |
| 1880 | status = RREG32(RADEON_RBBM_STATUS); |
| 1881 | if (status & (1 << 16)) { |
| 1882 | r100_cp_reset(rdev); |
| 1883 | } |
| 1884 | /* Check if GPU is idle */ |
| 1885 | status = RREG32(RADEON_RBBM_STATUS); |
Alex Deucher | 4612dc9 | 2010-02-05 01:58:28 -0500 | [diff] [blame] | 1886 | if (status & RADEON_RBBM_ACTIVE) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1887 | DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
| 1888 | return -1; |
| 1889 | } |
| 1890 | DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
| 1891 | return 0; |
| 1892 | } |
| 1893 | |
Alex Deucher | 92cde00 | 2009-12-04 10:55:12 -0500 | [diff] [blame] | 1894 | void r100_set_common_regs(struct radeon_device *rdev) |
| 1895 | { |
Alex Deucher | 2739d49 | 2010-02-05 03:34:16 -0500 | [diff] [blame] | 1896 | struct drm_device *dev = rdev->ddev; |
| 1897 | bool force_dac2 = false; |
Dave Airlie | d668046 | 2010-03-31 13:41:35 +1000 | [diff] [blame] | 1898 | u32 tmp; |
Alex Deucher | 2739d49 | 2010-02-05 03:34:16 -0500 | [diff] [blame] | 1899 | |
Alex Deucher | 92cde00 | 2009-12-04 10:55:12 -0500 | [diff] [blame] | 1900 | /* set these so they don't interfere with anything */ |
| 1901 | WREG32(RADEON_OV0_SCALE_CNTL, 0); |
| 1902 | WREG32(RADEON_SUBPIC_CNTL, 0); |
| 1903 | WREG32(RADEON_VIPH_CONTROL, 0); |
| 1904 | WREG32(RADEON_I2C_CNTL_1, 0); |
| 1905 | WREG32(RADEON_DVI_I2C_CNTL_1, 0); |
| 1906 | WREG32(RADEON_CAP0_TRIG_CNTL, 0); |
| 1907 | WREG32(RADEON_CAP1_TRIG_CNTL, 0); |
Alex Deucher | 2739d49 | 2010-02-05 03:34:16 -0500 | [diff] [blame] | 1908 | |
| 1909 | /* always set up dac2 on rn50 and some rv100 as lots |
| 1910 | * of servers seem to wire it up to a VGA port but |
| 1911 | * don't report it in the bios connector |
| 1912 | * table. |
| 1913 | */ |
| 1914 | switch (dev->pdev->device) { |
| 1915 | /* RN50 */ |
| 1916 | case 0x515e: |
| 1917 | case 0x5969: |
| 1918 | force_dac2 = true; |
| 1919 | break; |
| 1920 | /* RV100*/ |
| 1921 | case 0x5159: |
| 1922 | case 0x515a: |
| 1923 | /* DELL triple head servers */ |
| 1924 | if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && |
| 1925 | ((dev->pdev->subsystem_device == 0x016c) || |
| 1926 | (dev->pdev->subsystem_device == 0x016d) || |
| 1927 | (dev->pdev->subsystem_device == 0x016e) || |
| 1928 | (dev->pdev->subsystem_device == 0x016f) || |
| 1929 | (dev->pdev->subsystem_device == 0x0170) || |
| 1930 | (dev->pdev->subsystem_device == 0x017d) || |
| 1931 | (dev->pdev->subsystem_device == 0x017e) || |
| 1932 | (dev->pdev->subsystem_device == 0x0183) || |
| 1933 | (dev->pdev->subsystem_device == 0x018a) || |
| 1934 | (dev->pdev->subsystem_device == 0x019a))) |
| 1935 | force_dac2 = true; |
| 1936 | break; |
| 1937 | } |
| 1938 | |
| 1939 | if (force_dac2) { |
| 1940 | u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
| 1941 | u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 1942 | u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); |
| 1943 | |
| 1944 | /* For CRT on DAC2, don't turn it on if BIOS didn't |
| 1945 | enable it, even it's detected. |
| 1946 | */ |
| 1947 | |
| 1948 | /* force it to crtc0 */ |
| 1949 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; |
| 1950 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; |
| 1951 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
| 1952 | |
| 1953 | /* set up the TV DAC */ |
| 1954 | tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | |
| 1955 | RADEON_TV_DAC_STD_MASK | |
| 1956 | RADEON_TV_DAC_RDACPD | |
| 1957 | RADEON_TV_DAC_GDACPD | |
| 1958 | RADEON_TV_DAC_BDACPD | |
| 1959 | RADEON_TV_DAC_BGADJ_MASK | |
| 1960 | RADEON_TV_DAC_DACADJ_MASK); |
| 1961 | tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | |
| 1962 | RADEON_TV_DAC_NHOLD | |
| 1963 | RADEON_TV_DAC_STD_PS2 | |
| 1964 | (0x58 << 16)); |
| 1965 | |
| 1966 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 1967 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
| 1968 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
| 1969 | } |
Dave Airlie | d668046 | 2010-03-31 13:41:35 +1000 | [diff] [blame] | 1970 | |
| 1971 | /* switch PM block to ACPI mode */ |
| 1972 | tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); |
| 1973 | tmp &= ~RADEON_PM_MODE_SEL; |
| 1974 | WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); |
| 1975 | |
Alex Deucher | 92cde00 | 2009-12-04 10:55:12 -0500 | [diff] [blame] | 1976 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1977 | |
| 1978 | /* |
| 1979 | * VRAM info |
| 1980 | */ |
| 1981 | static void r100_vram_get_type(struct radeon_device *rdev) |
| 1982 | { |
| 1983 | uint32_t tmp; |
| 1984 | |
| 1985 | rdev->mc.vram_is_ddr = false; |
| 1986 | if (rdev->flags & RADEON_IS_IGP) |
| 1987 | rdev->mc.vram_is_ddr = true; |
| 1988 | else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) |
| 1989 | rdev->mc.vram_is_ddr = true; |
| 1990 | if ((rdev->family == CHIP_RV100) || |
| 1991 | (rdev->family == CHIP_RS100) || |
| 1992 | (rdev->family == CHIP_RS200)) { |
| 1993 | tmp = RREG32(RADEON_MEM_CNTL); |
| 1994 | if (tmp & RV100_HALF_MODE) { |
| 1995 | rdev->mc.vram_width = 32; |
| 1996 | } else { |
| 1997 | rdev->mc.vram_width = 64; |
| 1998 | } |
| 1999 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
| 2000 | rdev->mc.vram_width /= 4; |
| 2001 | rdev->mc.vram_is_ddr = true; |
| 2002 | } |
| 2003 | } else if (rdev->family <= CHIP_RV280) { |
| 2004 | tmp = RREG32(RADEON_MEM_CNTL); |
| 2005 | if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { |
| 2006 | rdev->mc.vram_width = 128; |
| 2007 | } else { |
| 2008 | rdev->mc.vram_width = 64; |
| 2009 | } |
| 2010 | } else { |
| 2011 | /* newer IGPs */ |
| 2012 | rdev->mc.vram_width = 128; |
| 2013 | } |
| 2014 | } |
| 2015 | |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2016 | static u32 r100_get_accessible_vram(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2017 | { |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2018 | u32 aper_size; |
| 2019 | u8 byte; |
| 2020 | |
| 2021 | aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
| 2022 | |
| 2023 | /* Set HDP_APER_CNTL only on cards that are known not to be broken, |
| 2024 | * that is has the 2nd generation multifunction PCI interface |
| 2025 | */ |
| 2026 | if (rdev->family == CHIP_RV280 || |
| 2027 | rdev->family >= CHIP_RV350) { |
| 2028 | WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, |
| 2029 | ~RADEON_HDP_APER_CNTL); |
| 2030 | DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); |
| 2031 | return aper_size * 2; |
| 2032 | } |
| 2033 | |
| 2034 | /* Older cards have all sorts of funny issues to deal with. First |
| 2035 | * check if it's a multifunction card by reading the PCI config |
| 2036 | * header type... Limit those to one aperture size |
| 2037 | */ |
| 2038 | pci_read_config_byte(rdev->pdev, 0xe, &byte); |
| 2039 | if (byte & 0x80) { |
| 2040 | DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); |
| 2041 | DRM_INFO("Limiting VRAM to one aperture\n"); |
| 2042 | return aper_size; |
| 2043 | } |
| 2044 | |
| 2045 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS |
| 2046 | * have set it up. We don't write this as it's broken on some ASICs but |
| 2047 | * we expect the BIOS to have done the right thing (might be too optimistic...) |
| 2048 | */ |
| 2049 | if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) |
| 2050 | return aper_size * 2; |
| 2051 | return aper_size; |
| 2052 | } |
| 2053 | |
| 2054 | void r100_vram_init_sizes(struct radeon_device *rdev) |
| 2055 | { |
| 2056 | u64 config_aper_size; |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2057 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2058 | /* work out accessible VRAM */ |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2059 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
| 2060 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
Jerome Glisse | 51e5fcd | 2010-02-19 14:33:54 +0000 | [diff] [blame] | 2061 | rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); |
| 2062 | /* FIXME we don't use the second aperture yet when we could use it */ |
| 2063 | if (rdev->mc.visible_vram_size > rdev->mc.aper_size) |
| 2064 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2065 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2066 | if (rdev->flags & RADEON_IS_IGP) { |
| 2067 | uint32_t tom; |
| 2068 | /* read NB_TOM to get the amount of ram stolen for the GPU */ |
| 2069 | tom = RREG32(RADEON_NB_TOM); |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 2070 | rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 2071 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
| 2072 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2073 | } else { |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 2074 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2075 | /* Some production boards of m6 will report 0 |
| 2076 | * if it's 8 MB |
| 2077 | */ |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 2078 | if (rdev->mc.real_vram_size == 0) { |
| 2079 | rdev->mc.real_vram_size = 8192 * 1024; |
| 2080 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2081 | } |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2082 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
| 2083 | * Novell bug 204882 + along with lots of ubuntu ones |
| 2084 | */ |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 2085 | if (config_aper_size > rdev->mc.real_vram_size) |
| 2086 | rdev->mc.mc_vram_size = config_aper_size; |
| 2087 | else |
| 2088 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2089 | } |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2090 | /* FIXME remove this once we support unmappable VRAM */ |
| 2091 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) { |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 2092 | rdev->mc.mc_vram_size = rdev->mc.aper_size; |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 2093 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2094 | } |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2095 | } |
| 2096 | |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 2097 | void r100_vga_set_state(struct radeon_device *rdev, bool state) |
| 2098 | { |
| 2099 | uint32_t temp; |
| 2100 | |
| 2101 | temp = RREG32(RADEON_CONFIG_CNTL); |
| 2102 | if (state == false) { |
| 2103 | temp &= ~(1<<8); |
| 2104 | temp |= (1<<9); |
| 2105 | } else { |
| 2106 | temp &= ~(1<<9); |
| 2107 | } |
| 2108 | WREG32(RADEON_CONFIG_CNTL, temp); |
| 2109 | } |
| 2110 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2111 | void r100_mc_init(struct radeon_device *rdev) |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2112 | { |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2113 | u64 base; |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2114 | |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2115 | r100_vram_get_type(rdev); |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 2116 | r100_vram_init_sizes(rdev); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 2117 | base = rdev->mc.aper_base; |
| 2118 | if (rdev->flags & RADEON_IS_IGP) |
| 2119 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
| 2120 | radeon_vram_location(rdev, &rdev->mc, base); |
| 2121 | if (!(rdev->flags & RADEON_IS_AGP)) |
| 2122 | radeon_gtt_location(rdev, &rdev->mc); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 2123 | radeon_update_bandwidth_info(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2124 | } |
| 2125 | |
| 2126 | |
| 2127 | /* |
| 2128 | * Indirect registers accessor |
| 2129 | */ |
| 2130 | void r100_pll_errata_after_index(struct radeon_device *rdev) |
| 2131 | { |
| 2132 | if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) { |
| 2133 | return; |
| 2134 | } |
| 2135 | (void)RREG32(RADEON_CLOCK_CNTL_DATA); |
| 2136 | (void)RREG32(RADEON_CRTC_GEN_CNTL); |
| 2137 | } |
| 2138 | |
| 2139 | static void r100_pll_errata_after_data(struct radeon_device *rdev) |
| 2140 | { |
| 2141 | /* This workarounds is necessary on RV100, RS100 and RS200 chips |
| 2142 | * or the chip could hang on a subsequent access |
| 2143 | */ |
| 2144 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { |
| 2145 | udelay(5000); |
| 2146 | } |
| 2147 | |
| 2148 | /* This function is required to workaround a hardware bug in some (all?) |
| 2149 | * revisions of the R300. This workaround should be called after every |
| 2150 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
| 2151 | * may not be correct. |
| 2152 | */ |
| 2153 | if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { |
| 2154 | uint32_t save, tmp; |
| 2155 | |
| 2156 | save = RREG32(RADEON_CLOCK_CNTL_INDEX); |
| 2157 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
| 2158 | WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); |
| 2159 | tmp = RREG32(RADEON_CLOCK_CNTL_DATA); |
| 2160 | WREG32(RADEON_CLOCK_CNTL_INDEX, save); |
| 2161 | } |
| 2162 | } |
| 2163 | |
| 2164 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) |
| 2165 | { |
| 2166 | uint32_t data; |
| 2167 | |
| 2168 | WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); |
| 2169 | r100_pll_errata_after_index(rdev); |
| 2170 | data = RREG32(RADEON_CLOCK_CNTL_DATA); |
| 2171 | r100_pll_errata_after_data(rdev); |
| 2172 | return data; |
| 2173 | } |
| 2174 | |
| 2175 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 2176 | { |
| 2177 | WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); |
| 2178 | r100_pll_errata_after_index(rdev); |
| 2179 | WREG32(RADEON_CLOCK_CNTL_DATA, v); |
| 2180 | r100_pll_errata_after_data(rdev); |
| 2181 | } |
| 2182 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 2183 | void r100_set_safe_registers(struct radeon_device *rdev) |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2184 | { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2185 | if (ASIC_IS_RN50(rdev)) { |
| 2186 | rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; |
| 2187 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); |
| 2188 | } else if (rdev->family < CHIP_R200) { |
| 2189 | rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; |
| 2190 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); |
| 2191 | } else { |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 2192 | r200_set_safe_registers(rdev); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2193 | } |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 2194 | } |
| 2195 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 2196 | /* |
| 2197 | * Debugfs info |
| 2198 | */ |
| 2199 | #if defined(CONFIG_DEBUG_FS) |
| 2200 | static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) |
| 2201 | { |
| 2202 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2203 | struct drm_device *dev = node->minor->dev; |
| 2204 | struct radeon_device *rdev = dev->dev_private; |
| 2205 | uint32_t reg, value; |
| 2206 | unsigned i; |
| 2207 | |
| 2208 | seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); |
| 2209 | seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); |
| 2210 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
| 2211 | for (i = 0; i < 64; i++) { |
| 2212 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); |
| 2213 | reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; |
| 2214 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); |
| 2215 | value = RREG32(RADEON_RBBM_CMDFIFO_DATA); |
| 2216 | seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); |
| 2217 | } |
| 2218 | return 0; |
| 2219 | } |
| 2220 | |
| 2221 | static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) |
| 2222 | { |
| 2223 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2224 | struct drm_device *dev = node->minor->dev; |
| 2225 | struct radeon_device *rdev = dev->dev_private; |
| 2226 | uint32_t rdp, wdp; |
| 2227 | unsigned count, i, j; |
| 2228 | |
| 2229 | radeon_ring_free_size(rdev); |
| 2230 | rdp = RREG32(RADEON_CP_RB_RPTR); |
| 2231 | wdp = RREG32(RADEON_CP_RB_WPTR); |
| 2232 | count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; |
| 2233 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
| 2234 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); |
| 2235 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); |
| 2236 | seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); |
| 2237 | seq_printf(m, "%u dwords in ring\n", count); |
| 2238 | for (j = 0; j <= count; j++) { |
| 2239 | i = (rdp + j) & rdev->cp.ptr_mask; |
| 2240 | seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); |
| 2241 | } |
| 2242 | return 0; |
| 2243 | } |
| 2244 | |
| 2245 | |
| 2246 | static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) |
| 2247 | { |
| 2248 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2249 | struct drm_device *dev = node->minor->dev; |
| 2250 | struct radeon_device *rdev = dev->dev_private; |
| 2251 | uint32_t csq_stat, csq2_stat, tmp; |
| 2252 | unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; |
| 2253 | unsigned i; |
| 2254 | |
| 2255 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); |
| 2256 | seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); |
| 2257 | csq_stat = RREG32(RADEON_CP_CSQ_STAT); |
| 2258 | csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); |
| 2259 | r_rptr = (csq_stat >> 0) & 0x3ff; |
| 2260 | r_wptr = (csq_stat >> 10) & 0x3ff; |
| 2261 | ib1_rptr = (csq_stat >> 20) & 0x3ff; |
| 2262 | ib1_wptr = (csq2_stat >> 0) & 0x3ff; |
| 2263 | ib2_rptr = (csq2_stat >> 10) & 0x3ff; |
| 2264 | ib2_wptr = (csq2_stat >> 20) & 0x3ff; |
| 2265 | seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); |
| 2266 | seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); |
| 2267 | seq_printf(m, "Ring rptr %u\n", r_rptr); |
| 2268 | seq_printf(m, "Ring wptr %u\n", r_wptr); |
| 2269 | seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); |
| 2270 | seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); |
| 2271 | seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); |
| 2272 | seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); |
| 2273 | /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms |
| 2274 | * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ |
| 2275 | seq_printf(m, "Ring fifo:\n"); |
| 2276 | for (i = 0; i < 256; i++) { |
| 2277 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
| 2278 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
| 2279 | seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); |
| 2280 | } |
| 2281 | seq_printf(m, "Indirect1 fifo:\n"); |
| 2282 | for (i = 256; i <= 512; i++) { |
| 2283 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
| 2284 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
| 2285 | seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); |
| 2286 | } |
| 2287 | seq_printf(m, "Indirect2 fifo:\n"); |
| 2288 | for (i = 640; i < ib1_wptr; i++) { |
| 2289 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); |
| 2290 | tmp = RREG32(RADEON_CP_CSQ_DATA); |
| 2291 | seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); |
| 2292 | } |
| 2293 | return 0; |
| 2294 | } |
| 2295 | |
| 2296 | static int r100_debugfs_mc_info(struct seq_file *m, void *data) |
| 2297 | { |
| 2298 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 2299 | struct drm_device *dev = node->minor->dev; |
| 2300 | struct radeon_device *rdev = dev->dev_private; |
| 2301 | uint32_t tmp; |
| 2302 | |
| 2303 | tmp = RREG32(RADEON_CONFIG_MEMSIZE); |
| 2304 | seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); |
| 2305 | tmp = RREG32(RADEON_MC_FB_LOCATION); |
| 2306 | seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); |
| 2307 | tmp = RREG32(RADEON_BUS_CNTL); |
| 2308 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); |
| 2309 | tmp = RREG32(RADEON_MC_AGP_LOCATION); |
| 2310 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); |
| 2311 | tmp = RREG32(RADEON_AGP_BASE); |
| 2312 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); |
| 2313 | tmp = RREG32(RADEON_HOST_PATH_CNTL); |
| 2314 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); |
| 2315 | tmp = RREG32(0x01D0); |
| 2316 | seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); |
| 2317 | tmp = RREG32(RADEON_AIC_LO_ADDR); |
| 2318 | seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); |
| 2319 | tmp = RREG32(RADEON_AIC_HI_ADDR); |
| 2320 | seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); |
| 2321 | tmp = RREG32(0x01E4); |
| 2322 | seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); |
| 2323 | return 0; |
| 2324 | } |
| 2325 | |
| 2326 | static struct drm_info_list r100_debugfs_rbbm_list[] = { |
| 2327 | {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, |
| 2328 | }; |
| 2329 | |
| 2330 | static struct drm_info_list r100_debugfs_cp_list[] = { |
| 2331 | {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, |
| 2332 | {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, |
| 2333 | }; |
| 2334 | |
| 2335 | static struct drm_info_list r100_debugfs_mc_info_list[] = { |
| 2336 | {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, |
| 2337 | }; |
| 2338 | #endif |
| 2339 | |
| 2340 | int r100_debugfs_rbbm_init(struct radeon_device *rdev) |
| 2341 | { |
| 2342 | #if defined(CONFIG_DEBUG_FS) |
| 2343 | return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); |
| 2344 | #else |
| 2345 | return 0; |
| 2346 | #endif |
| 2347 | } |
| 2348 | |
| 2349 | int r100_debugfs_cp_init(struct radeon_device *rdev) |
| 2350 | { |
| 2351 | #if defined(CONFIG_DEBUG_FS) |
| 2352 | return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); |
| 2353 | #else |
| 2354 | return 0; |
| 2355 | #endif |
| 2356 | } |
| 2357 | |
| 2358 | int r100_debugfs_mc_info_init(struct radeon_device *rdev) |
| 2359 | { |
| 2360 | #if defined(CONFIG_DEBUG_FS) |
| 2361 | return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); |
| 2362 | #else |
| 2363 | return 0; |
| 2364 | #endif |
| 2365 | } |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 2366 | |
| 2367 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
| 2368 | uint32_t tiling_flags, uint32_t pitch, |
| 2369 | uint32_t offset, uint32_t obj_size) |
| 2370 | { |
| 2371 | int surf_index = reg * 16; |
| 2372 | int flags = 0; |
| 2373 | |
| 2374 | /* r100/r200 divide by 16 */ |
| 2375 | if (rdev->family < CHIP_R300) |
| 2376 | flags = pitch / 16; |
| 2377 | else |
| 2378 | flags = pitch / 8; |
| 2379 | |
| 2380 | if (rdev->family <= CHIP_RS200) { |
| 2381 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
| 2382 | == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) |
| 2383 | flags |= RADEON_SURF_TILE_COLOR_BOTH; |
| 2384 | if (tiling_flags & RADEON_TILING_MACRO) |
| 2385 | flags |= RADEON_SURF_TILE_COLOR_MACRO; |
| 2386 | } else if (rdev->family <= CHIP_RV280) { |
| 2387 | if (tiling_flags & (RADEON_TILING_MACRO)) |
| 2388 | flags |= R200_SURF_TILE_COLOR_MACRO; |
| 2389 | if (tiling_flags & RADEON_TILING_MICRO) |
| 2390 | flags |= R200_SURF_TILE_COLOR_MICRO; |
| 2391 | } else { |
| 2392 | if (tiling_flags & RADEON_TILING_MACRO) |
| 2393 | flags |= R300_SURF_TILE_MACRO; |
| 2394 | if (tiling_flags & RADEON_TILING_MICRO) |
| 2395 | flags |= R300_SURF_TILE_MICRO; |
| 2396 | } |
| 2397 | |
Michel Dänzer | c88f9f0 | 2009-09-15 17:09:30 +0200 | [diff] [blame] | 2398 | if (tiling_flags & RADEON_TILING_SWAP_16BIT) |
| 2399 | flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; |
| 2400 | if (tiling_flags & RADEON_TILING_SWAP_32BIT) |
| 2401 | flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; |
| 2402 | |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 2403 | DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); |
| 2404 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); |
| 2405 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); |
| 2406 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); |
| 2407 | return 0; |
| 2408 | } |
| 2409 | |
| 2410 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg) |
| 2411 | { |
| 2412 | int surf_index = reg * 16; |
| 2413 | WREG32(RADEON_SURFACE0_INFO + surf_index, 0); |
| 2414 | } |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2415 | |
| 2416 | void r100_bandwidth_update(struct radeon_device *rdev) |
| 2417 | { |
| 2418 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; |
| 2419 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; |
| 2420 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; |
| 2421 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; |
| 2422 | fixed20_12 memtcas_ff[8] = { |
| 2423 | fixed_init(1), |
| 2424 | fixed_init(2), |
| 2425 | fixed_init(3), |
| 2426 | fixed_init(0), |
| 2427 | fixed_init_half(1), |
| 2428 | fixed_init_half(2), |
| 2429 | fixed_init(0), |
| 2430 | }; |
| 2431 | fixed20_12 memtcas_rs480_ff[8] = { |
| 2432 | fixed_init(0), |
| 2433 | fixed_init(1), |
| 2434 | fixed_init(2), |
| 2435 | fixed_init(3), |
| 2436 | fixed_init(0), |
| 2437 | fixed_init_half(1), |
| 2438 | fixed_init_half(2), |
| 2439 | fixed_init_half(3), |
| 2440 | }; |
| 2441 | fixed20_12 memtcas2_ff[8] = { |
| 2442 | fixed_init(0), |
| 2443 | fixed_init(1), |
| 2444 | fixed_init(2), |
| 2445 | fixed_init(3), |
| 2446 | fixed_init(4), |
| 2447 | fixed_init(5), |
| 2448 | fixed_init(6), |
| 2449 | fixed_init(7), |
| 2450 | }; |
| 2451 | fixed20_12 memtrbs[8] = { |
| 2452 | fixed_init(1), |
| 2453 | fixed_init_half(1), |
| 2454 | fixed_init(2), |
| 2455 | fixed_init_half(2), |
| 2456 | fixed_init(3), |
| 2457 | fixed_init_half(3), |
| 2458 | fixed_init(4), |
| 2459 | fixed_init_half(4) |
| 2460 | }; |
| 2461 | fixed20_12 memtrbs_r4xx[8] = { |
| 2462 | fixed_init(4), |
| 2463 | fixed_init(5), |
| 2464 | fixed_init(6), |
| 2465 | fixed_init(7), |
| 2466 | fixed_init(8), |
| 2467 | fixed_init(9), |
| 2468 | fixed_init(10), |
| 2469 | fixed_init(11) |
| 2470 | }; |
| 2471 | fixed20_12 min_mem_eff; |
| 2472 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; |
| 2473 | fixed20_12 cur_latency_mclk, cur_latency_sclk; |
| 2474 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, |
| 2475 | disp_drain_rate2, read_return_rate; |
| 2476 | fixed20_12 time_disp1_drop_priority; |
| 2477 | int c; |
| 2478 | int cur_size = 16; /* in octawords */ |
| 2479 | int critical_point = 0, critical_point2; |
| 2480 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ |
| 2481 | int stop_req, max_stop_req; |
| 2482 | struct drm_display_mode *mode1 = NULL; |
| 2483 | struct drm_display_mode *mode2 = NULL; |
| 2484 | uint32_t pixel_bytes1 = 0; |
| 2485 | uint32_t pixel_bytes2 = 0; |
| 2486 | |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 2487 | radeon_update_display_priority(rdev); |
| 2488 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2489 | if (rdev->mode_info.crtcs[0]->base.enabled) { |
| 2490 | mode1 = &rdev->mode_info.crtcs[0]->base.mode; |
| 2491 | pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; |
| 2492 | } |
Dave Airlie | dfee561 | 2009-10-02 09:19:09 +1000 | [diff] [blame] | 2493 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| 2494 | if (rdev->mode_info.crtcs[1]->base.enabled) { |
| 2495 | mode2 = &rdev->mode_info.crtcs[1]->base.mode; |
| 2496 | pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; |
| 2497 | } |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2498 | } |
| 2499 | |
| 2500 | min_mem_eff.full = rfixed_const_8(0); |
| 2501 | /* get modes */ |
| 2502 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { |
| 2503 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); |
| 2504 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); |
| 2505 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); |
| 2506 | /* check crtc enables */ |
| 2507 | if (mode2) |
| 2508 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); |
| 2509 | if (mode1) |
| 2510 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); |
| 2511 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); |
| 2512 | } |
| 2513 | |
| 2514 | /* |
| 2515 | * determine is there is enough bw for current mode |
| 2516 | */ |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 2517 | sclk_ff = rdev->pm.sclk; |
| 2518 | mclk_ff = rdev->pm.mclk; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2519 | |
| 2520 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); |
| 2521 | temp_ff.full = rfixed_const(temp); |
| 2522 | mem_bw.full = rfixed_mul(mclk_ff, temp_ff); |
| 2523 | |
| 2524 | pix_clk.full = 0; |
| 2525 | pix_clk2.full = 0; |
| 2526 | peak_disp_bw.full = 0; |
| 2527 | if (mode1) { |
| 2528 | temp_ff.full = rfixed_const(1000); |
| 2529 | pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */ |
| 2530 | pix_clk.full = rfixed_div(pix_clk, temp_ff); |
| 2531 | temp_ff.full = rfixed_const(pixel_bytes1); |
| 2532 | peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff); |
| 2533 | } |
| 2534 | if (mode2) { |
| 2535 | temp_ff.full = rfixed_const(1000); |
| 2536 | pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */ |
| 2537 | pix_clk2.full = rfixed_div(pix_clk2, temp_ff); |
| 2538 | temp_ff.full = rfixed_const(pixel_bytes2); |
| 2539 | peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff); |
| 2540 | } |
| 2541 | |
| 2542 | mem_bw.full = rfixed_mul(mem_bw, min_mem_eff); |
| 2543 | if (peak_disp_bw.full >= mem_bw.full) { |
| 2544 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" |
| 2545 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); |
| 2546 | } |
| 2547 | |
| 2548 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ |
| 2549 | temp = RREG32(RADEON_MEM_TIMING_CNTL); |
| 2550 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ |
| 2551 | mem_trcd = ((temp >> 2) & 0x3) + 1; |
| 2552 | mem_trp = ((temp & 0x3)) + 1; |
| 2553 | mem_tras = ((temp & 0x70) >> 4) + 1; |
| 2554 | } else if (rdev->family == CHIP_R300 || |
| 2555 | rdev->family == CHIP_R350) { /* r300, r350 */ |
| 2556 | mem_trcd = (temp & 0x7) + 1; |
| 2557 | mem_trp = ((temp >> 8) & 0x7) + 1; |
| 2558 | mem_tras = ((temp >> 11) & 0xf) + 4; |
| 2559 | } else if (rdev->family == CHIP_RV350 || |
| 2560 | rdev->family <= CHIP_RV380) { |
| 2561 | /* rv3x0 */ |
| 2562 | mem_trcd = (temp & 0x7) + 3; |
| 2563 | mem_trp = ((temp >> 8) & 0x7) + 3; |
| 2564 | mem_tras = ((temp >> 11) & 0xf) + 6; |
| 2565 | } else if (rdev->family == CHIP_R420 || |
| 2566 | rdev->family == CHIP_R423 || |
| 2567 | rdev->family == CHIP_RV410) { |
| 2568 | /* r4xx */ |
| 2569 | mem_trcd = (temp & 0xf) + 3; |
| 2570 | if (mem_trcd > 15) |
| 2571 | mem_trcd = 15; |
| 2572 | mem_trp = ((temp >> 8) & 0xf) + 3; |
| 2573 | if (mem_trp > 15) |
| 2574 | mem_trp = 15; |
| 2575 | mem_tras = ((temp >> 12) & 0x1f) + 6; |
| 2576 | if (mem_tras > 31) |
| 2577 | mem_tras = 31; |
| 2578 | } else { /* RV200, R200 */ |
| 2579 | mem_trcd = (temp & 0x7) + 1; |
| 2580 | mem_trp = ((temp >> 8) & 0x7) + 1; |
| 2581 | mem_tras = ((temp >> 12) & 0xf) + 4; |
| 2582 | } |
| 2583 | /* convert to FF */ |
| 2584 | trcd_ff.full = rfixed_const(mem_trcd); |
| 2585 | trp_ff.full = rfixed_const(mem_trp); |
| 2586 | tras_ff.full = rfixed_const(mem_tras); |
| 2587 | |
| 2588 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ |
| 2589 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); |
| 2590 | data = (temp & (7 << 20)) >> 20; |
| 2591 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { |
| 2592 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ |
| 2593 | tcas_ff = memtcas_rs480_ff[data]; |
| 2594 | else |
| 2595 | tcas_ff = memtcas_ff[data]; |
| 2596 | } else |
| 2597 | tcas_ff = memtcas2_ff[data]; |
| 2598 | |
| 2599 | if (rdev->family == CHIP_RS400 || |
| 2600 | rdev->family == CHIP_RS480) { |
| 2601 | /* extra cas latency stored in bits 23-25 0-4 clocks */ |
| 2602 | data = (temp >> 23) & 0x7; |
| 2603 | if (data < 5) |
| 2604 | tcas_ff.full += rfixed_const(data); |
| 2605 | } |
| 2606 | |
| 2607 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { |
| 2608 | /* on the R300, Tcas is included in Trbs. |
| 2609 | */ |
| 2610 | temp = RREG32(RADEON_MEM_CNTL); |
| 2611 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); |
| 2612 | if (data == 1) { |
| 2613 | if (R300_MEM_USE_CD_CH_ONLY & temp) { |
| 2614 | temp = RREG32(R300_MC_IND_INDEX); |
| 2615 | temp &= ~R300_MC_IND_ADDR_MASK; |
| 2616 | temp |= R300_MC_READ_CNTL_CD_mcind; |
| 2617 | WREG32(R300_MC_IND_INDEX, temp); |
| 2618 | temp = RREG32(R300_MC_IND_DATA); |
| 2619 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); |
| 2620 | } else { |
| 2621 | temp = RREG32(R300_MC_READ_CNTL_AB); |
| 2622 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
| 2623 | } |
| 2624 | } else { |
| 2625 | temp = RREG32(R300_MC_READ_CNTL_AB); |
| 2626 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); |
| 2627 | } |
| 2628 | if (rdev->family == CHIP_RV410 || |
| 2629 | rdev->family == CHIP_R420 || |
| 2630 | rdev->family == CHIP_R423) |
| 2631 | trbs_ff = memtrbs_r4xx[data]; |
| 2632 | else |
| 2633 | trbs_ff = memtrbs[data]; |
| 2634 | tcas_ff.full += trbs_ff.full; |
| 2635 | } |
| 2636 | |
| 2637 | sclk_eff_ff.full = sclk_ff.full; |
| 2638 | |
| 2639 | if (rdev->flags & RADEON_IS_AGP) { |
| 2640 | fixed20_12 agpmode_ff; |
| 2641 | agpmode_ff.full = rfixed_const(radeon_agpmode); |
| 2642 | temp_ff.full = rfixed_const_666(16); |
| 2643 | sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff); |
| 2644 | } |
| 2645 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ |
| 2646 | |
| 2647 | if (ASIC_IS_R300(rdev)) { |
| 2648 | sclk_delay_ff.full = rfixed_const(250); |
| 2649 | } else { |
| 2650 | if ((rdev->family == CHIP_RV100) || |
| 2651 | rdev->flags & RADEON_IS_IGP) { |
| 2652 | if (rdev->mc.vram_is_ddr) |
| 2653 | sclk_delay_ff.full = rfixed_const(41); |
| 2654 | else |
| 2655 | sclk_delay_ff.full = rfixed_const(33); |
| 2656 | } else { |
| 2657 | if (rdev->mc.vram_width == 128) |
| 2658 | sclk_delay_ff.full = rfixed_const(57); |
| 2659 | else |
| 2660 | sclk_delay_ff.full = rfixed_const(41); |
| 2661 | } |
| 2662 | } |
| 2663 | |
| 2664 | mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff); |
| 2665 | |
| 2666 | if (rdev->mc.vram_is_ddr) { |
| 2667 | if (rdev->mc.vram_width == 32) { |
| 2668 | k1.full = rfixed_const(40); |
| 2669 | c = 3; |
| 2670 | } else { |
| 2671 | k1.full = rfixed_const(20); |
| 2672 | c = 1; |
| 2673 | } |
| 2674 | } else { |
| 2675 | k1.full = rfixed_const(40); |
| 2676 | c = 3; |
| 2677 | } |
| 2678 | |
| 2679 | temp_ff.full = rfixed_const(2); |
| 2680 | mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff); |
| 2681 | temp_ff.full = rfixed_const(c); |
| 2682 | mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff); |
| 2683 | temp_ff.full = rfixed_const(4); |
| 2684 | mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff); |
| 2685 | mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff); |
| 2686 | mc_latency_mclk.full += k1.full; |
| 2687 | |
| 2688 | mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff); |
| 2689 | mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff); |
| 2690 | |
| 2691 | /* |
| 2692 | HW cursor time assuming worst case of full size colour cursor. |
| 2693 | */ |
| 2694 | temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); |
| 2695 | temp_ff.full += trcd_ff.full; |
| 2696 | if (temp_ff.full < tras_ff.full) |
| 2697 | temp_ff.full = tras_ff.full; |
| 2698 | cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff); |
| 2699 | |
| 2700 | temp_ff.full = rfixed_const(cur_size); |
| 2701 | cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff); |
| 2702 | /* |
| 2703 | Find the total latency for the display data. |
| 2704 | */ |
Michel Dänzer | b5fc901 | 2009-10-08 10:44:10 +0200 | [diff] [blame] | 2705 | disp_latency_overhead.full = rfixed_const(8); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 2706 | disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff); |
| 2707 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; |
| 2708 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; |
| 2709 | |
| 2710 | if (mc_latency_mclk.full > mc_latency_sclk.full) |
| 2711 | disp_latency.full = mc_latency_mclk.full; |
| 2712 | else |
| 2713 | disp_latency.full = mc_latency_sclk.full; |
| 2714 | |
| 2715 | /* setup Max GRPH_STOP_REQ default value */ |
| 2716 | if (ASIC_IS_RV100(rdev)) |
| 2717 | max_stop_req = 0x5c; |
| 2718 | else |
| 2719 | max_stop_req = 0x7c; |
| 2720 | |
| 2721 | if (mode1) { |
| 2722 | /* CRTC1 |
| 2723 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. |
| 2724 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] |
| 2725 | */ |
| 2726 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; |
| 2727 | |
| 2728 | if (stop_req > max_stop_req) |
| 2729 | stop_req = max_stop_req; |
| 2730 | |
| 2731 | /* |
| 2732 | Find the drain rate of the display buffer. |
| 2733 | */ |
| 2734 | temp_ff.full = rfixed_const((16/pixel_bytes1)); |
| 2735 | disp_drain_rate.full = rfixed_div(pix_clk, temp_ff); |
| 2736 | |
| 2737 | /* |
| 2738 | Find the critical point of the display buffer. |
| 2739 | */ |
| 2740 | crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency); |
| 2741 | crit_point_ff.full += rfixed_const_half(0); |
| 2742 | |
| 2743 | critical_point = rfixed_trunc(crit_point_ff); |
| 2744 | |
| 2745 | if (rdev->disp_priority == 2) { |
| 2746 | critical_point = 0; |
| 2747 | } |
| 2748 | |
| 2749 | /* |
| 2750 | The critical point should never be above max_stop_req-4. Setting |
| 2751 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. |
| 2752 | */ |
| 2753 | if (max_stop_req - critical_point < 4) |
| 2754 | critical_point = 0; |
| 2755 | |
| 2756 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { |
| 2757 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ |
| 2758 | critical_point = 0x10; |
| 2759 | } |
| 2760 | |
| 2761 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); |
| 2762 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); |
| 2763 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
| 2764 | temp &= ~(RADEON_GRPH_START_REQ_MASK); |
| 2765 | if ((rdev->family == CHIP_R350) && |
| 2766 | (stop_req > 0x15)) { |
| 2767 | stop_req -= 0x10; |
| 2768 | } |
| 2769 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
| 2770 | temp |= RADEON_GRPH_BUFFER_SIZE; |
| 2771 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | |
| 2772 | RADEON_GRPH_CRITICAL_AT_SOF | |
| 2773 | RADEON_GRPH_STOP_CNTL); |
| 2774 | /* |
| 2775 | Write the result into the register. |
| 2776 | */ |
| 2777 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
| 2778 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
| 2779 | |
| 2780 | #if 0 |
| 2781 | if ((rdev->family == CHIP_RS400) || |
| 2782 | (rdev->family == CHIP_RS480)) { |
| 2783 | /* attempt to program RS400 disp regs correctly ??? */ |
| 2784 | temp = RREG32(RS400_DISP1_REG_CNTL); |
| 2785 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | |
| 2786 | RS400_DISP1_STOP_REQ_LEVEL_MASK); |
| 2787 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | |
| 2788 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
| 2789 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
| 2790 | temp = RREG32(RS400_DMIF_MEM_CNTL1); |
| 2791 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | |
| 2792 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); |
| 2793 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | |
| 2794 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | |
| 2795 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); |
| 2796 | } |
| 2797 | #endif |
| 2798 | |
| 2799 | DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n", |
| 2800 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ |
| 2801 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); |
| 2802 | } |
| 2803 | |
| 2804 | if (mode2) { |
| 2805 | u32 grph2_cntl; |
| 2806 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; |
| 2807 | |
| 2808 | if (stop_req > max_stop_req) |
| 2809 | stop_req = max_stop_req; |
| 2810 | |
| 2811 | /* |
| 2812 | Find the drain rate of the display buffer. |
| 2813 | */ |
| 2814 | temp_ff.full = rfixed_const((16/pixel_bytes2)); |
| 2815 | disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff); |
| 2816 | |
| 2817 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); |
| 2818 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); |
| 2819 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); |
| 2820 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); |
| 2821 | if ((rdev->family == CHIP_R350) && |
| 2822 | (stop_req > 0x15)) { |
| 2823 | stop_req -= 0x10; |
| 2824 | } |
| 2825 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); |
| 2826 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; |
| 2827 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | |
| 2828 | RADEON_GRPH_CRITICAL_AT_SOF | |
| 2829 | RADEON_GRPH_STOP_CNTL); |
| 2830 | |
| 2831 | if ((rdev->family == CHIP_RS100) || |
| 2832 | (rdev->family == CHIP_RS200)) |
| 2833 | critical_point2 = 0; |
| 2834 | else { |
| 2835 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; |
| 2836 | temp_ff.full = rfixed_const(temp); |
| 2837 | temp_ff.full = rfixed_mul(mclk_ff, temp_ff); |
| 2838 | if (sclk_ff.full < temp_ff.full) |
| 2839 | temp_ff.full = sclk_ff.full; |
| 2840 | |
| 2841 | read_return_rate.full = temp_ff.full; |
| 2842 | |
| 2843 | if (mode1) { |
| 2844 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; |
| 2845 | time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff); |
| 2846 | } else { |
| 2847 | time_disp1_drop_priority.full = 0; |
| 2848 | } |
| 2849 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; |
| 2850 | crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2); |
| 2851 | crit_point_ff.full += rfixed_const_half(0); |
| 2852 | |
| 2853 | critical_point2 = rfixed_trunc(crit_point_ff); |
| 2854 | |
| 2855 | if (rdev->disp_priority == 2) { |
| 2856 | critical_point2 = 0; |
| 2857 | } |
| 2858 | |
| 2859 | if (max_stop_req - critical_point2 < 4) |
| 2860 | critical_point2 = 0; |
| 2861 | |
| 2862 | } |
| 2863 | |
| 2864 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { |
| 2865 | /* some R300 cards have problem with this set to 0 */ |
| 2866 | critical_point2 = 0x10; |
| 2867 | } |
| 2868 | |
| 2869 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | |
| 2870 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); |
| 2871 | |
| 2872 | if ((rdev->family == CHIP_RS400) || |
| 2873 | (rdev->family == CHIP_RS480)) { |
| 2874 | #if 0 |
| 2875 | /* attempt to program RS400 disp2 regs correctly ??? */ |
| 2876 | temp = RREG32(RS400_DISP2_REQ_CNTL1); |
| 2877 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | |
| 2878 | RS400_DISP2_STOP_REQ_LEVEL_MASK); |
| 2879 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | |
| 2880 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | |
| 2881 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); |
| 2882 | temp = RREG32(RS400_DISP2_REQ_CNTL2); |
| 2883 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | |
| 2884 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); |
| 2885 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | |
| 2886 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | |
| 2887 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); |
| 2888 | #endif |
| 2889 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); |
| 2890 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); |
| 2891 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); |
| 2892 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); |
| 2893 | } |
| 2894 | |
| 2895 | DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n", |
| 2896 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); |
| 2897 | } |
| 2898 | } |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2899 | |
| 2900 | static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) |
| 2901 | { |
| 2902 | DRM_ERROR("pitch %d\n", t->pitch); |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 2903 | DRM_ERROR("use_pitch %d\n", t->use_pitch); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2904 | DRM_ERROR("width %d\n", t->width); |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 2905 | DRM_ERROR("width_11 %d\n", t->width_11); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2906 | DRM_ERROR("height %d\n", t->height); |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 2907 | DRM_ERROR("height_11 %d\n", t->height_11); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2908 | DRM_ERROR("num levels %d\n", t->num_levels); |
| 2909 | DRM_ERROR("depth %d\n", t->txdepth); |
| 2910 | DRM_ERROR("bpp %d\n", t->cpp); |
| 2911 | DRM_ERROR("coordinate type %d\n", t->tex_coord_type); |
| 2912 | DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); |
| 2913 | DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 2914 | DRM_ERROR("compress format %d\n", t->compress_format); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2915 | } |
| 2916 | |
| 2917 | static int r100_cs_track_cube(struct radeon_device *rdev, |
| 2918 | struct r100_cs_track *track, unsigned idx) |
| 2919 | { |
| 2920 | unsigned face, w, h; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2921 | struct radeon_bo *cube_robj; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2922 | unsigned long size; |
| 2923 | |
| 2924 | for (face = 0; face < 5; face++) { |
| 2925 | cube_robj = track->textures[idx].cube_info[face].robj; |
| 2926 | w = track->textures[idx].cube_info[face].width; |
| 2927 | h = track->textures[idx].cube_info[face].height; |
| 2928 | |
| 2929 | size = w * h; |
| 2930 | size *= track->textures[idx].cpp; |
| 2931 | |
| 2932 | size += track->textures[idx].cube_info[face].offset; |
| 2933 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2934 | if (size > radeon_bo_size(cube_robj)) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2935 | DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2936 | size, radeon_bo_size(cube_robj)); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2937 | r100_cs_track_texture_print(&track->textures[idx]); |
| 2938 | return -1; |
| 2939 | } |
| 2940 | } |
| 2941 | return 0; |
| 2942 | } |
| 2943 | |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 2944 | static int r100_track_compress_size(int compress_format, int w, int h) |
| 2945 | { |
| 2946 | int block_width, block_height, block_bytes; |
| 2947 | int wblocks, hblocks; |
| 2948 | int min_wblocks; |
| 2949 | int sz; |
| 2950 | |
| 2951 | block_width = 4; |
| 2952 | block_height = 4; |
| 2953 | |
| 2954 | switch (compress_format) { |
| 2955 | case R100_TRACK_COMP_DXT1: |
| 2956 | block_bytes = 8; |
| 2957 | min_wblocks = 4; |
| 2958 | break; |
| 2959 | default: |
| 2960 | case R100_TRACK_COMP_DXT35: |
| 2961 | block_bytes = 16; |
| 2962 | min_wblocks = 2; |
| 2963 | break; |
| 2964 | } |
| 2965 | |
| 2966 | hblocks = (h + block_height - 1) / block_height; |
| 2967 | wblocks = (w + block_width - 1) / block_width; |
| 2968 | if (wblocks < min_wblocks) |
| 2969 | wblocks = min_wblocks; |
| 2970 | sz = wblocks * hblocks * block_bytes; |
| 2971 | return sz; |
| 2972 | } |
| 2973 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2974 | static int r100_cs_track_texture_check(struct radeon_device *rdev, |
| 2975 | struct r100_cs_track *track) |
| 2976 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 2977 | struct radeon_bo *robj; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2978 | unsigned long size; |
| 2979 | unsigned u, i, w, h; |
| 2980 | int ret; |
| 2981 | |
| 2982 | for (u = 0; u < track->num_texture; u++) { |
| 2983 | if (!track->textures[u].enabled) |
| 2984 | continue; |
| 2985 | robj = track->textures[u].robj; |
| 2986 | if (robj == NULL) { |
| 2987 | DRM_ERROR("No texture bound to unit %u\n", u); |
| 2988 | return -EINVAL; |
| 2989 | } |
| 2990 | size = 0; |
| 2991 | for (i = 0; i <= track->textures[u].num_levels; i++) { |
| 2992 | if (track->textures[u].use_pitch) { |
| 2993 | if (rdev->family < CHIP_R300) |
| 2994 | w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); |
| 2995 | else |
| 2996 | w = track->textures[u].pitch / (1 << i); |
| 2997 | } else { |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 2998 | w = track->textures[u].width; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 2999 | if (rdev->family >= CHIP_RV515) |
| 3000 | w |= track->textures[u].width_11; |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 3001 | w = w / (1 << i); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3002 | if (track->textures[u].roundup_w) |
| 3003 | w = roundup_pow_of_two(w); |
| 3004 | } |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 3005 | h = track->textures[u].height; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3006 | if (rdev->family >= CHIP_RV515) |
| 3007 | h |= track->textures[u].height_11; |
Mathias Fröhlich | ceb776b | 2009-10-19 12:50:41 -0400 | [diff] [blame] | 3008 | h = h / (1 << i); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3009 | if (track->textures[u].roundup_h) |
| 3010 | h = roundup_pow_of_two(h); |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 3011 | if (track->textures[u].compress_format) { |
| 3012 | |
| 3013 | size += r100_track_compress_size(track->textures[u].compress_format, w, h); |
| 3014 | /* compressed textures are block based */ |
| 3015 | } else |
| 3016 | size += w * h; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3017 | } |
| 3018 | size *= track->textures[u].cpp; |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 3019 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3020 | switch (track->textures[u].tex_coord_type) { |
| 3021 | case 0: |
| 3022 | break; |
| 3023 | case 1: |
| 3024 | size *= (1 << track->textures[u].txdepth); |
| 3025 | break; |
| 3026 | case 2: |
| 3027 | if (track->separate_cube) { |
| 3028 | ret = r100_cs_track_cube(rdev, track, u); |
| 3029 | if (ret) |
| 3030 | return ret; |
| 3031 | } else |
| 3032 | size *= 6; |
| 3033 | break; |
| 3034 | default: |
| 3035 | DRM_ERROR("Invalid texture coordinate type %u for unit " |
| 3036 | "%u\n", track->textures[u].tex_coord_type, u); |
| 3037 | return -EINVAL; |
| 3038 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3039 | if (size > radeon_bo_size(robj)) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3040 | DRM_ERROR("Texture of unit %u needs %lu bytes but is " |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3041 | "%lu\n", u, size, radeon_bo_size(robj)); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3042 | r100_cs_track_texture_print(&track->textures[u]); |
| 3043 | return -EINVAL; |
| 3044 | } |
| 3045 | } |
| 3046 | return 0; |
| 3047 | } |
| 3048 | |
| 3049 | int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) |
| 3050 | { |
| 3051 | unsigned i; |
| 3052 | unsigned long size; |
| 3053 | unsigned prim_walk; |
| 3054 | unsigned nverts; |
| 3055 | |
| 3056 | for (i = 0; i < track->num_cb; i++) { |
| 3057 | if (track->cb[i].robj == NULL) { |
Marek Olšák | 46c64d4 | 2009-12-17 06:02:28 +0100 | [diff] [blame] | 3058 | if (!(track->fastfill || track->color_channel_mask || |
| 3059 | track->blend_read_enable)) { |
| 3060 | continue; |
| 3061 | } |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3062 | DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); |
| 3063 | return -EINVAL; |
| 3064 | } |
| 3065 | size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; |
| 3066 | size += track->cb[i].offset; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3067 | if (size > radeon_bo_size(track->cb[i].robj)) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3068 | DRM_ERROR("[drm] Buffer too small for color buffer %d " |
| 3069 | "(need %lu have %lu) !\n", i, size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3070 | radeon_bo_size(track->cb[i].robj)); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3071 | DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", |
| 3072 | i, track->cb[i].pitch, track->cb[i].cpp, |
| 3073 | track->cb[i].offset, track->maxy); |
| 3074 | return -EINVAL; |
| 3075 | } |
| 3076 | } |
| 3077 | if (track->z_enabled) { |
| 3078 | if (track->zb.robj == NULL) { |
| 3079 | DRM_ERROR("[drm] No buffer for z buffer !\n"); |
| 3080 | return -EINVAL; |
| 3081 | } |
| 3082 | size = track->zb.pitch * track->zb.cpp * track->maxy; |
| 3083 | size += track->zb.offset; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3084 | if (size > radeon_bo_size(track->zb.robj)) { |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3085 | DRM_ERROR("[drm] Buffer too small for z buffer " |
| 3086 | "(need %lu have %lu) !\n", size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3087 | radeon_bo_size(track->zb.robj)); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3088 | DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", |
| 3089 | track->zb.pitch, track->zb.cpp, |
| 3090 | track->zb.offset, track->maxy); |
| 3091 | return -EINVAL; |
| 3092 | } |
| 3093 | } |
| 3094 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; |
| 3095 | nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; |
| 3096 | switch (prim_walk) { |
| 3097 | case 1: |
| 3098 | for (i = 0; i < track->num_arrays; i++) { |
| 3099 | size = track->arrays[i].esize * track->max_indx * 4; |
| 3100 | if (track->arrays[i].robj == NULL) { |
| 3101 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
| 3102 | "bound\n", prim_walk, i); |
| 3103 | return -EINVAL; |
| 3104 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3105 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
| 3106 | dev_err(rdev->dev, "(PW %u) Vertex array %u " |
| 3107 | "need %lu dwords have %lu dwords\n", |
| 3108 | prim_walk, i, size >> 2, |
| 3109 | radeon_bo_size(track->arrays[i].robj) |
| 3110 | >> 2); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3111 | DRM_ERROR("Max indices %u\n", track->max_indx); |
| 3112 | return -EINVAL; |
| 3113 | } |
| 3114 | } |
| 3115 | break; |
| 3116 | case 2: |
| 3117 | for (i = 0; i < track->num_arrays; i++) { |
| 3118 | size = track->arrays[i].esize * (nverts - 1) * 4; |
| 3119 | if (track->arrays[i].robj == NULL) { |
| 3120 | DRM_ERROR("(PW %u) Vertex array %u no buffer " |
| 3121 | "bound\n", prim_walk, i); |
| 3122 | return -EINVAL; |
| 3123 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3124 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
| 3125 | dev_err(rdev->dev, "(PW %u) Vertex array %u " |
| 3126 | "need %lu dwords have %lu dwords\n", |
| 3127 | prim_walk, i, size >> 2, |
| 3128 | radeon_bo_size(track->arrays[i].robj) |
| 3129 | >> 2); |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3130 | return -EINVAL; |
| 3131 | } |
| 3132 | } |
| 3133 | break; |
| 3134 | case 3: |
| 3135 | size = track->vtx_size * nverts; |
| 3136 | if (size != track->immd_dwords) { |
| 3137 | DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", |
| 3138 | track->immd_dwords, size); |
| 3139 | DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", |
| 3140 | nverts, track->vtx_size); |
| 3141 | return -EINVAL; |
| 3142 | } |
| 3143 | break; |
| 3144 | default: |
| 3145 | DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", |
| 3146 | prim_walk); |
| 3147 | return -EINVAL; |
| 3148 | } |
| 3149 | return r100_cs_track_texture_check(rdev, track); |
| 3150 | } |
| 3151 | |
| 3152 | void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) |
| 3153 | { |
| 3154 | unsigned i, face; |
| 3155 | |
| 3156 | if (rdev->family < CHIP_R300) { |
| 3157 | track->num_cb = 1; |
| 3158 | if (rdev->family <= CHIP_RS200) |
| 3159 | track->num_texture = 3; |
| 3160 | else |
| 3161 | track->num_texture = 6; |
| 3162 | track->maxy = 2048; |
| 3163 | track->separate_cube = 1; |
| 3164 | } else { |
| 3165 | track->num_cb = 4; |
| 3166 | track->num_texture = 16; |
| 3167 | track->maxy = 4096; |
| 3168 | track->separate_cube = 0; |
| 3169 | } |
| 3170 | |
| 3171 | for (i = 0; i < track->num_cb; i++) { |
| 3172 | track->cb[i].robj = NULL; |
| 3173 | track->cb[i].pitch = 8192; |
| 3174 | track->cb[i].cpp = 16; |
| 3175 | track->cb[i].offset = 0; |
| 3176 | } |
| 3177 | track->z_enabled = true; |
| 3178 | track->zb.robj = NULL; |
| 3179 | track->zb.pitch = 8192; |
| 3180 | track->zb.cpp = 4; |
| 3181 | track->zb.offset = 0; |
| 3182 | track->vtx_size = 0x7F; |
| 3183 | track->immd_dwords = 0xFFFFFFFFUL; |
| 3184 | track->num_arrays = 11; |
| 3185 | track->max_indx = 0x00FFFFFFUL; |
| 3186 | for (i = 0; i < track->num_arrays; i++) { |
| 3187 | track->arrays[i].robj = NULL; |
| 3188 | track->arrays[i].esize = 0x7F; |
| 3189 | } |
| 3190 | for (i = 0; i < track->num_texture; i++) { |
Dave Airlie | d785d78 | 2009-12-07 13:16:06 +1000 | [diff] [blame] | 3191 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 3192 | track->textures[i].pitch = 16536; |
| 3193 | track->textures[i].width = 16536; |
| 3194 | track->textures[i].height = 16536; |
| 3195 | track->textures[i].width_11 = 1 << 11; |
| 3196 | track->textures[i].height_11 = 1 << 11; |
| 3197 | track->textures[i].num_levels = 12; |
| 3198 | if (rdev->family <= CHIP_RS200) { |
| 3199 | track->textures[i].tex_coord_type = 0; |
| 3200 | track->textures[i].txdepth = 0; |
| 3201 | } else { |
| 3202 | track->textures[i].txdepth = 16; |
| 3203 | track->textures[i].tex_coord_type = 1; |
| 3204 | } |
| 3205 | track->textures[i].cpp = 64; |
| 3206 | track->textures[i].robj = NULL; |
| 3207 | /* CS IB emission code makes sure texture unit are disabled */ |
| 3208 | track->textures[i].enabled = false; |
| 3209 | track->textures[i].roundup_w = true; |
| 3210 | track->textures[i].roundup_h = true; |
| 3211 | if (track->separate_cube) |
| 3212 | for (face = 0; face < 5; face++) { |
| 3213 | track->textures[i].cube_info[face].robj = NULL; |
| 3214 | track->textures[i].cube_info[face].width = 16536; |
| 3215 | track->textures[i].cube_info[face].height = 16536; |
| 3216 | track->textures[i].cube_info[face].offset = 0; |
| 3217 | } |
| 3218 | } |
| 3219 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 3220 | |
| 3221 | int r100_ring_test(struct radeon_device *rdev) |
| 3222 | { |
| 3223 | uint32_t scratch; |
| 3224 | uint32_t tmp = 0; |
| 3225 | unsigned i; |
| 3226 | int r; |
| 3227 | |
| 3228 | r = radeon_scratch_get(rdev, &scratch); |
| 3229 | if (r) { |
| 3230 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); |
| 3231 | return r; |
| 3232 | } |
| 3233 | WREG32(scratch, 0xCAFEDEAD); |
| 3234 | r = radeon_ring_lock(rdev, 2); |
| 3235 | if (r) { |
| 3236 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
| 3237 | radeon_scratch_free(rdev, scratch); |
| 3238 | return r; |
| 3239 | } |
| 3240 | radeon_ring_write(rdev, PACKET0(scratch, 0)); |
| 3241 | radeon_ring_write(rdev, 0xDEADBEEF); |
| 3242 | radeon_ring_unlock_commit(rdev); |
| 3243 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 3244 | tmp = RREG32(scratch); |
| 3245 | if (tmp == 0xDEADBEEF) { |
| 3246 | break; |
| 3247 | } |
| 3248 | DRM_UDELAY(1); |
| 3249 | } |
| 3250 | if (i < rdev->usec_timeout) { |
| 3251 | DRM_INFO("ring test succeeded in %d usecs\n", i); |
| 3252 | } else { |
| 3253 | DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", |
| 3254 | scratch, tmp); |
| 3255 | r = -EINVAL; |
| 3256 | } |
| 3257 | radeon_scratch_free(rdev, scratch); |
| 3258 | return r; |
| 3259 | } |
| 3260 | |
| 3261 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
| 3262 | { |
| 3263 | radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); |
| 3264 | radeon_ring_write(rdev, ib->gpu_addr); |
| 3265 | radeon_ring_write(rdev, ib->length_dw); |
| 3266 | } |
| 3267 | |
| 3268 | int r100_ib_test(struct radeon_device *rdev) |
| 3269 | { |
| 3270 | struct radeon_ib *ib; |
| 3271 | uint32_t scratch; |
| 3272 | uint32_t tmp = 0; |
| 3273 | unsigned i; |
| 3274 | int r; |
| 3275 | |
| 3276 | r = radeon_scratch_get(rdev, &scratch); |
| 3277 | if (r) { |
| 3278 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); |
| 3279 | return r; |
| 3280 | } |
| 3281 | WREG32(scratch, 0xCAFEDEAD); |
| 3282 | r = radeon_ib_get(rdev, &ib); |
| 3283 | if (r) { |
| 3284 | return r; |
| 3285 | } |
| 3286 | ib->ptr[0] = PACKET0(scratch, 0); |
| 3287 | ib->ptr[1] = 0xDEADBEEF; |
| 3288 | ib->ptr[2] = PACKET2(0); |
| 3289 | ib->ptr[3] = PACKET2(0); |
| 3290 | ib->ptr[4] = PACKET2(0); |
| 3291 | ib->ptr[5] = PACKET2(0); |
| 3292 | ib->ptr[6] = PACKET2(0); |
| 3293 | ib->ptr[7] = PACKET2(0); |
| 3294 | ib->length_dw = 8; |
| 3295 | r = radeon_ib_schedule(rdev, ib); |
| 3296 | if (r) { |
| 3297 | radeon_scratch_free(rdev, scratch); |
| 3298 | radeon_ib_free(rdev, &ib); |
| 3299 | return r; |
| 3300 | } |
| 3301 | r = radeon_fence_wait(ib->fence, false); |
| 3302 | if (r) { |
| 3303 | return r; |
| 3304 | } |
| 3305 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 3306 | tmp = RREG32(scratch); |
| 3307 | if (tmp == 0xDEADBEEF) { |
| 3308 | break; |
| 3309 | } |
| 3310 | DRM_UDELAY(1); |
| 3311 | } |
| 3312 | if (i < rdev->usec_timeout) { |
| 3313 | DRM_INFO("ib test succeeded in %u usecs\n", i); |
| 3314 | } else { |
| 3315 | DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", |
| 3316 | scratch, tmp); |
| 3317 | r = -EINVAL; |
| 3318 | } |
| 3319 | radeon_scratch_free(rdev, scratch); |
| 3320 | radeon_ib_free(rdev, &ib); |
| 3321 | return r; |
| 3322 | } |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3323 | |
| 3324 | void r100_ib_fini(struct radeon_device *rdev) |
| 3325 | { |
| 3326 | radeon_ib_pool_fini(rdev); |
| 3327 | } |
| 3328 | |
| 3329 | int r100_ib_init(struct radeon_device *rdev) |
| 3330 | { |
| 3331 | int r; |
| 3332 | |
| 3333 | r = radeon_ib_pool_init(rdev); |
| 3334 | if (r) { |
| 3335 | dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r); |
| 3336 | r100_ib_fini(rdev); |
| 3337 | return r; |
| 3338 | } |
| 3339 | r = r100_ib_test(rdev); |
| 3340 | if (r) { |
| 3341 | dev_err(rdev->dev, "failled testing IB (%d).\n", r); |
| 3342 | r100_ib_fini(rdev); |
| 3343 | return r; |
| 3344 | } |
| 3345 | return 0; |
| 3346 | } |
| 3347 | |
| 3348 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) |
| 3349 | { |
| 3350 | /* Shutdown CP we shouldn't need to do that but better be safe than |
| 3351 | * sorry |
| 3352 | */ |
| 3353 | rdev->cp.ready = false; |
| 3354 | WREG32(R_000740_CP_CSQ_CNTL, 0); |
| 3355 | |
| 3356 | /* Save few CRTC registers */ |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 3357 | save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3358 | save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); |
| 3359 | save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); |
| 3360 | save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); |
| 3361 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| 3362 | save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); |
| 3363 | save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); |
| 3364 | } |
| 3365 | |
| 3366 | /* Disable VGA aperture access */ |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 3367 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3368 | /* Disable cursor, overlay, crtc */ |
| 3369 | WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); |
| 3370 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | |
| 3371 | S_000054_CRTC_DISPLAY_DIS(1)); |
| 3372 | WREG32(R_000050_CRTC_GEN_CNTL, |
| 3373 | (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | |
| 3374 | S_000050_CRTC_DISP_REQ_EN_B(1)); |
| 3375 | WREG32(R_000420_OV0_SCALE_CNTL, |
| 3376 | C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); |
| 3377 | WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); |
| 3378 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| 3379 | WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | |
| 3380 | S_000360_CUR2_LOCK(1)); |
| 3381 | WREG32(R_0003F8_CRTC2_GEN_CNTL, |
| 3382 | (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | |
| 3383 | S_0003F8_CRTC2_DISPLAY_DIS(1) | |
| 3384 | S_0003F8_CRTC2_DISP_REQ_EN_B(1)); |
| 3385 | WREG32(R_000360_CUR2_OFFSET, |
| 3386 | C_000360_CUR2_LOCK & save->CUR2_OFFSET); |
| 3387 | } |
| 3388 | } |
| 3389 | |
| 3390 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) |
| 3391 | { |
| 3392 | /* Update base address for crtc */ |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 3393 | WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3394 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 3395 | WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3396 | } |
| 3397 | /* Restore CRTC registers */ |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 3398 | WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 3399 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); |
| 3400 | WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); |
| 3401 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| 3402 | WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); |
| 3403 | } |
| 3404 | } |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 3405 | |
| 3406 | void r100_vga_render_disable(struct radeon_device *rdev) |
| 3407 | { |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3408 | u32 tmp; |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 3409 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3410 | tmp = RREG8(R_0003C2_GENMO_WT); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 3411 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); |
| 3412 | } |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3413 | |
| 3414 | static void r100_debugfs(struct radeon_device *rdev) |
| 3415 | { |
| 3416 | int r; |
| 3417 | |
| 3418 | r = r100_debugfs_mc_info_init(rdev); |
| 3419 | if (r) |
| 3420 | dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); |
| 3421 | } |
| 3422 | |
| 3423 | static void r100_mc_program(struct radeon_device *rdev) |
| 3424 | { |
| 3425 | struct r100_mc_save save; |
| 3426 | |
| 3427 | /* Stops all mc clients */ |
| 3428 | r100_mc_stop(rdev, &save); |
| 3429 | if (rdev->flags & RADEON_IS_AGP) { |
| 3430 | WREG32(R_00014C_MC_AGP_LOCATION, |
| 3431 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
| 3432 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
| 3433 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
| 3434 | if (rdev->family > CHIP_RV200) |
| 3435 | WREG32(R_00015C_AGP_BASE_2, |
| 3436 | upper_32_bits(rdev->mc.agp_base) & 0xff); |
| 3437 | } else { |
| 3438 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); |
| 3439 | WREG32(R_000170_AGP_BASE, 0); |
| 3440 | if (rdev->family > CHIP_RV200) |
| 3441 | WREG32(R_00015C_AGP_BASE_2, 0); |
| 3442 | } |
| 3443 | /* Wait for mc idle */ |
| 3444 | if (r100_mc_wait_for_idle(rdev)) |
| 3445 | dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); |
| 3446 | /* Program MC, should be a 32bits limited address space */ |
| 3447 | WREG32(R_000148_MC_FB_LOCATION, |
| 3448 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
| 3449 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| 3450 | r100_mc_resume(rdev, &save); |
| 3451 | } |
| 3452 | |
| 3453 | void r100_clock_startup(struct radeon_device *rdev) |
| 3454 | { |
| 3455 | u32 tmp; |
| 3456 | |
| 3457 | if (radeon_dynclks != -1 && radeon_dynclks) |
| 3458 | radeon_legacy_set_clock_gating(rdev, 1); |
| 3459 | /* We need to force on some of the block */ |
| 3460 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); |
| 3461 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); |
| 3462 | if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) |
| 3463 | tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); |
| 3464 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); |
| 3465 | } |
| 3466 | |
| 3467 | static int r100_startup(struct radeon_device *rdev) |
| 3468 | { |
| 3469 | int r; |
| 3470 | |
Alex Deucher | 92cde00 | 2009-12-04 10:55:12 -0500 | [diff] [blame] | 3471 | /* set common regs */ |
| 3472 | r100_set_common_regs(rdev); |
| 3473 | /* program mc */ |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3474 | r100_mc_program(rdev); |
| 3475 | /* Resume clock */ |
| 3476 | r100_clock_startup(rdev); |
| 3477 | /* Initialize GPU configuration (# pipes, ...) */ |
| 3478 | r100_gpu_init(rdev); |
| 3479 | /* Initialize GART (initialize after TTM so we can allocate |
| 3480 | * memory through TTM but finalize after TTM) */ |
Dave Airlie | 17e15b0 | 2009-11-05 15:36:53 +1000 | [diff] [blame] | 3481 | r100_enable_bm(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3482 | if (rdev->flags & RADEON_IS_PCI) { |
| 3483 | r = r100_pci_gart_enable(rdev); |
| 3484 | if (r) |
| 3485 | return r; |
| 3486 | } |
| 3487 | /* Enable IRQ */ |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3488 | r100_irq_set(rdev); |
Jerome Glisse | cafe660 | 2010-01-07 12:39:21 +0100 | [diff] [blame] | 3489 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3490 | /* 1M ring buffer */ |
| 3491 | r = r100_cp_init(rdev, 1024 * 1024); |
| 3492 | if (r) { |
| 3493 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
| 3494 | return r; |
| 3495 | } |
| 3496 | r = r100_wb_init(rdev); |
| 3497 | if (r) |
| 3498 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
| 3499 | r = r100_ib_init(rdev); |
| 3500 | if (r) { |
| 3501 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| 3502 | return r; |
| 3503 | } |
| 3504 | return 0; |
| 3505 | } |
| 3506 | |
| 3507 | int r100_resume(struct radeon_device *rdev) |
| 3508 | { |
| 3509 | /* Make sur GART are not working */ |
| 3510 | if (rdev->flags & RADEON_IS_PCI) |
| 3511 | r100_pci_gart_disable(rdev); |
| 3512 | /* Resume clock before doing reset */ |
| 3513 | r100_clock_startup(rdev); |
| 3514 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| 3515 | if (radeon_gpu_reset(rdev)) { |
| 3516 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 3517 | RREG32(R_000E40_RBBM_STATUS), |
| 3518 | RREG32(R_0007C0_CP_STAT)); |
| 3519 | } |
| 3520 | /* post */ |
| 3521 | radeon_combios_asic_init(rdev->ddev); |
| 3522 | /* Resume clock after posting */ |
| 3523 | r100_clock_startup(rdev); |
Dave Airlie | 550e2d9 | 2009-12-09 14:15:38 +1000 | [diff] [blame] | 3524 | /* Initialize surface registers */ |
| 3525 | radeon_surface_init(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3526 | return r100_startup(rdev); |
| 3527 | } |
| 3528 | |
| 3529 | int r100_suspend(struct radeon_device *rdev) |
| 3530 | { |
| 3531 | r100_cp_disable(rdev); |
| 3532 | r100_wb_disable(rdev); |
| 3533 | r100_irq_disable(rdev); |
| 3534 | if (rdev->flags & RADEON_IS_PCI) |
| 3535 | r100_pci_gart_disable(rdev); |
| 3536 | return 0; |
| 3537 | } |
| 3538 | |
| 3539 | void r100_fini(struct radeon_device *rdev) |
| 3540 | { |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 3541 | radeon_pm_fini(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3542 | r100_cp_fini(rdev); |
| 3543 | r100_wb_fini(rdev); |
| 3544 | r100_ib_fini(rdev); |
| 3545 | radeon_gem_fini(rdev); |
| 3546 | if (rdev->flags & RADEON_IS_PCI) |
| 3547 | r100_pci_gart_fini(rdev); |
Jerome Glisse | d0269ed | 2010-01-07 16:08:32 +0100 | [diff] [blame] | 3548 | radeon_agp_fini(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3549 | radeon_irq_kms_fini(rdev); |
| 3550 | radeon_fence_driver_fini(rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3551 | radeon_bo_fini(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3552 | radeon_atombios_fini(rdev); |
| 3553 | kfree(rdev->bios); |
| 3554 | rdev->bios = NULL; |
| 3555 | } |
| 3556 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3557 | int r100_init(struct radeon_device *rdev) |
| 3558 | { |
| 3559 | int r; |
| 3560 | |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3561 | /* Register debugfs file specific to this group of asics */ |
| 3562 | r100_debugfs(rdev); |
| 3563 | /* Disable VGA */ |
| 3564 | r100_vga_render_disable(rdev); |
| 3565 | /* Initialize scratch registers */ |
| 3566 | radeon_scratch_init(rdev); |
| 3567 | /* Initialize surface registers */ |
| 3568 | radeon_surface_init(rdev); |
| 3569 | /* TODO: disable VGA need to use VGA request */ |
| 3570 | /* BIOS*/ |
| 3571 | if (!radeon_get_bios(rdev)) { |
| 3572 | if (ASIC_IS_AVIVO(rdev)) |
| 3573 | return -EINVAL; |
| 3574 | } |
| 3575 | if (rdev->is_atom_bios) { |
| 3576 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
| 3577 | return -EINVAL; |
| 3578 | } else { |
| 3579 | r = radeon_combios_init(rdev); |
| 3580 | if (r) |
| 3581 | return r; |
| 3582 | } |
| 3583 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| 3584 | if (radeon_gpu_reset(rdev)) { |
| 3585 | dev_warn(rdev->dev, |
| 3586 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 3587 | RREG32(R_000E40_RBBM_STATUS), |
| 3588 | RREG32(R_0007C0_CP_STAT)); |
| 3589 | } |
| 3590 | /* check if cards are posted or not */ |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 3591 | if (radeon_boot_test_post_card(rdev) == false) |
| 3592 | return -EINVAL; |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3593 | /* Set asic errata */ |
| 3594 | r100_errata(rdev); |
| 3595 | /* Initialize clocks */ |
| 3596 | radeon_get_clock_info(rdev->ddev); |
Rafał Miłecki | 6234077 | 2009-12-15 21:46:58 +0100 | [diff] [blame] | 3597 | /* Initialize power management */ |
| 3598 | radeon_pm_init(rdev); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 3599 | /* initialize AGP */ |
| 3600 | if (rdev->flags & RADEON_IS_AGP) { |
| 3601 | r = radeon_agp_init(rdev); |
| 3602 | if (r) { |
| 3603 | radeon_agp_disable(rdev); |
| 3604 | } |
| 3605 | } |
| 3606 | /* initialize VRAM */ |
| 3607 | r100_mc_init(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3608 | /* Fence driver */ |
| 3609 | r = radeon_fence_driver_init(rdev); |
| 3610 | if (r) |
| 3611 | return r; |
| 3612 | r = radeon_irq_kms_init(rdev); |
| 3613 | if (r) |
| 3614 | return r; |
| 3615 | /* Memory manager */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 3616 | r = radeon_bo_init(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3617 | if (r) |
| 3618 | return r; |
| 3619 | if (rdev->flags & RADEON_IS_PCI) { |
| 3620 | r = r100_pci_gart_init(rdev); |
| 3621 | if (r) |
| 3622 | return r; |
| 3623 | } |
| 3624 | r100_set_safe_registers(rdev); |
| 3625 | rdev->accel_working = true; |
| 3626 | r = r100_startup(rdev); |
| 3627 | if (r) { |
| 3628 | /* Somethings want wront with the accel init stop accel */ |
| 3629 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3630 | r100_cp_fini(rdev); |
| 3631 | r100_wb_fini(rdev); |
| 3632 | r100_ib_fini(rdev); |
Jerome Glisse | 655efd3 | 2010-02-02 11:51:45 +0100 | [diff] [blame] | 3633 | radeon_irq_kms_fini(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3634 | if (rdev->flags & RADEON_IS_PCI) |
| 3635 | r100_pci_gart_fini(rdev); |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 3636 | rdev->accel_working = false; |
| 3637 | } |
| 3638 | return 0; |
| 3639 | } |